EP1939887B1 - DRAM with disabled refresh in test mode - Google Patents

DRAM with disabled refresh in test mode Download PDF

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Publication number
EP1939887B1
EP1939887B1 EP07150438.5A EP07150438A EP1939887B1 EP 1939887 B1 EP1939887 B1 EP 1939887B1 EP 07150438 A EP07150438 A EP 07150438A EP 1939887 B1 EP1939887 B1 EP 1939887B1
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EP
European Patent Office
Prior art keywords
refresh
signal
data
mask
test
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EP07150438.5A
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German (de)
English (en)
French (fr)
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EP1939887A1 (en
Inventor
Masaki c/o FUJITSU LIMITED Okuda
Atsushi c/o FUJITSU LIMITED Fujii
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Definitions

  • the present invention relates to a semiconductor memory having memory cells of DRAM and an interface of SRAM.
  • a pseudo SRAM has memory cells of DRAM (dynamic memory cells) and operates as SRAM by internally and automatically executing a refresh operation of memory cells.
  • the pseudo SRAM executes the refresh operation without being recognized by a controller such as CPU, during a period in which a read operation or a write operation of a memory core is not executed.
  • the refresh operation is executed in response to an internal refresh request which occurs periodically inside the pseudo SRAM.
  • an access cycle time which is a minimum supply interval for an access command (read command or write command) is set to a time obtained by adding a refresh operation time of the memory core to a read operation time or a write operation time of the memory core.
  • US 2006/0023547 A1 discloses a timer that measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed.
  • the external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate.
  • the predetermined time is set to be longer than a core operation time for the memory core to perform a single operation.
  • the memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time.
  • EP 1 235 228 A1 discloses a semiconductor memory device incorporating memory cells the same as for DRAM and which operates under SRAM specification, where the chip size is small and power consumption and cost are low, and for which access delay or memory cell data destruction due to skew incorporated in an address does not arise.
  • An ATD circuit generates a one shot pulse for an address transition detection signal from transition of an externally supplied address. At this time, by generating the one shot pulse for each bit of the address and then combining these, then even in the case where the address contains a skew, the one shot pulse is only generated once. At first, refresh is performed during the generation period of the one shot pulse, using a refresh address generated by a refresh control circuit. Then, on receipt of a fall in the one shot pulse, a latch control signal is generated, the address is latched by the latch and the memory cell array accessed.
  • a semi conducteur memory according to the invention is defined in claim 1 and an operating method of a semiconductor memory according to the invention is defined in claim 9.
  • each signal line shown by the heavy line is constituted of a plurality of lines. Further, part of blocks to which the heavy lines are connected is constituted of a plurality of circuits. Each signal line through which the signal is transmitted is denoted by the same reference symbol as the signal name. Each signal starting with "/" represents negative logic. Each signal ending with “Z” represents positive logic. Each double circle in the drawings represents an external terminal.
  • FIG. 1 shows an embodiment of the present invention.
  • a semiconductor memory MEM is, for example, an FCRAM (Fast Cycle RAM) with an asynchronous clock.
  • the FCRAM is a pseudo SRAM which has memory cells of DRAM and has an interface of SRAM.
  • the memory MEM has an access control circuit 10, a refresh control circuit 12, a mode register 14, a row address control circuit 16, a column address control circuit 18, a data control circuit 20 and a memory core 22.
  • the access control circuit 10 receives at an external terminal a control signal (chip enable signal /CE, write enable signal /WE, output enable signal /OE, upper-byte control signal/UB, lower-byte control signal/LB) for causing the memory MEM to perform an access operation. Also, the access control circuit 10 receives an active signal ACTZ for causing the memory MEM to execute a read operation or a write operation and a refresh control signal REFZ for causing the memory MEM to execute a refresh operation.
  • a control signal chip enable signal /CE, write enable signal /WE, output enable signal /OE, upper-byte control signal/UB, lower-byte control signal/LB
  • the access control circuit 10 outputs, according to a received control signal, a read control signal RDZ, a write control signal WRZ or a mode register set signal MRSZ and data control signals UBZ, LBZ, and outputs, according to the received active signal ACTZ or refresh control signal REFZ, a precharge control signal PREZ, a word control signal WLZ, a sense amplifier activation signal LEZ, a column control signal CLZ.
  • the read control signal RDZ read command, read request
  • the write control signal WRZ write command, write request
  • the refresh control circuit 12 outputs the active signal ACTZ in response to the read command RDZ or the write command WRZ, and outputs the refresh control signal REFZ in response to a refresh request (RREQ0Z in Fig. 2 ) which is generated by itself.
  • the refresh control circuit 12 judges, when the read command RDZ or the write command WRZ conflicts with the refresh request, which of a read operation or write operation and a refresh operation is to be executed first, and outputs the active signal ACTZ and the refresh control signal REFZ sequentially according to the determined order.
  • the refresh control circuit 12 outputs an address selection signal ASELZ during execution of the refresh operation.
  • the refresh control circuit 12 prohibits the output of the refresh control signal REFZ in response to a refresh request signal RREQ0Z while a test mode signal TMZ is activated (during a test mode), and outputs the refresh control signal REFZ in response to the read command RDZ or the write command WRZ. However, the refresh control circuit 12 prohibits the output of the refresh control signal REFZ in response to the read command RDZ or the write command WRZ when a refresh mask signal RMSKZ is activated.
  • a refresh mask terminal RMSKZ is a dedicated terminal for receiving the refresh mask signal RMSKZ, and is formed as a test pad for example.
  • the test pad is, as shown in Fig. 6 , a terminal for connecting a probe PRB of an LSI tester TEST when the memory MEM in a wafer state WAF is tested.
  • the refresh mask terminal RMSKZ is not connected to an external terminal (lead) of the packaged memory MEM as different from other control terminals.
  • the refresh mask terminal RMSKZ is connected to a ground line VSS via a resistor R1. Accordingly, in the packaged memory MEM, the refresh mask signal RMSKZ is always inactivated. Details of the refresh control circuit 12 are shown in Fig. 3 . Also, operations of the test mode are shown in Fig. 8 and Fig. 9 .
  • the mode register 14 is set according to values of address signals RAD, CAD supplied in synchronization with the mode register set signal MRSZ.
  • the mode resister 14 activates the test mode signal TMZ to a high logic level when a predetermined bit (test mode bit) in the address signals RAD, CAD indicates entry to the test mode.
  • the memory MEM changes from a normal operation mode to the test mode.
  • the mode register 14 inactivates the test mode signal TMZ to a low logic level when the test mode bit indicates exit from the test mode. By the inactivation of the test mode signal TMZ, the memory MEM returns from the test mode to the normal operation mode.
  • test mode bit of the mode register 14 is reset when the power of the memory MEM is turned on, and inactivates the test mode signal TMZ.
  • the operation mode of the memory MEM is set to the normal operation mode when the power is turned on.
  • the mode register 14 has bits for setting other operation modes of the memory MEM.
  • the column address control circuit 18 decodes a column address signal CAD supplied to the address terminal AD in synchronization with a read command or a write command, and outputs this signal as a column decode signal DCAD.
  • This memory MEM is a memory of address non-multiplex type in which the row address signal RAD and the column address signal CAD are supplied simultaneously.
  • the data control circuit 20 receives a write data signal at a data terminal DQ, and outputs the received data signal to a column switch CSW via a data bus DB. Also, the data control circuit 20 receives a read data signal from a memory cell MC via the data bus DB, and outputs the received data signal to the data terminal DQ.
  • the data terminal DQ is constituted of 16 bits (2 bytes) for example.
  • a data signal DQ0-7 of the lower one byte is inputted/outputted while the lower-byte control signal /LB (data mask signal) is activated.
  • a data signal DQ7-15 of the higher one byte is inputted/outputted while the upper-byte control signal/UB (data mask signal) is activated.
  • the memory core 22 has a memory cell array ARY, a word decoder WS, a sense amplifier SA, a column switch CSW and a not-shown precharge circuit.
  • the memory cell array ARY has a plurality of dynamic memory cells MC, word lines WL connected to memory cells MC which are arranged in one direction, and bit lines BL, /BL connected to memory cells MC which are arranged in a direction orthogonal to the one direction.
  • the memory cells MC have a capacitor for retaining data as an electric charge and a transfer transistor for connecting one end of the capacitor to the bit line BL (or /BL). The other end of the capacitor is connected to a precharge voltage line or an internal power supply line. Gates of the transfer transistors are connected to the word lines WL.
  • the word decoder WD selects one of the word lines WL according to the row decode signal DRAD.
  • the word lines WL are selected while the word control signal WLZ is activated.
  • the sense amplifier SA amplifies a difference in signal amounts of data signals read to a pair of the bit lines BL, /BL.
  • the sense amplifier SA executes an amplification operation while the sense amplifier activation signal LEZ is activated.
  • the column switch CSW turns on according to a column decode signal DCAD, and connects the bit lines BL, /BL to the data bus DB via a read amplifier and a write amplifier which are not shown.
  • the column switch CSW turns on while the column control signal CLZ is activated.
  • the not-shown precharge circuit has a switch which turns on while the precharge control signal PREZ is activated (when the memory cells MC are not accessed), and connects the bit lines BL, /BL to the precharge voltage line.
  • the overview of operations of the memory core 22 is shown in Fig. 5 .
  • Fig. 2 shows details of the access control circuit 10 shown in Fig. 1 .
  • the access control circuit 10 has an input buffer INBUF, a command decoder CDEC, a basic timing generating circuit BTGEN and a core control circuit CCNT.
  • the input buffer INBUF receives the /CE signal, the /WE signal, the /OE signal, the /UB signal and the /LB signal, and inverts the logic levels of the received signals and outputs these signals as internal control signals CEZ, WEZ, OEZ, UBZ and LBZ.
  • the command decoder CDEC recognizes a command according to the logic level of the internal control signal CEZ, WEZ, OEZ and outputs, according to the recognized command, the read control signal RDZ (read command), the write control signal WRZ (write command) or the mode register set signal MRSZ.
  • the read command and the write command are external access commands for executing an access operation of the memory core 22.
  • the basic timing generating circuit BTGEN outputs a row basic timing signal RASZ in synchronization with the active signal ACTZ or the refresh control signal REFZ.
  • the core control circuit CCNT generates the precharge control signal PREZ, the word control signal WLZ, the sense amplifier activation signal LEZ and the column control signal CLZ sequentially in synchronization with the row basic timing signal RASZ. Generation timings of these control signals PREZ, WLZ, LEZ and CLZ are shown in Fig. 5 .
  • Fig. 3 shows details of the refresh control circuit 12 shown in Fig. 1 .
  • the refresh control circuit 12 has a refresh generating circuit REFGEN, a pulse generating circuit PLS, a mask circuit MSK, a selector SEL, an arbiter ARB and a logic gate connected to these circuits.
  • the refresh generating circuit REFGEN has an oscillator which generates the internal refresh request signal RREQ0Z periodically.
  • the pulse generating circuit PLS generates a command pulse signal COMP (test refresh request signal) having a pulse of a high logic level in synchronization with an access command (read control signal RDZ or write control signal WRZ).
  • the mask circuit MSK outputs the command pulse signal COMP as a command pulse enable signal COMPE (test refresh request signal) when receiving the refresh mask signal RMSKZ at a low logic level, and sets the command pulse enable signal COMPE to a low logic level when receiving the refresh mask signal RMSKZ at a high logic level. Specifically, when the refresh mask signal RMSKZ is at a valid level, generation of the command pulse enable signal COMPE is prohibited even when the read command RDZ or the write command WRZ is generated.
  • the selector SEL outputs the internal refresh request signal RREQ0Z as a refresh request signal RREQZ when the test mode signal TMZ is at a low logic level (normal operation mode), and outputs the command pulse enable signal COMPE as the refresh request signal RREQZ when the test mode signal TMZ is at a high logic level (test mode).
  • the arbiter ARB determines which of a read/write command signal RWZ indicating the read command RDZ or the write command WRZ and the refresh request RREQZ should be given priority, and outputs the active signal ACTV or the refresh control signal REFZ according to the order of priority.
  • the arbiter ARB when the arbiter ARB receives the read command RDZ (RWZ) and the refresh request RREQZ at the same time, the arbiter ARB gives priority to the refresh request RREQZ. A read operation responding to the read command RDZ is suspended until a refresh operation responding to the refresh request RREQZ is completed. In reverse, when the refresh request RREQZ is supplied during a read operation, a refresh operation responding to the refresh request RREQZ is suspended until the read operation is completed. The same applies to the write command WRZ. Further, in synchronization with the refresh control signal REFZ, the arbiter ARB activates the address selection signal ASELZ indicating that the refresh operation is being executed.
  • the address selection signal ASELZ is activated from just before the refresh operation starts until the refresh operation finishes.
  • the arbiter ARB has a function to determine which of an access operation and a refresh operation is to be executed first when an access command conflicts with the internal refresh request signal RREQ0Z or the test refresh request signal COMPE.
  • Fig. 4 shows details of the row address control circuit 16 shown in Fig. 1 .
  • the row address control circuit 16 has a delay circuit DLY, a refresh address counter RAC, a row address buffer RAB, a selector SEL and a row decoder RDEC.
  • the refresh address counter RAC counts up in synchronization with the refresh control signal REFZ delayed by the delay circuit DLY, and generates a refresh address signal RXAD sequentially.
  • the refresh address signal RXAD is a row address signal having the same number of bits as the row address signal RAD. Note that the refresh address counter RAC may also be counted down.
  • the delay circuit DLY is provided for updating the value of the refresh address counter RAC after the refresh operation responding to the refresh control signal REFZ is completed.
  • the row address buffer RAB receives the row address signal RAD and outputs the received signal as an internal row address signal XAD.
  • the selector SEL selects the internal row address signal XAD when receiving the address selection signal ASELZ at a low logic level, and selects the refresh address signal RXAD when receiving the address selection signal ASELZ at a high logic level, and outputs a selected signal to the row decoder RDEC.
  • the row decoder RDEC decodes the address signal supplied from the selector SEL, and outputs this signal as a row decode signal DRAD.
  • Fig. 5 shows the overview of operations of the semiconductor memory MEM of the embodiment.
  • “H” denotes a high logic level and “L” denotes a low logic level
  • “X” denotes that either of “L” and “H” is possible
  • “L/H” denotes setting to either one of “L” and “H”.
  • the memory MEM turns to a standby state STBY, and an operation other than a refresh operation REF is not executed.
  • the refresh control signal REFZ is activated in response to activation of the refresh request signal RREQ0Z.
  • the memory MEM turns to an active state, and one of a read operation RD, a write operation WR, a refresh operation REF and a mode register set operation MRS is executed.
  • the read operation RD is executed by activation of the read control signal RDZ when the /WE signal and the /OE signal are at an H level and an L level respectively.
  • the write operation WR is executed by activation of the write control signal WRZ when the /WE signal and the /OE signal are at an L level and an H level respectively.
  • the refresh operation REF is executed when the refresh request signal RREQ0Z is activated, regardless of levels of the external control signals /CE, /WE, /OE, /LB, /UB.
  • the mode register set operation MRS is executed by activation of the mode register set signal MRSZ when, for example, both the /WE signal and the /OE signal are at an L level.
  • the precharge signal PREZ is inactivated in response to the external access command signals RDZ, WRZ or the internal refresh request signal RREQ0Z, and thereafter, the word control signal WLZ, the sense amplifier activation signal LEZ and the column control signal CLZ are activated sequentially. Then, in the read operation RD, read data DOUT are outputted to the data terminal DQ, and in the write operation WR, write data DIN are supplied to the data terminal DQ.
  • the refresh operation REF a read data signal which is read from a memory cell MC and amplified by the sense amplifier SA is not outputted to the data terminal DQ but written back to the memory cell MC.
  • the read operation RD finishes in response to inactivation of the /CE signal or the /OE signal.
  • the write operation WR finishes in response to inactivation of the /CE signal or the /WE signal.
  • the refresh operation REF finishes automatically by control of the access control circuit 10.
  • Fig. 6 shows a test environment of the embodiment.
  • a plurality of memories MEM are formed on a semiconductor wafer WAF through a semiconductor manufacturing process.
  • the memories MEM are tested by an LSI tester TEST before being cut off from the wafer WAF. From the LSI tester TEST, not only a control signal but also power supply voltage VDD and ground voltage VSS are supplied.
  • the memories MEM are connected to the LSI tester TEST via, for example, a probe PRB of a not-shown probe card.
  • one memory MEM is connected to the LST tester TEST, but a plurality of (four for example) memories MEM may be connected at once to the LSI tester TEST.
  • the number of memories MEM connected to the LSI tester TEST at once depends on the number of terminals of the LSI tester TEST and the number of terminals of a memory MEM.
  • the refresh mask signal RMSKZ is supplied from the LSI tester TEST together with the control signals /CE, /WE, /OE, /UB, /LB and the address signal AD.
  • a write command WR and a read command RD are supplied sequentially to the memory MEM.
  • a write address signal AD1 is supplied in synchronization with the write command WR
  • a read address signal AD2 is supplied in synchronization with the read command RD.
  • the internal refresh request signal RREQ0Z is outputted just before the write command WR is received ( Fig 7 (a) ).
  • the refresh control circuit 12 outputs the internal refresh request signal RREQ0Z as the refresh request signal RREQZ ( Fig. 7 (b) ).
  • the arbiter ARB determines to execute the refresh request with higher priority than the write command WR, and outputs the refresh control signal REFZ ( Fig. 7 (c) ).
  • the access control circuit 10 outputs the row basic timing signal RASZ in response to the refresh control signal REFZ ( Fig. 7 (d) ). Then, the word line WL is activated and the refresh operation REF is executed ( Fig. 7 (e) ).
  • the refresh operation REF is executed using the refresh address signal RXAD generated by the refresh address counter RAC.
  • the refresh control circuit 12 outputs a command pulse signal COMP in response to the write command WR ( Fig. 7 (f) ). Since the refresh mask signal RMSKZ is fixed to a low logic level L, the command pulse enable signal COMPE is outputted in response to the command pulse signal COMP ( Fig. 7 (g) ). However, in the normal operation mode, by the function of the selector SEL of the refresh control circuit 12, the refresh request signal RREQZ will not be outputted in response to the command pulse enable signal COMPE.
  • the write data signal DIN is supplied to the data terminal DQ ( Fig. 7 (h) ).
  • the arbiter ARB outputs the active signal ACTZ in response to finish of the refresh operation REF ( Fig. 7 (i) ).
  • the access control circuit 10 outputs the row basic timing signal RASZ in response to the active signal ACTZ ( Fig. 7 (j) ).
  • the word line WL is activated, and the write operation WR is executed ( Fig. 7 (k) ).
  • the write operation WR finishes by inactivation of the /CE signal.
  • a specification of the write access cycle time required for one write operation WR is TC1.
  • the access cycle time TC1 is an external timing specification which the system accessing the memory MEM has to conform, and indicates a minimum supply interval of the write command WR or the read command RD.
  • the memory MEM in this embodiment is designed to be capable of executing one write operation WR and one refresh operation REF within the access cycle time TC1. Thus, the system accessing the memory MEM needs not to be conscious of a refresh operation and can access the memory MEM as an SRAM.
  • the read command RD is supplied.
  • the internal refresh request signal RREQ0Z is generated, for example, once in a few ⁇ s to a few tens of ⁇ s. Accordingly, in Fig. 7 , conflict of the read command RD with the refresh request does not occur. Since the internal refresh request signal RREQ0Z has not occur, the arbiter ARB outputs the active signal ACTZ in response to the read command RD ( Fig. 7 (l) ). Thereafter, similarly to the write operation WR, the row basic timing signal RASZ is outputted ( Fig. 7 (m) ), the word line WL is activated, and the read operation RD is executed ( Fig. 7 (n) ).
  • the read operation RD finishes by inactivation of the /CE signal.
  • the access cycle time required for one read operation RD is TC1, similarly to the write operation WR.
  • the memory MEM in this embodiment is designed to be capable of executing one read operation RD and one refresh operation REF within the access cycle time TCl, similarly to the write operation WR.
  • the refresh operation REF is executed just before the read operation RD.
  • Timings of the refresh operation REF and the read operation RD at this time are the same as the above described (b) to (k) except the data signal DQ.
  • the read data signal DOUT is outputted in synchronization with activation of the not-shown column control signal CLZ after the word line WL is activated along with the read operation RD.
  • the write command WR and the read command RD are supplied sequentially to the memory MEM.
  • the write address signal AD1 and the read address signal AD2 are the same as those in Fig. 7 .
  • the selector SEL of the refresh control circuit 12 prohibits output of the refresh control signal REFZ in response to the internal refresh request signal RREQ0Z during the test mode.
  • the refresh control signal REFZ can be generated in response to the write command WR or the read command RD during the test mode.
  • the refresh control signal REFZ is not generated in response to the write command WR but generated in response to the read command RD.
  • the LSI tester TEST which tests the memory MEM sets the refresh mask signal RMSKZ to a high logic level (valid level) in synchronization with supply of the write command WR ( Fig. 8 (a) ), so as to prevent generation of the refresh control signal REFZ in response to the write command WR.
  • the high logic level period of the refresh mask signal RMSKZ is set including the high logic level period of the command pulse signal COMP.
  • generation of the command pulse enable signal COMPE is prohibited, and hence the refresh request signal RREQZ is not generated ( Fig. 8 (b) ).
  • the write operation responding to the write command WR is executed at the same timing as the read operation responding to the read command RD shown in Fig. 7 . Specifically, the write operation is executed just after the write command WR ( Fig. 8 (c) ).
  • a specification of the access cycle time required for the write operation WR is set to TC2, which is shorter than the access cycle time TCl. Specifically, the specification of the access cycle time TC2 when the refresh mask signal RMSKZ is at the valid level is set shorter than the specification of the access cycle time TCl in the normal operation mode by the time in which the refresh operation is not executed.
  • the read command RD is supplied, and the command pulse signal COMP is outputted in synchronization with the read command RD ( Fig. 8 (d) ).
  • the refresh mask signal RMSKZ is set to a low logic level (invalid level) by the LSI tester TEST. Accordingly, the command pulse enable signal COMPE is outputted in synchronization with the command pulse signal COMP ( Fig. 8 (e) ), and the refresh request signal RREQZ is outputted ( Fig. 8 (f) ).
  • the refresh request RREQZ and the read command RD occur at substantially the same time, and thus the arbiter ARB outputs the refresh control signal REFZ first, and outputs the active signal ACTZ thereafter ( Fig.
  • the refresh operation REF and the read operation RD are executed sequentially ( Fig. 8 (i,j)).
  • the specification of the access cycle time TCl when the refresh mask signal RMSKZ is at the invalid level is set equal to the access cycle time TCl in the normal operation mode.
  • the read command RD and the write command WR are supplied sequentially to the memory MEM.
  • the read address signal AD2 and the write address signal AD1 are the same as those in Fig. 7 .
  • the refresh control signal REFZ is not generated in response to the read command RD, but generated in response to the write command WR.
  • the LSI tester TEST which tests the memory MEM sets the refresh mask signal RMSKZ to a high logic level in synchronization with the supply of the read command RD ( Fig. 9 (a) ), so as to prevent generation of the refresh control signal REFZ in response to the read command RD.
  • execution of the refresh operation REF is masked.
  • the read operation responding to the read command RD is executed at the same timing as the read operation responding to the read command RD shown in Fig. 7 and Fig. 8 .
  • the access cycle time required for the read operation RD is TC2, which is shorter than the access cycle time TCl.
  • the write command WR is supplied, and the command pulse signal COMP is outputted in synchronization with the write command WR ( Fig. 9 (b) ).
  • the refresh mask signal RMSKZ is set to a low logic level by the LSI tester TEST. Accordingly, the command pulse enable signal COMPE is outputted in synchronization with the command pulse signal COMP ( Fig. 9 (c) ), and the refresh request signal RREQZ is outputted ( Fig. 9 (d) ).
  • the refresh request RREQZ and the write command WR occur at substantially the same time, and thus the arbiter ARB executes the refresh operation REF first, and executes the read operation RD thereafter ( Fig. 9 (e, f)), similarly to Fig. 7 .
  • the refresh mask signal RMSKZ is set to a high logic level in synchronization with the access command WR or RD during the test mode.
  • execution of the refresh operation REF in synchronization with the access command WR, RD can be masked. Therefore, the specification of the access cycle time required for the access operation (write operation WR in Fig. 8 , read operation RD in Fig. 9 ) is TC2, which is shorter than the access cycle time TCl.
  • the access cycle time TC2 is equal to a time obtained by subtracting a time taken for one refresh operation (activation period of the RASZ signal) from the access cycle time TC1. Specifically, the access cycle time TC2 is slightly longer than a half of the access cycle time TC1. As a result, a test time for testing the memory MEM can be shortened.
  • Fig. 10 shows one example of operations in a test mode prior to the present invention. Detailed explanations of the same operations as those in Fig. 7 - Fig. 9 are omitted.
  • the command pulse signal COMP is generated for every write command WR and read command RD. Accordingly, the refresh operation is always executed in response to the write command WR and the read command RD. Therefore, the access cycle time required for one write operation and one read operation is always TCl, similarly to the normal operation mode.
  • testing of the memory MEM is performed by writing test data in a large number of memory cells MC and comparing thereafter data read from the large number of memory cells MC with expected values (written test data).
  • one access operation (write operation or read operation) is executed by approximately 50 - 100 ns for example, and the refresh operation is executed once in a few ⁇ s to a few tens of ⁇ s in response to the refresh request signal RREQ0Z.
  • the refresh operation is executed once in 10,000 access operations for example.
  • the refresh operation is executed for every access operation during the test mode, and hence was wasteful.
  • the refresh operation only needs to be executed once in 10,000 access operations for example.
  • a test time of 400 ⁇ s (10,000 times of 40 ns) can be saved by 10,000 access operations.
  • whether or not to execute the refresh operation in synchronization with the access command RD, WR during the test mode can be set according to the logic level of the refresh mask signal RMSKZ.
  • the refresh request is masked when the refresh mask signal RMSKZ is at the valid level. Accordingly, the specification of the access cycle time TC2 in which the refresh operation is prohibited can be set shorter than the access cycle time T1 in the normal operation mode. Since only the refresh operation required for the test can be executed, the test time can be shortened. Consequently, the test efficiency can be improved and the manufacturing cost for a semiconductor memory can be reduced.
  • Fig. 11 shows another embodiment of the present invention.
  • the refresh mask terminal RMSKZ and the register R1 of the previous embodiment are deleted, and the upper-byte control signal/UB (data mask signal) received at the upper-byte control terminal /UB (data mask terminal) are supplied to the refresh control circuit 12 as the refresh mask signal RMSKZ.
  • the semiconductor memory MEM is an FCRAM for example.
  • Fig. 12 shows details of a refresh control circuit 12 shown in Fig. 11 .
  • the circuit configuration of the refresh control circuit 12 is the same as the refresh control circuit of the previous embodiment.
  • the mask circuit MSK receives not the inverted logic of the refresh mask signal RMSKZ but the inverted logic of the upper-byte control signal /UB. Specifically, the mask circuit MSK sets the command pulse enable signal COMPE to a low logic level when the upper-byte control signal /UB is at a high logic level (valid level), and outputs the command pulse signal COMP as the command pulse enable signal COMPE (test refresh request signal) when the upper-byte control signal /UB is at a low logic level (invalid level).
  • the command pulse enable signal COMPE is not activated when the read command RDZ or the write command WRZ is generated.
  • the upper-byte control signal /UB functions as a refresh mask terminal which receives the refresh mask signal RMSKZ during the test mode.
  • the high level period (valid level period) of the test refresh request signal COMP generated in synchronization with the access command RD or WR can be set shorter than the pulse generating circuit PLS.
  • the high level period of the test refresh request signal COMP can be made sufficiently shorter than a supply period of the access command RD or WR (low logic level period of the /OE signal or the /WE signal).
  • the valid level period (mask period) of the refresh mask signal RMSKZ (/UB) can be made shorter, it is possible to securely prevent overlapping of the input/output period of a data signal DQ and the valid level period of the refresh mask signal RMSKZ, as shown in Fig. 13 and Fig. 14 which will be explained later.
  • the refresh control circuit 12 may receive the data control signal UBZ outputted from the access control circuit 10, instead of the refresh mask signal RMSKZ.
  • the data control signal UBZ is supplied directly to the mask circuit MSK without intervention of an inverter.
  • a refresh request during the test mode is masked by the refresh mask signal RMSKZ received at the upper-byte control terminal /UB.
  • the waveform of the upper-byte control signal/UB is the same as the waveform of the refresh mask signal RMSKZ shown in Fig. 8 except that a valid level period ( Fig. 13 (a) ) is different. Waveforms of other signals are the same as the waveforms in Fig. 8 .
  • a data signal DQ is inputted or outputted after receiving the access command WR, RD according to the operation of the memory core.
  • the data signal DQ is not transmitted to the data terminal, and hence the upper-byte control signal /UB can be reused as a signal other than the mask signal of the data signal DQ (namely, the refresh mask signal RMSKZ) during a supply period of the access command WR, RD.
  • the upper-byte control terminal/UB functions as a terminal to receive the refresh mask signal RMSKZ when receiving the access command WR, RD, and functions as a terminal to receive the data mask sianal/UB which masks the data signal DQ inputted/outputted to the data terminal DQ after receiving the access command WR, RD.
  • a finish timing of receiving the access command WR, RD is, for example, a falling edge of the upper-byte control signal/UB ( Fig. 13 (b) ). Note that when the write data signal DQ7-1 5 is masked, the upper-byte control signal /UB is set to a high logic level during the supply period of the write data signal DQ7-15. The same applies to the lower-byte control signal/LB.
  • the valid level period (high logic level period) of the upper-byte control signal/UB for masking the refresh operation does not overlap with the supply period of the data signal DOUT, DIN to the data terminal DQ.
  • the valid level period of the upper-byte control signal /UB for masking the refresh operation is set including the high logic level period of the command pulse signal COMP, and hence it is necessary that the command pulse signal COMP falls before start of the supply of the write data signal DIN.
  • the command pulse signal COMP is set to a short valid level period by the pulse generating circuit PLS. Accordingly, it is possible to securely prevent overlapping of the input/output period of the data signal DQ with the valid level period of the refresh mask signal RMSKZ (/UB). The same applies to an operation example of Fig. 14 .
  • Fig. 15 shows a test environment of this embodiment.
  • a difference from the previous embodiment is that the refresh mask signal RMSKZ is not supplied from the LSI tester TEST to the memory MEM.
  • the other configuration is the same as in Fig. 6 .
  • the refresh operation can be masked using the upper-byte control signal /UB during the test mode. Accordingly, the number of terminals of the LSI tester TEST used for one memory MEM becomes smaller than in the previous embodiment.
  • the upper-byte control terminal /UB is enabled to function also as a refresh mask terminal to receive the refresh mask signal RMSKZ.
  • the dedicated terminal to receive the refresh mask signal RMSKZ can be dispensed with.
  • the present invention is not limited to such an embodiment.
  • the present invention may be applied to a pseudo SRAM of synchronous clock type.
  • an access command is supplied in synchronization with a transition edge of the clock signal.
  • the refresh mask signal RMSKZ is supplied in synchronization with a transition edge of the clock signal at which the access command is supplied.
  • a dedicated test command which is not used for a normal access operation may be prepared so as to make the memory MEM enter the test mode from the normal operation mode according to the test command.
  • the test command there may be prepared a test entry command to enter the test mode and a test exit command to return to the normal operation mode from the test mode.
  • preparation of the test exit command may be omitted.
  • a dedicated test terminal may be provided so as to make the memory MEM enter the test mode when a valid level is supplied to the test terminal.
  • the test terminal is formed as a test pad to be contacted by a probe of an LSI tester, similarly to the refresh mask terminal RMSKZ shown in Fig. 1 .
  • the present invention is not limited to such an embodiment.
  • the present invention may be applied to a semiconductor memory having an input-dedicated data terminal and an output-dedicated data terminal.
  • the upper-byte control terminal /UB is enabled to function also as a terminal to receive the refresh mask signal RMSKZ during the test mode.
  • the present invention is not limited to such an embodiment.
  • the same effect can be obtained by enabling the lower-byte control signal /LB to function as a terminal to receive the refresh mask signal RMSKZ.
  • a plurality of test modes may be provided so as to enable the upper-byte control terminal /UB to function as a dedicated terminal to receive the refresh mask signal RMSKZ during the test mode using the refresh mask signal RMSKZ.
  • Fig. 16 shows an example of the semiconductor memory MEM in which this invention is applied.
  • the data control circuit 20 receives the test mode signal TMZ at a high logic level, prohibits acceptance of the upper-byte control signal /UB, and prohibits that the data signal DQ is masked by the upper-byte control signal /UB. Note that reception of the lower-byte control signal /LB may be prohibited during the test mode.
  • the present invention can be applied to a semiconductor memory having memory cells of DRAM and an interface of SRAM.
  • a proposition of the embodiments is to improve test efficiency by executing only a refresh operation needed for a test.
  • Another proposition of the embodiments is to improve test efficiency by executing only a refresh operation needed for a test without providing a dedicated test terminal.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
EP07150438.5A 2006-12-27 2007-12-27 DRAM with disabled refresh in test mode Expired - Fee Related EP1939887B1 (en)

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US7649796B2 (en) 2010-01-19
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KR100909408B1 (ko) 2009-07-24
US20080159041A1 (en) 2008-07-03
JP2008165865A (ja) 2008-07-17

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