EP1907933B1 - Flashspeicher-fehlerkorrektur - Google Patents

Flashspeicher-fehlerkorrektur Download PDF

Info

Publication number
EP1907933B1
EP1907933B1 EP06755725A EP06755725A EP1907933B1 EP 1907933 B1 EP1907933 B1 EP 1907933B1 EP 06755725 A EP06755725 A EP 06755725A EP 06755725 A EP06755725 A EP 06755725A EP 1907933 B1 EP1907933 B1 EP 1907933B1
Authority
EP
European Patent Office
Prior art keywords
data
memory
error correction
read
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP06755725A
Other languages
English (en)
French (fr)
Other versions
EP1907933A2 (de
Inventor
Morgan Colmer
Robert John Duncan Macaulay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cufer Asset Ltd LLC
Original Assignee
GS IP LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GS IP LLC filed Critical GS IP LLC
Publication of EP1907933A2 publication Critical patent/EP1907933A2/de
Application granted granted Critical
Publication of EP1907933B1 publication Critical patent/EP1907933B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

Definitions

  • the invention relates to a data processing device for applying an error correction algorithm to data to be written to and/or read from a re-writable memory.
  • Filing systems such as FAT16 and FAT32 save two copies of a table that is used to tell the host processor where everything is stored on the device. Every time any part of the bulk memory is changed, the filing system causes the two copies of this essential data to be re-written.
  • NAND flash memory a single location or byte cannot be individually erased and so an entire block (covering several sectors) must be formatted and re-written each time part of the bulk memory is changed. This causes premature failures to many devices such as thumb drives.
  • DRAM another commodity memory product is frequently salvaged from old SIMMS and often at a fraction of the ambient market prices. With a revolution in NAND flash demand from the audio electronics industry poised to happen, it seems likely that this type of memory product will also be targeted by component recycling companies.
  • Recycled flash memory will be characterised by a number of factors: (i) older technology and (ii) higher probability of defective sectors. Any flash controller entering the market should be adapted to deal with these disadvantages so that it can be used with recycled flash memory.
  • US patent 5,603,001 describes a NAND based storage disk system, featuring automatic error correction for data stored on the disk.
  • an error correction code (ECC) is generated and a check for error detection is performed by the hardware logic of the flash memory interface circuit.
  • the error correction for read data is done by the firmware which is executed by the microprocessor.
  • US patent 5,063,565 A describes a system in which a first memory is used to store information data and corresponding parity data. If an error is detected in the information data, correction data stored in a second memory is used to correct the information data.
  • US patent 6,256,762 B1 describes a system which divides up the data to be stored into a plurality of memory banks and applies ECC to each bank.
  • a data storage device comprising; an integrated circuit comprising a rewritable memory and an error correction means for providing the rewritable memory with simple error correction; an extended error correction means for applying an extended error correction algorithm to data written to and data read from the re-writable memory, the extended error correction means comprising: a coding unit implemented in hardware, the coding unit being capable of performing a coding operation in which it receives a first set of data to be written to the memory, processes that data in accordance with the extended error correction algorithm to form a second set of data and outputs the second set of data for writing to the memory, and an error detection operation in which it receives data read from the memory and processes that data in accordance with the extended error correction algorithm to determine whether the read data contains an error; and an error correction unit implemented in software, the error correction unit being arranged to receive read data that contains an error, process that data in accordance with the extended error correction algorithm to correct
  • the coding unit is arranged to, if it determines that the data read from memory does not contain an error, output the data read from memory.
  • the coding unit may be arranged to perform the same processing of the data read from memory during the error detection operation as it performs on the first set of data during the coding operation.
  • the coding unit may be arranged to, during an error detection operation, treat the data read from memory as a first set of data in accordance with a coding operation and process that data in accordance with the error correction algorithm to form a second set of data.
  • the coding unit may comprise a codeword generator arranged to receive the data read from memory, multiply the information data included in the read data by a generator polynomial and compare the result of said multiplication with the parity data included in the read data.
  • the syndrome generator may be arranged to substitute a plurality of roots of the generator polynomial into the concatenated data and to sum the values resulting from each substitution, the results of each summation being indicative of the location of an error in the information data.
  • the coding unit is arranged to, when it has determined that the data read from memory contains an error, output that information data to the error correction unit.
  • the error correction unit may be arranged to interleave data to be written to the memory and deinterleave data that is read from the memory.
  • the coding unit is preferably capable of detecting more than one bit error in every 256 bytes read from memory.
  • the error correction unit is preferably capable of correcting more than one bit error in every 512 bytes read from memory.
  • the error correction algorithm may be a Reed-Solomon code.
  • the error correction algorithm is preferably a Cross Interleaved Reed-Solomon code.
  • the error correction unit is a digital processor.
  • the memory may be a recycled integrated memory.
  • the memory may have a percentage of unusable memory blocks greater than 2%.
  • the memory is preferably flash memory.
  • the memory is preferably NAND flash memory.
  • the memory may be such that bits of the memory are not accessible in isolation from other bits of the memory.
  • a method for processing data to be written to and data to be read from a rewritable memory integrated circuit having an integrated error correction means capable of providing the memory with simple error correction comprising: performing a coding operation in hardware, the coding operation comprising receiving a first set of data to be written to the memory, processing that data in accordance with an extended error correction algorithm to form a second set of data and outputting the second set of data for writing to the memory; performing an error detection operation in hardware (s204), the error detection operation comprising receiving data read from the memory and processing that data in accordance with the extended error correction algorithm to determine whether the read data contains an error; and performing an error correction operation in software (s206), the error correction operation comprising receiving read data that contains an error, processing that data in accordance with the extended error correction algorithm to correct said error and outputting the corrected data, characterised in that the extended error correction means is capable of detecting and correcting more errors than the simple error correction already provided with the re-writable memory
  • Embodiments of the invention provide a data processing device for use with a rewritable memory.
  • the device is particularly suitable for use with a recycled memory that contains a large number of damaged sectors or with a manufactured memory that has too high an error rate to be sold as a normal device.
  • the data processing device is arranged to process data to be written to and/or read from the memory in accordance with an error correction code.
  • the data processing device advantageously splits the error coding and correcting functions between hardware and software, so that a powerful error correction code (which is necessary to deal with the data errors caused by damaged memory sectors) can be implemented without adding a substantial overhead to read and write times and without adding substantially to the processing power required of the processor. This is in contrast with many existing memory controllers, in which all data to be written to and/or read from the memory has to be processed by software.
  • a data processing device is illustrated in figure 1 .
  • the data processing device is shown generally at 101 and is coupled to a memory 102.
  • the data processing device comprises a coding unit 103, which is implemented in hardware, and an error correction unit 104, which is implemented in software.
  • the error correction unit is suitably a digital processor.
  • the coding unit is arranged to receive data to be written to the memory.
  • the coding unit codes the data that is to be written to the memory and outputs the resulting coded data, so that it too can be written to the memory.
  • the coding unit preferably implements a systematic code, in which the coding process generates additional coded data (i.e. parity data) from the data to be written to memory, rather than changing the data itself.
  • the coding unit may output only the coded data to be written to the memory, or may output both the coded data and actual data for writing to memory.
  • the coded data and actual data may subsequently be stored in different memory locations, i.e. the actual data need not be stored adjacent to its associated parity data.
  • the coding unit is also arranged to receive data read from the memory.
  • the data should include information data read from the memory location at which the original data was written and parity data associated with that information data, i.e. data read from the location at which the coded data formed from the original data was written in the memory.
  • the coding unit processes the data read from memory in order to detect whether it contains any errors. This processing may involve both the parity data and the information data or the parity data only. If the coding unit detects an error or errors in the data read from the memory, it passes the erroneous data to the error correction unit. If the coding unit does not detect any errors, then it may output the information data. Alternatively, the coding unit may signal to another component, e.g. a controller, coupled to the memory, that the information data may safely be output by that component.
  • a controller coupled to the memory
  • the coding unit may also provide hardware support for the error correction unit during the error correction operation.
  • Some of the data processing operations required by error correction algorithms such as Reed-Solomon codes are particularly suitable for implementing in hardware.
  • This additional processing could include e.g. the calculation and processing of syndromes, which is described in more detail below. Such additional processing could be performed by the coding unit as soon as it determines that data read from memory contains an error and any additional data (such as syndromes) generated from that processing may be passed to the error correction unit together with the erroneous data.
  • the coding unit may perform such additional processing under the control of the error correction unit, i.e. the coding unit may immediately pass any erroneous data to the error correction unit and only perform additional processing if it is forwarded appropriate data for processing by the error correction unit.
  • the coding unit may incorporate various specialised hardware blocks for processing data to be read to and/or read from memory.
  • the coding unit may use the same hardware block for performing the coding and error detection operations described above.
  • the coding unit may be provided with duplicate hardware blocks: one for coding data being written to memory and one for detecting errors in data read from memory.
  • the coding unit may be provided with further specialist hardware for performing any additional processing.
  • the coding unit may be provided with different specialist hardware blocks to provide hardware support for the different error correction algorithms that may be implemented by the software of the error correction unit.
  • the error correction unit is arranged to receive data from the coding unit and correct the errors contained in the information data.
  • the data received by the error correction unit may include the information data, the parity data and optionally some further data calculated by the coding unit, e.g. syndrome data.
  • Multiplication and division are slightly more complicated. As each member can be regarded as a power of ⁇ it is possible to take the log of any member. The log is simply the position in the above sequence i.e. the number of shifts or the power of ⁇ . So the log of 1 is 0 and the log of 3A is 9. In order to multiply or divide two bytes we first take the log of each number then either add or subtract the logs then raise ⁇ to this power to get the result.
  • the error correcting power of the Reed-Solomon codes described above can be increased by employing interleaving. This results in the Cross Interleaved Reed-Solomon Code (CIRC) is a very powerful error correction algorithm.
  • CIRC Cross Interleaved Reed-Solomon Code
  • the basic error correction capability of a Reed-Solomon code can be extended by cross interleaving. This essentially means arranging the data into a two dimensional array and computing independent parity bytes for rows and columns. This means that a burst error, which one would expect from defective sectors of the memory, affects many contiguous bytes in one dimension only affects one or two bytes per frame in the other dimension. Such an array is shown in figure 6 .
  • the frame in the "vertical” or column direction is referred-to as C1 and contains 32 bytes, four of which are parity.
  • the frame in the "horizontal” or row direction is referred-to as C2 and contains 28 bytes, four of which are parity. After processing C1 and C2, 24 data bytes remain. These are equivalent to six stereo samples.
  • C1 parity is computed such that the following equations hold true.
  • the data can be checked very quickly using the syndrome generator logic.
  • This logic contains four accumulators. When a byte is written to the syndrome logic the previous value in each of the accumulators is multiplied by 1, ⁇ 1 , ⁇ 2 and ⁇ 3 respectively then added to the new byte. This efficiently performs the above calculation irrespective of the size of the frame.
  • the syndrome If the data is correct then the values in the accumulators, known as the syndrome, will all be zero. If the syndrome is non zero then the syndrome can be used to correct the error in one of three ways, single error correction, double error correction and four erasure correction.
  • the coding unit could be arranged to calculate a syndrome of the received codeword. If the syndrome is non-zero, then an error is detected.
  • L 0 , L 1 , L 2 and L 3 are given by the flags from C1.
  • the errors are then equal to the modified syndrome bytes.
  • the code uses certain shortcuts for speed. When a coefficient would reach its final value there is no need to compute or store that value as it is no longer needed.
  • this in conjunction with the de-interleaving buffer would allow up to 4096 contiguous bits in error to be corrected without a single bit of the erroneous data being found by the host CPU. This is 4096 times better than the current error correction and without the enormous overhead that might be expected by casual inspection.
  • the redundancy is 16 bytes in every 512, thus 3.1% of the data stored to the flash memory is the error correction overhead, in a system based upon CIRC, this redundancy level rises to 12.5% (when only using C2), however this is for a 4096:1 increase in the error correction capacity.
  • the CIRC error correction can also re-use the extra space available from the now-unused Hamming code system which takes the data redundancy down to only 9.4%.
  • the data processing device is particularly advantageous when used together with memories that contain a large number of damaged sectors, such as recycled memories or manufactured memories that have too high an error rate for normal sale, and which would otherwise be manufacturing rejects.
  • the data processing device is not limited, however, to implementations in which it is coupled to such damaged memories. It may be beneficially used in any implementation in which it is desired to implement a powerful error correction code without incurring the read and write overhead that implementing such an error correction code in software alone would typically entail.
  • the data processing device may be advantageously incorporated into a wide range of consumer electrical products, such as CD players, digital audio players, digital cameras, mobile phones etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Read Only Memory (AREA)

Claims (26)

  1. Datenspeicherungsanordnung, die aufweist:
    eine integrierte Schaltung, die einen überschreibbaren Speicher (102) und ein Fehlerkorrekturmittel aufweist, um den überschreibbaren Speicher (102) mit einer einfachen Fehlerkorrektur zu versehen;
    ein erweitertes Fehlerkorrekturmittel zur Anwendung eines erweiterten Fehlerkorrekturalgorithmus auf Daten, die in den überschreibbaren Speicher (102) geschrieben und aus diesem ausgelesen werden, wobei das erweiterte Fehlerkorrekturmittel aufweist:
    eine in Hardware ausgeführte Kodiereinheit (103), wobei die Kodiereinheit geeignet ist einen Kodiervorgang auszuführen in dem sie einen ersten Satz von Daten entgegennimmt die in den überschreibbaren Speicher (102) geschrieben werden sollen, die Daten gemäß dem erweiterten Fehlerkorrekturalgorithmus zu verarbeiten, um einen zweiten Satz von Daten zu bilden und den zweiten Satz von Daten zum Schreiben in den überschreibbaren Speicher (102) ausgibt, und einen Fehlererkennungsvorgang auszuführen, in dem sie aus dem überschreibbaren Speicher (102) ausgelesene Daten entgegennimmt und die Daten gemäß dem erweiterten Fehlerkorrekturalgorithmus verarbeitet, um festzustellen, ob die ausgelesenen Daten einen Fehler enthalten; und
    eine in Software ausgeführte Fehlerkorrektureinheit (104), wobei die Fehlerkorrektureinheit eingerichtet ist ausgelesene Daten, die einen Fehler enthalten, entgegenzunehmen, diese Daten gemäß dem erweiterten Fehlerkorrekturalgorithmus zu verarbeiten, um diesen Fehler zu korrigieren und dadurch korrigierte Daten zu bilden, und die korrigierten Daten auszugeben, wobei
    das erweiterte Fehlerkorrekturmittel geeignet ist, mehr Fehler zu erkennen und zu korrigieren, als die einfache Fehlerkorrektur, die bereits mit dem überschreibbaren Speicher (102) zur Verfügung gestellt wird.
  2. Datenverarbeitungsanordnung gemäß Anspruch 1, wobei die Kodiereinheit eingerichtet ist die aus dem Speicher ausgelesenen Daten auszugeben, wenn sie feststellt, dass die aus dem Speicher ausgelesenen Daten keinen Fehler enthalten.
  3. Datenverarbeitungsanordnung gemäß Anspruch 1 oder 2, wobei die Kodiereinheit eingerichtet ist während des Fehlererkennungsvorgangs die gleiche Verarbeitung der aus dem Speicher ausgelesenen Daten auszuführen die sie während des Kodiervorgangs mit dem ersten Satz von Daten ausführt.
  4. Datenverarbeitungsanordnung gemäß Anspruch 3, wobei die Kodiereinheit eingerichtet ist während eines Fehlererkennungsvorgangs die aus dem Speicher ausgelesenen Daten gemäß einem Kodiervorgang als einen ersten Satz von Daten zu behandeln und diese Daten gemäß dem Fehlerkorrekturalgorithmus zu verarbeiten um einen zweiten Satz von Daten zu bilden.
  5. Datenverarbeitungseinheit gemäß einem der vorherigen Ansprüche, wobei die Kodiereinheit eingerichtet ist Informationsdaten entgegenzunehmen, die aus einer ersten Position in dem Speicher ausgelesen wurden, in die zuvor ein erster Satz von Daten geschrieben wurde, und Paritätsdaten entgegenzunehmen die zugehörig sind zu den Informationsdaten, die aus einer zweiten Position in dem Speicher ausgelesen wurden, in die zuvor ein zweiter Satz von Daten geschrieben wurde, wobei der zweite Satz von Daten zuvor während eines Kodiervorgangs aus dem ersten Satz von Daten gebildet wurde.
  6. Datenverarbeitungsanordnung gemäß dem direkt von Anspruch 4 abhängigen Anspruch 5, wobei die Kodiereinheit eingerichtet ist durch Verarbeiten der Informationsdaten gemäß dem Fehlererkennungsalgorithmus zur Bildung eines zweiten Satzes von Daten zu erkennen, dass aus dem Speicher ausgelesene Daten einen Fehler enthalten, diesen zweiten Satz von Daten mit den Paritätsdaten zu vergleichen und zu erkennen, dass die Informationsdaten einen Fehler enthalten, wenn der zweite Satz von Daten nicht identisch ist mit den Paritätsdaten.
  7. Datenverarbeitungsanordnung gemäß einem der vorherigen Ansprüche, wobei die Kodiereinheit einen Kennwortgenerator aufweist der eingerichtet ist den ersten Satz von Daten entgegenzunehmen, diese Daten durch einen Generator polynomial zu multiplizieren und das Ergebnis dieser Multiplikation als den zweiten Satz von Daten auszugeben.
  8. Datenverarbeitungsanordnung gemäß einem der Ansprüche 5 bis 7, wobei die Kodiereinheit einen Kennwortgenerator aufweist der eingerichtet ist die aus dem Speicher ausgelesenen Daten entgegenzunehmen, die in den ausgelesenen Daten enthaltenen Informationsdaten durch einen Generator polynomial zu multiplizieren und das Ergebnis dieser Multiplikation mit den in den ausgelesenen Daten enthaltenen Paritätsdaten zu vergleichen.
  9. Datenverarbeitungsanordnung gemäß einem der Ansprüche 5 bis 8, wobei die Kodiereinheit einen Syndromgenerator aufweist der eingerichtet ist die aus dem Speicher ausgelesenen Daten entgegenzunehmen, die in den ausgelesenen Daten enthaltenen Informationsdaten und Paritätsdaten zu verknüpfen, eine Wurzel des Generatorpolynoms in den verknüpften Daten zu ersetzen und die sich ergebenden Werte zu summieren.
  10. Datenverarbeitungsanordnung gemäß Anspruch 9, wobei die Kodiereinheit eingerichtet ist zu erkennen dass die Informationsdaten einen Fehler enthalten, wenn die Summierung der sich ergebenden Werte nicht Null ist.
  11. Datenverarbeitungsanordnung gemäß Anspruch 10, wobei der Syndromgenerator eingerichtet ist eine Vielzahl von Wurzeln des Generatorpolynoms in den verknüpften Daten zu ersetzen und die sich aus jeder Ersetzung ergebenden Werte zu summieren, wobei die Ergebnisse jeder Summierung die Position eines Fehlers in den Informationsdaten anzeigen.
  12. Datenverarbeitungsanordnung gemäß einem der vorherigen Ansprüche, wobei die Kodiereinheit eingerichtet ist die Informationsdaten an die Fehlerkorrektureinheit auszugeben, wenn sie festgestellt hat, dass die aus dem Speicher ausgelesenen Daten einen Fehler enthalten.
  13. Datenprozessor gemäß einem der vorherigen Ansprüche, wobei die Fehlerkorrektureinheit eingerichtet ist Daten, die in den Speicher geschrieben werden sollen, zu verschachteln und Daten, die aus dem Speicher ausgelesen werden, zu entschachteln.
  14. Datenprozessor gemäß einem der vorherigen Ansprüche, wobei die Kodiereinheit geeignet ist, mehr als einen Bitfehler in jeden 256 aus dem Speicher ausgelesenen Byte zu erkennen.
  15. Datenprozessor gemäß einem der vorherigen Ansprüche, wobei die Fehlerkorrektureinheit geeignet ist, mehr als einen Bitfehler in jeden 256 aus dem Speicher ausgelesenen Byte zu korrigieren.
  16. Datenverarbeitungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Fehlerkorrekturalgorithmus ein Reed-Solomon Code ist.
  17. Datenverarbeitungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Fehlerkorrekturalgorithmus ein Cross Interleaved Reed-Solomon Code ist.
  18. Datenprozessor gemäß einem der vorherigen Ansprüche, wobei die Fehlerkorrektureinheit ein digitaler Prozessor ist.
  19. Datenverarbeitungsanordnung gemäß einem der vorherigen Ansprüche, wobei der überschreibbare Speicher auf einer einzelnen integrierten Schaltung montiert ist.
  20. Datenverarbeitungsanordnung gemäß Anspruch 19, wobei der überschreibbare Speicher und das erweiterte Fehlerkorrekturmittel nicht auf der gleichen integrierten Schaltung montiert sind.
  21. Datenspeicherungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Speicher ein aufgearbeiteter integrierter Speicher ist.
  22. Datenspeicherungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Prozentsatz an nicht verwendbaren Speicherblöcken größer als 2 % ist.
  23. Datenspeicherungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Speicher Flashspeicher ist.
  24. Datenspeicherungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Speicher NAND Flashspeicher ist.
  25. Datenspeicherungsanordnung gemäß einem der vorherigen Ansprüche, wobei der Speicher so vorliegt, dass auf Bits des Speichers nicht getrennt von anderen Bits des Speichers zugegriffen werden kann.
  26. Verfahren zur Verarbeitung von Daten, die geschrieben werden sollen in und ausgelesen werden sollen aus einer integrierten Schaltung eines überschreibbaren Speichers (102) der ein integriertes Fehlerkorrekturmittel aufweist das geeignet ist den überschreibbaren Speicher (102) mit einer einfachen Fehlerkorrektur zu versehen, wobei das Verfahren aufweist:
    Ausführen eines Kodiervorgangs in Hardware, wobei der Kodiervorgang das Entgegennehmen eines ersten Satzes von Daten aufweist, die in den überschreibbaren Speicher (102) geschrieben werden sollen, das Verarbeiten der Daten gemäß eines erweiterten Fehlerkorrekturalgorithmus um einen zweiten Satz von Daten zu bilden und das Ausgeben des zweiten Satzes von Daten zum Schreiben in den überschreibbaren Speicher (102),
    Ausführen eines Fehlererkennungsvorgangs in Hardware (s204), wobei der Fehlererkennungsvorgang das Entgegennehmen von aus dem überschreibbaren Speicher (102) ausgelesenen Daten aufweist und das Verarbeiten dieser Daten gemäß dem erweiterten Fehlerkorrekturalgorithmus um zu erkennen, ob die ausgelesenen Daten einen Fehler enthalten; und
    Ausführen eines Fehlerkorrekturvorgangs in Software (s206), wobei der Fehlerkorrekturvorgang das Entgegennehmen ausgelesener Daten aufweist, die einen Fehler enthalten, das Verarbeiten dieser Daten gemäß des erweiterten Fehlerkorrekturalgorithmus um den Fehler zu korrigieren und die korrigierten Daten auszugeben, wobei
    das erweiterte Fehlerkorrekturmittel geeignet ist mehr Fehler zu erkennen und zu korrigieren als die einfache Fehlererkennung, die bereits mit dem überschreibbaren Speicher (102) zur Verfügung gestellt wird.
EP06755725A 2005-07-15 2006-07-06 Flashspeicher-fehlerkorrektur Active EP1907933B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0514610A GB2428496A (en) 2005-07-15 2005-07-15 Error correction for flash memory
PCT/GB2006/002507 WO2007010189A2 (en) 2005-07-15 2006-07-06 Flash memory error correction

Publications (2)

Publication Number Publication Date
EP1907933A2 EP1907933A2 (de) 2008-04-09
EP1907933B1 true EP1907933B1 (de) 2009-09-16

Family

ID=34897323

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06755725A Active EP1907933B1 (de) 2005-07-15 2006-07-06 Flashspeicher-fehlerkorrektur

Country Status (8)

Country Link
US (1) US8140939B2 (de)
EP (1) EP1907933B1 (de)
JP (1) JP4988731B2 (de)
KR (1) KR100989532B1 (de)
CN (1) CN101258471A (de)
DE (1) DE602006009273D1 (de)
GB (1) GB2428496A (de)
WO (1) WO2007010189A2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101504337B1 (ko) * 2008-06-26 2015-03-25 삼성전자주식회사 메모리 시스템 및 그 구동방법
US8291295B2 (en) 2005-09-26 2012-10-16 Sandisk Il Ltd. NAND flash memory controller exporting a NAND interface
US7979666B2 (en) * 2006-12-08 2011-07-12 William Marsh Rice University System and method for context-independent codes for off-chip interconnects
JP4564520B2 (ja) 2007-08-31 2010-10-20 株式会社東芝 半導体記憶装置およびその制御方法
US20090070655A1 (en) * 2007-09-11 2009-03-12 Silicon Motion, Inc. Method for Generating an ECC Code for a Memory Device
KR101403314B1 (ko) 2008-05-23 2014-06-05 삼성전자주식회사 메모리 장치 및 데이터 비트 저장 방법
US8458536B2 (en) * 2008-07-17 2013-06-04 Marvell World Trade Ltd. Data recovery in solid state memory devices
JP2010097600A (ja) * 2008-09-22 2010-04-30 Panasonic Corp 半導体記録装置
JP5422974B2 (ja) * 2008-11-18 2014-02-19 富士通株式会社 誤り判定回路及び共有メモリシステム
US8341501B2 (en) 2009-04-30 2012-12-25 International Business Machines Corporation Adaptive endurance coding of non-volatile memories
US20110041005A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Providing Read Status and Spare Block Management Information in a Flash Memory System
US20110040924A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code
KR101616100B1 (ko) * 2009-09-25 2016-04-28 삼성전자주식회사 메모리 시스템 및 그것의 동작 방법
US8862973B2 (en) * 2009-12-09 2014-10-14 Intel Corporation Method and system for error management in a memory device
US11869584B2 (en) 2010-04-19 2024-01-09 Silicon Motion, Inc. Memory access module for performing a plurality of sensing operations to generate digital values of a storage cell in order to perform decoding of the storage cell
TW201508759A (zh) 2010-04-19 2015-03-01 Silicon Motion Inc 用來進行記憶體存取管理之方法以及記憶裝置及其控制器
US8572457B2 (en) 2010-05-28 2013-10-29 Seagate Technology Llc Outer code protection for solid state memory devices
US8769374B2 (en) * 2010-10-13 2014-07-01 International Business Machines Corporation Multi-write endurance and error control coding of non-volatile memories
TWI459396B (zh) * 2010-12-30 2014-11-01 Phison Electronics Corp 資料寫入與讀取方法、記憶體控制器與記憶體儲存裝置
JP2012155541A (ja) 2011-01-26 2012-08-16 Toshiba Corp データ記憶装置、メモリ制御装置及びメモリ制御方法
GB201114831D0 (en) * 2011-08-26 2011-10-12 Univ Oxford Brookes Circuit with error correction
FR2992504A1 (fr) * 2012-06-26 2013-12-27 Commissariat Energie Atomique Dispositif et procede pour la correction d'erreurs dans un mot de code
KR102002925B1 (ko) * 2012-11-01 2019-07-23 삼성전자주식회사 메모리 모듈, 그것을 포함하는 메모리 시스템, 그것의 구동 방법
CN104035833A (zh) * 2013-03-07 2014-09-10 联发科技股份有限公司 校验机器可读代码完整性的方法及系统
EP2863566B1 (de) 2013-10-18 2020-09-02 Université de Nantes Verfahren zur Rekonstruktion eines Datenblocks und Vorrichtung zur Verwendung davon
TWI541819B (zh) * 2013-12-30 2016-07-11 慧榮科技股份有限公司 用來進行錯誤更正之方法、記憶裝置、與控制器
US9690823B2 (en) 2014-09-25 2017-06-27 Dropbox, Inc. Synchronizing copies of an extent in an append-only storage system
US9720607B2 (en) * 2014-09-25 2017-08-01 Dropbox, Inc. Append-only storage system supporting open and closed extents
US9772783B2 (en) 2014-09-25 2017-09-26 Dropbox, Inc. Constructing an index to facilitate accessing a closed extent in an append-only storage system
CN105653391B (zh) * 2014-11-13 2018-11-02 群联电子股份有限公司 数据存取方法、存储器控制电路单元及存储器储存装置
CN104932951B (zh) * 2015-07-12 2017-09-05 符方晓 一种nand闪存出现ecc无法纠错时的数据恢复方法
US10049007B2 (en) * 2015-10-28 2018-08-14 Via Technologies, Inc. Non-volatile memory device and read method thereof
CN105607974A (zh) * 2015-12-18 2016-05-25 西安电子科技大学 高可靠性多核处理系统
CN106601305A (zh) * 2016-11-18 2017-04-26 华中科技大学 一种使用检错码和纠错码相结合的固态盘纠错方法
CN107239358A (zh) * 2017-06-01 2017-10-10 捷开通讯(深圳)有限公司 安卓系统的启动方法、移动终端及具有存储功能的装置
US11184446B2 (en) 2018-12-05 2021-11-23 Micron Technology, Inc. Methods and apparatus for incentivizing participation in fog networks
US11256778B2 (en) 2019-02-14 2022-02-22 Micron Technology, Inc. Methods and apparatus for checking the results of characterized memory searches
US11327551B2 (en) * 2019-02-14 2022-05-10 Micron Technology, Inc. Methods and apparatus for characterizing memory devices
US12118056B2 (en) 2019-05-03 2024-10-15 Micron Technology, Inc. Methods and apparatus for performing matrix transformations within a memory array
US10867655B1 (en) 2019-07-08 2020-12-15 Micron Technology, Inc. Methods and apparatus for dynamically adjusting performance of partitioned memory
US10922012B1 (en) 2019-09-03 2021-02-16 Dropbox, Inc. Fair data scrubbing in a data storage system
US11449577B2 (en) 2019-11-20 2022-09-20 Micron Technology, Inc. Methods and apparatus for performing video processing matrix operations within a memory array
US11853385B2 (en) 2019-12-05 2023-12-26 Micron Technology, Inc. Methods and apparatus for performing diversity matrix operations within a memory array
CN111966524B (zh) * 2020-08-24 2021-07-13 深圳三地一芯电子有限责任公司 一种Flash数据写入方法及装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2553565B2 (ja) 1987-06-30 1996-11-13 松下電器産業株式会社 ガロア体演算装置
JP2606862B2 (ja) * 1987-12-28 1997-05-07 株式会社東芝 単−エラー検出・訂正方式
JPH07146825A (ja) 1993-11-22 1995-06-06 Okuma Mach Works Ltd メモリシステム
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
JP3268619B2 (ja) * 1994-11-10 2002-03-25 株式会社ケンウッド エンコード装置
US5778009A (en) * 1995-06-14 1998-07-07 Quantum Corporation Dedicated ALU architecture for 10-bit Reed-Solomon error correction module
JPH10207786A (ja) * 1997-01-22 1998-08-07 Kanebo Ltd メモリシステム
JPH10207726A (ja) * 1997-01-23 1998-08-07 Oki Electric Ind Co Ltd 半導体ディスク装置
US6360346B1 (en) * 1997-08-27 2002-03-19 Sony Corporation Storage unit, method of checking storage unit, reading and writing method
JPH11272568A (ja) * 1998-01-07 1999-10-08 Hitachi Ltd 記憶再生装置、誤り訂正方法及びこれらを用いた携帯情報端末ならびにディジタルカメラ
DE69932962T2 (de) * 1998-01-21 2007-02-01 Sony Corp. Kodierungsverfahren und Speicheranordnung
JP3975245B2 (ja) * 1999-12-16 2007-09-12 株式会社ルネサステクノロジ 記録再生装置および半導体メモリ
JP2004055098A (ja) * 2002-07-24 2004-02-19 Renesas Technology Corp 不揮発性メモリの記憶システム
US8412879B2 (en) * 2002-10-28 2013-04-02 Sandisk Technologies Inc. Hybrid implementation for error correction codes within a non-volatile memory system
JP4072424B2 (ja) * 2002-12-02 2008-04-09 エルピーダメモリ株式会社 メモリシステム及びその制御方法
US7231585B2 (en) * 2002-12-11 2007-06-12 Nvidia Corporation Error correction for flash memory
JP2004234545A (ja) * 2003-01-31 2004-08-19 Toshiba Corp 制御回路及びメモリコントローラ
US7426676B2 (en) * 2004-01-14 2008-09-16 Broadcom Corporation Data retrieval from a storage device using a combined error correction and detection approach
US7389465B2 (en) * 2004-01-30 2008-06-17 Micron Technology, Inc. Error detection and correction scheme for a memory device
JP4595342B2 (ja) * 2004-02-19 2010-12-08 日本電気株式会社 記憶装置のデータ書き込み、読み出し方法およびデータ記憶システム

Also Published As

Publication number Publication date
KR20080045676A (ko) 2008-05-23
JP2009501380A (ja) 2009-01-15
WO2007010189A2 (en) 2007-01-25
WO2007010189A3 (en) 2007-07-12
US8140939B2 (en) 2012-03-20
EP1907933A2 (de) 2008-04-09
GB0514610D0 (en) 2005-08-24
DE602006009273D1 (de) 2009-10-29
US20080235560A1 (en) 2008-09-25
CN101258471A (zh) 2008-09-03
GB2428496A (en) 2007-01-31
JP4988731B2 (ja) 2012-08-01
KR100989532B1 (ko) 2010-10-25

Similar Documents

Publication Publication Date Title
EP1907933B1 (de) Flashspeicher-fehlerkorrektur
KR102108386B1 (ko) 저장 장치 및 그것의 데이터 엔코딩 및 디코딩 방법들
JP5043562B2 (ja) エラー訂正回路、その方法及び前記回路を備える半導体メモリ装置
US8429489B2 (en) Data retrieval from a storage device using a combined error correction and detection approach
US10635528B2 (en) Memory controller and method of controlling memory controller
US7774688B1 (en) Hardware efficient decoding system for Bose, Ray-Chaudhuri, Hocquenghem (BCH) product codes
US8694872B2 (en) Extended bidirectional hamming code for double-error correction and triple-error detection
JP2007172818A5 (de)
US11016844B2 (en) Error correction code structure
JP4790790B2 (ja) 誤り検出訂正回路及び半導体メモリ
US20180198468A1 (en) Error correction code (ecc) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes
KR20180059151A (ko) 에러 정정 회로 및 이를 포함하는 메모리 컨트롤러
US10333555B2 (en) Apparatuses and methods for interleaved BCH codes
CN110908827A (zh) 用于NAND Flash闪存纠错的并行BCH解码方法
EP1486872B1 (de) Datenfehlerkorrektur mittels Redundanzblöcke
KR19990087035A (ko) 향상된다중버스트정정시스템
JP2007299393A (ja) 回転する記憶媒体の複数の層にデータを読み書きする方法、プログラム及びデータ記憶装置
US9448884B2 (en) Apparatuses and methods for encoding using error protection codes
US10404282B2 (en) Apparatuses and methods for integrated interleaved Reed-Solomon encoding and decoding
KR102705065B1 (ko) 낮은 레이턴시를 갖는 에러정정코드 디코더
Gilroy Appendix II: RAID 6 tutorial

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20071127

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 20080521

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602006009273

Country of ref document: DE

Date of ref document: 20091029

Kind code of ref document: P

REG Reference to a national code

Ref country code: FR

Ref legal event code: CA

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20100617

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 11

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 12

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240613

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240613

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240613

Year of fee payment: 19