Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

• the present invention relates to a process forming a structure comprising a layer taken from semiconductor material from a donor wafer, the donor wafer comprising before sampling a first layer of Sii-x Ge x and a second layer of Si -y Ge y on the first layer (x, y being respectively between 0 and 1, and x being different from y), the process comprising the following successive steps: (a) implantation of atomic species to form an embrittlement zone under the second layer;
• This type of layer sampling uses the Smart-Cut® technique, well known to those skilled in the art.
• An example of implementation of such a sampling method is described in particular in document US2004 / 0053477 in which the second layer has a crystallographic structure elastically constrained by that of the first layer.
• the step (d) of treatment of the sampled layers is often necessary to implement to remove defective areas and reduce the roughness present at the surface and which mainly result from the implementation of steps (a) and (c).
• the defect area has a thickness typically around 150 nm for atomic hydrogen implantation.
• a mechanical polishing or a chemical mechanical planarization may be used to make up the surface roughness, and / or sacrificial oxidation steps of the defective zones.
• step (b) Since the bonding according to step (b) is conventionally carried out by means of a layer of electrical insulating material, it will be possible to providing a semiconductor-on-insulator structure, such as an Si-I- x Ge x / Si-i-yG ⁇ y on insulator structure.
• a step subsequent to step (d) may be carried out so as to remove the remaining portion of the first layer, thereby retaining only the second layer on the receiver plate.
• This will produce a structure Si y Ge y on insulator.
• the removal operation of the remaining portion of the first layer can be effected effectively by selective chemical etching by employing suitable etching agents. Selective chemical etching makes it possible to obtain in the end the desired layer with a good surface quality, without the risk of damaging it too much (which could be the case if a single polishing was implemented).
• the chemical etching may in certain cases cause problems of at least partial delamination of the bonding interface. Indeed, it can in particular delaminate edge of the bonding layer, that is to say attack the latter at its outcropping by the edge of the structure produced.
• a sSOI structure (“strained silicon on insulator") comprising
• HF HAc (HAc being the abbreviation of acetic acid) on a sSi / SiGeOI structure
• the subsequent etching can no longer be selective.
• it is often desirable to avoid any diffusion from one layer to another. This is particularly the case when the second layer is in constrained Si (ie y 0) and it is ultimately desired to obtain a sSOI structure to fully benefit from the electrical properties of such a structure (ie increased mobility of charges).
• the treatment temperature is limited by the diffusion of Ge from one layer to another (this diffusion typically starting around 800 0 C), and the reinforcement carried out at low temperature can then be only partial. The delamination problem therefore remains.
• An object of the invention is to avoid delamination at the edge of the bonding layer during the implementation of a chemical finishing etching.
• Another object of the invention is to reduce the duration, the economic cost, and the number of processing means, after step (c), of the layers removed, and in particular no longer use mechanical polishing means.
• Another object of the invention is to provide a structure, such as a semiconductor-on-insulator structure, comprising a sampled layer including a less stable material than Si, such as constrained Si or SiGe.
• Another objective of the invention is to reduce the quantity of material sacrificed during the treatment of the sampled layer.
• Another objective of the invention is to propose a simple method for treating the sampled layer and easily integrating into the entire sampling process using the Smart-Cut® technique.
• the present invention seeks to overcome these problems by providing according to a first aspect, a process forming a structure comprising a layer removed from a donor wafer, the donor wafer comprising before sampling a first layer of Sii -x Ge x and a second layer on the first layer of Si y Ge y (x, y are respectively comprised between 0 and 1, and x being different from y), the method comprising the steps of:
• step (d) is carried out at a temperature of between about 1000 ° C. and about 1200 ° C. for about 10 seconds to about 30 seconds; step (d) is carried out at a temperature around 1100 ° C. for about 10 seconds;
• step (d) is carried out under a reducing atmosphere
• step (d) is carried out under a reducing atmosphere of argon and hydrogen or under a reducing atmosphere of argon; a sacrificial oxidation of a part of the first layer is implemented between step (c) and step (d);
• a plasma activation of at least one bonding surface is implemented before step (b);
• step (b) A heat treatment of more than 30 minutes and capable of reinforcing the bonding is further implemented after step (b);
• the atomic species implanted during step (a) consist of a single atomic element
• the atomic species implanted during step (a) comprise two distinct atomic elements, step (a) thus being a co-implantation; after step (c), the method does not include the implementation of mechanical polishing means;
• the method further comprises, after step (e), a crystal growth of Si y Ge y over the second layer to thicken the latter;
• the donor plate further comprises a third layer SH- x Ge x on the second layer;
• the donor wafer comprises a support substrate of bulk Si, a buffer structure made of SiGe, and a multilayer structure comprising alternating first layers of Si -x Ge x layers and second strained Ge y Si y, so as to achieve a plurality of samples from the same donor plate;
• each layer of Si y Ge forces is a greater thickness than the equilibrium critical thickness
• the method further comprises, before step (b), a step of forming a bonding layer on the donor plate (10) and / or on the receiving plate, the bonding layer comprising an electrically insulating material, as for example SiO 2 , Si 3 N 4 or Si x O y N z .
• the invention proposes an application of said method of forming a structure, to the formation of a semiconductor-on-insulator structure.
• FIGS. 1a to 1f show schematically the various steps of a method according to the invention for forming a structure comprising a layer taken by Smart-Cut®.
• Figures 2a and 2b show schematically a first variant according to the invention.
• Figures 3a and 3b show schematically a second variant according to the invention.
• FIG. 4 represents results of measurements carried out by secondary ion mass spectrometry making it possible to determine the concentration of germanium in a strained silicon layer taken according to the invention, compared with concentrations of germanium in Si (unconstrained) calculated from diffusion constants of the literature.
• FIG. 5 represents a comparative study of the germanium diffusion coefficients in an unstressed silicon layer and in a strained silicon layer.
• FIG. 1a to 1e there is shown a first method for drawing a first layer of Si 1 -x Ge x (with xe [0; 1]) and a second layer 2 of Si y Ge y ( with ye [0; 1] and y ⁇ x), from a donor plate 10, to transfer them to a receiving plate 20, according to the invention.
• a donor wafer 10 comprising the first layer of Si 1 -x Ge x layer and the second layer 2 of Si y Ge y to be removed, is illustrated.
• a donor wafer 10 including the Si -x Ge x includes a 5-solid Si substrate on which was formed, such as by crystal growth, a buffer structure made of SiGe (not shown) composed of different layers.
• the latter may have a gradual change in thickness of its Ge composition, ranging from 0% at the bulk Si substrate to about 100x% at the interface with the first layer 1 Sii -x Ge x (also preferentially formed by crystalline growth).
• the thickness for the layer Sii -x Ge x may for example be chosen around 1 micrometer.
• a second layer 2 of Si y Ge y is formed on the first layer of Si 1 -x Ge x.
• the growth of the second layer 2 is carried out in situ, directly in continuity with the formation of the first layer 1.
• the growth of the second layer 2 is carried out after a slight step of preparing the first layer 2.
• surface of the first layer for example by CMP polishing.
• the second layer 2 is advantageously formed by epitaxy using known techniques such as CVD and MBE techniques (abbreviations of "Chemical Vapor Deposition” and "Molecular Beam Epitaxy” respectively).
• CVD and MBE techniques abbreviations of "Chemical Vapor Deposition” and "Molecular Beam Epitaxy” respectively.
• the second layer 2 is then constrained by the first layer 1 so as to make its mesh parameter substantially identical to that of its growth substrate and thus present internal elastic stresses. These internal stresses are in tension if the silicon content in the alloy of the second layer 2 is greater than that of the first layer 1, and they are in compression in the opposite case. It is necessary to form a second thin layer 2: an excessively large layer thickness, greater than a critical equilibrium thickness, would indeed cause a relaxation of the stress in the thickness of this film towards the nominal mesh size parameter. Sii y Ge y and / or generation of defects. Reference can be made to Friedrich Schaffler's "High-mobility Si and Ge Structures"("Semiconductor Science Technology" 12 (1997) 1515-1549) for further details.
• a weakened zone 4 is then formed in the donor wafer 10 in the second layer 2.
• this implementation may be made in the first layer of Si 1 -x Ge x (as shown in Figure 1 (b).
• This embrittlement zone 4 is formed by implantation of atomic species whose dosage, nature, and energy are chosen so as to determine an implant depth and a level of weakness. In particular, the energy of the implantation is determined so that the weakening zone is formed below the second layer 2.
• this embrittlement zone 4 can be formed between about 1500 Angstroms and about 3000 Angstroms, and more particularly about 2000 Angstroms.
• an implantation of hydrogen species at an energy of between 20 and 80 keV and a dose of between 3.10 16 and 10.10 16 atoms / cm 2 , more particularly an energy around 30 keV and a dose around 6.10 16 atoms / cm 2 . It will thus be possible to obtain an implant depth of the order of 1000 to 5000 Angstroms.
• the parameters determining the implantation of atomic species are adjusted so as to minimize the roughness appearing at the zone of weakening 4 after detachment. Indeed, the extent of post-detachment roughness is partly related to these last parameters.
• a co-implantation of atomic species such as for example a co-implantation of hydrogen, and helium or argon or other inert gas.
• atomic species such as for example a co-implantation of hydrogen, and helium or argon or other inert gas.
• the weakening zone 4 is often thinner than in the case of a simple implantation (see in particular FR 04/09980 for more details).
• helium at approximately 1.10 16 / cm 2 and an energy of between 20 and 80 Kev
• hydrogen 1.10 16 / cm 2 and an energy of between 20 and 80 Kev
• Receiving plate 20 may be solid Si or other materials.
• a bonding layer may be formed, such as a layer comprising SiO 2, Si 3 N 4 , Si x O y N z on one and / or the other of the surfaces. respective to be glued.
• the technique used to form this bonding layer may be a deposit, in order to avoid any deterioration of the stresses in the second layer 2 or any consequent diffusion in the first layer 1.
• a preparation of at least one of the surfaces to be bonded can optionally be carried out, using known techniques of cleaning and surface preparation such as SC1 and SC2 solutions, ozonated solutions, or others.
• the bonding as such can be carried out firstly by molecular adhesion, taking into account the hydrophilicity that each of the two surfaces to be bonded has.
• the plasma activation can be implemented so that in the end, after gluing and after sampling, the gluing energy is greater than or equal to about 0.8 JIm 2 .
• the plasma may for example be obtained from an inert gas, such as Ar or N 2 , or from an oxidizing gas, such as IO 2 .
• a low temperature annealing heat treatment (less than or equal to 800 ° C.) can be implemented before bonding, so as to further strengthen the bonding interface.
• detachment of the layers taken at the weakening zone 4 is achieved by a supply of thermal energy and / or mechanical energy, sufficient to break the weak links at the level of the embrittlement 4, and thus detach the donor plate 10 in a first portion 10 'comprising a remainder of the first layer 1 'and a second part 30 comprising the other part of the first layer 1' and the second layer 2.
• This thermal energy can then be sufficient to cause, at the level of the embrittlement zone 4, thermal effects on the gaseous species enclosed therein causing the breaking of the weak bonds.
• the detachment may be obtained at temperatures between about 300 0 C and about 600 0 C for longer or shorter times depending on whether the temperature is respectively lower or higher. May for example implement, for a layer to be taken in Sii -x Ge x and Si-YGE there, a heat treatment at a temperature of about 500 0 C to about 600 0 C for a period ranging from 15 at 30 minutes up to 2 hours, and more particularly around 600 ° C.
• the remaining portion of the donor plate 10 provides protection to the first and second layers 1 and 2 removed against possible contaminants, oxidants, or other species, which offers the possibility of implementing the new heat treatment in different atmospheres.
• Heat treatment can also be done after the plates have been physically separated (and out of the detachment oven). This heat treatment can be implemented in addition to or in replacement of the plasma activation possibly used before bonding.
• the heat treatment for reinforcing the bonding interface 6 is carried out at a temperature between about 35O 0 C and about 800 0 C, in particular between about 35O 0 C and about 700 0 C, particularly at about 600 0 C, maintained for about 30 minutes to about 4 hours, and is implemented so to sufficiently reinforce the bonding (and thus prevent the risk of edge delamination during the selective etching that will be implemented after sampling).
• a rapid thermal annealing also called RTA, of the "Rapid Thermal Annealing” is implemented. implemented at a temperature greater than or equal to about 1000 0 C for a period not exceeding about 5 minutes.
• This RTA is preferably carried out under a reducing atmosphere, such as an atmosphere of Argon and Hydrogen or Argon only.
• RTA between about 1000 0 C and about 1200 0 C for about 10 to about 30 seconds, in particular at about 1100 0 C for about 10s.
• This temperature of 1000 ° C. or more is a temperature which is conventionally not used when there are two layers 1 and 2 having different concentrations of Ge. Indeed, it has been recognized (see, for example, the paper by M. Griglione et al entitled “Diffusion of Ge in Sii -x Ge x / Si single quantum well in inert and oxidazing ambients" (Journal of Applied Physics, vol. 88, No. 3, August 1, 2000)) that the heat treatments carried out at these temperatures resulted diffusion of Ge from the layer having the Ge content the stronger toward the layer having the content of Ge lowest, thus tending to homogenize the Ge content in all of the two layers, and thus to no longer differentiate the physical and electrical properties of the two layers.
• the Applicant has however made a series of studies on structures Sii -x Ge x / Si y Ge y forced / SiO 2 / Si plate solid obtained just after detachment, showing that the distribution of Ge during treatment with 800 0 C or more is not as marked as it was advanced.
• the Applicant has demonstrated that an RTA as previously described can thus be implemented without the diffusion between the first layer 1 'and the second layer 2 is consistent.
• the x-axis of the graph of FIG. 4 represents the depth probed in the samples tested, from the free surface of the first layer Y.
• FIG. 4 is divided into a left part Y representing the first layer Y and a right part 2 representing the second layer 2, separated by a vertical line 12 representing the interface between the first layer 1 'and the second layer 2.
• the "y" axis of Figure 4 represents the concentration of germanium found by the measurements.
• the measurements were performed by secondary ion mass spectrometry on three samples, after these have undergone heat treatments at temperatures of 75O 0 C, 800 ° C and 85O 0 C for four hours, and the respective measurement results being represented by the diffusion profiles 62, 63 and 64.
• Figure 4 further includes diffusion profiles calculated theoretically from the data provided in the document by M. Griglione et al. entitled “Diffusion of Ge in Si -x Ge x / Si single quantum wells and in inert ambients oxidazing" (Journal of Applied Physics, Vol. 88, No. 3, August 1, 2000), in which a study of a layer of relaxed silicon / Sio. ⁇ sGeo.is has been realized.
• the diffusion profiles 52, 53, 54 are then found after having integrated in the calculations heat treatments, at temperatures of 75O 0 C, 800 0 C, 85O 0 C for four hours.
• diffusion profiles 53, 54 tend to be closer to the initial profile (after epitaxy) than the diffusion profiles given in the state of the art (i.e. diffusion profiles 53, 54).
• the Applicant has calculated the diffusion coefficient "D" (in square centimeters per second) (ie the y-axis) according to the temperature of the heat treatment performed on the samples (the abscissa axis representing the inverse of the temperature "T" in Kelvin multiplied by 10,000).
• the points 83 and 84 respectively represent the scattering coefficients found from the measured diffusion profiles 63 and 64 of Figure 3.
• the points 73 and 74 were found by Griglione (see the document reference above) and correspond to diffusions found after heat treatments respectively at 800 0 C and 85O 0 C for four hours.
• the diffusion coefficients in the second strained Si layer 2 are of the order of four times lower than in a second relaxed Si layer 2, at the temperatures considered.
• the results obtained by the Applicant thus show that the diffusion of Ge is surprisingly reduced in the case of a second layer 2 in Si constrained in relation to the case where she would be in Si relaxed.
• Post-stripping heat treatments carried out at temperatures above the temperatures conventionally employed can then be envisaged.
• the Applicant has thus implemented rapid thermal annealing at high temperature (RTA) according to the invention, and then demonstrated that their influence on the diffusion of germanium in the second layer 2 of Si constrained were much lower than what would have been deducted from prior technical education.
• RTA rapid thermal annealing at high temperature
• This latter post-detachment roughness could previously be limited by having previously adapted the implantation conditions, as previously seen (H and He co-implantation), and / or a fracture annealing at
• the RTA can lead to an encapsulation of the oxide layer by smoothing effect of the SiGe layer on the plate edges, as described in the document FR 03/02623, which tends to limit further advantage delamination problems at the interface at the time of selective etching.
• This sacrificial oxidation is implemented for example at a temperature below 65O 0 C.
• the thickness removed may be around
• the first layer the Sii -x Ge x is optionally removed to obtain a final Si y Ge y constrained structure on insulator. It may then be possible to thicken the thickness of Si-I- y Ge y constrained by epitaxy.
• selective chemical etching can be carried out using chemical agents adapted to the materials in the presence.
• the etching time is directly correlated with the speed of the etching. It is typically about 5 minutes for 800A to be etched with CH 3 COOH / H 2 O 2 / HF.
• the first layer has a Ge concentration of less than or equal to 20% (ie x ⁇ 0.2) and the second layer 2 has a Ge concentration greater than 25% (ie y ⁇ 0). , 25), TMAH or KOH can then be used to remove the remainder of the first layer 1a.
• the implementation of RTA possibly combined with the prior implementation of a co-implantation and / or a plasma activation and / or a low temperature thermal treatment for reinforcing the bonding interface and / or sacrificial oxidation, having considerably reduced the surface roughness and non-uniformity of thickness in the layers taken 1 and 2, makes it possible to implement a selective etching substantially identical to those of the state of the art but also by removing the disadvantages it could present, such as the need to previously implement mechanical polishing means.
• the strengthening of the bonding (carried out at least by RTA) is sufficient to overcome the problems of edge delamination mentioned above.
• a thin etching the surface layer of Sii -y strained Ge y (SC1 by treatment for example) can follow the selective etching to remove the surface of this layer, a thin layer of material wherein the Ge could disseminate.
• the process may optionally be terminated by a high temperature stabilization step to close the bonding interface and / or by a furnace or RTA annealing to achieve a final smoothing of the coating layer.
• a subsequent step of crystal growth e.g. epitaxy MBE or CVD
• a subsequent step of crystal growth e.g. epitaxy MBE or CVD
• the donor plate 10 comprises, successively before sampling, a first layer 1 made of Si 1 -x Ge x , a second layer 2 made of Si 1 -y Ge which then constrains, then a third layer of Si 3-x Ge x.
• the embrittlement zone is then formed according to the invention beneath the second layer 2, for example in the first layer 1.
• a selective etching of Si -x Ge x can then be implemented after RTA, in accordance with what was seen previously, so as to perform ultimately a 30 Si y Ge structure forced y / Sii -x Ge x on insulator (as shown in Figure 2b) with a second layer 2 of Si y Ge y constrained and a third layer 3 in
• the second layer 2 of Si y Ge y constrained by crystal growth may be thickened.
• the second layer 2 of strained Si not here plays the role of a barrier layer protecting the third layer of Si 3-x Ge x of the first etching.
• a SiGeOI structure (not shown) is then obtained.
• the donor wafer 10 before sampling comprises a multilayer structure comprising alternating first layers 1A, 1 B, 1C, 1 D, 1 E in Sii -x Ge x and second layers 2A, 2B, 2C, 2D, 2E in Si-i-yG ⁇ y constrained. It is thus possible to carry out a plurality of samples according to the invention from the same donor plate 10, each sample then being followed by recycling of the remaining part of the donor plate 10 in order to prepare it for a new sample.
• a first structure 3OA Sii -y Ge y constrained on insulator and a second structure 3OB Sii -y Ge y constrained on insulator from the same donor plate 10 will be formed.
• This type of sampling is taught in document US2004 / 0053477.
• each stressed layer [referenced “2" in FIGS. 1a to 1f, 2a and 2b, and “2A”, “2B”, “2C”, “2D” or “2E” in FIGS. 3a and 3b] of the donor plate 10 is thick, that is to say that it has a thickness greater than the critical equilibrium thickness (thickness from which the elastic stresses begin to relax) without presenting any relaxation of its elastic constraints. This has been made possible by low temperature epitaxial formation.
• a strained Si layer deposited at temperatures between about 45O 0 C and 65O 0 C on a growth support Si o, o 8GE, 2 can reach typically a thickness between about 30 nm and 60 nm without its constraints relax in one way or another.
• thick stress layer will advantageously be implemented plasma activation before bonding (as discussed above) which is typically at an ambient temperature of less than about 100 0 C.
• at least one layer bonding material of dielectric material such as SiO 2 , is advantageously formed on one or both surfaces to be bonded, this layer of dielectric material subsequently helping (ie after detachment) to retain the elastic stresses.
• a post-detachment heat treatment at a temperature T can be implemented, T being advantageously less than the deposition temperature of the thick-stressed layer in the case where no bonding layer has been planned.
• the man of the art can easily implement the invention in the case of minority species are added to the layers Sii Sii -x Ge x and y Ge y, for example by adding dopant species and / or a small amount of carbon (about 5% or less).

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