WO2006077216A3 - Formation et traitement d'une structure en sige - Google Patents

Formation et traitement d'une structure en sige Download PDF

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Publication number
WO2006077216A3
WO2006077216A3 PCT/EP2006/050261 EP2006050261W WO2006077216A3 WO 2006077216 A3 WO2006077216 A3 WO 2006077216A3 EP 2006050261 W EP2006050261 W EP 2006050261W WO 2006077216 A3 WO2006077216 A3 WO 2006077216A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
donor plate
plate
formation
treatment
Prior art date
Application number
PCT/EP2006/050261
Other languages
English (en)
Other versions
WO2006077216A2 (fr
Inventor
Nicolas Daval
Original Assignee
Soitec Silicon On Insulator
Nicolas Daval
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0500524A external-priority patent/FR2880988B1/fr
Application filed by Soitec Silicon On Insulator, Nicolas Daval filed Critical Soitec Silicon On Insulator
Priority to EP06703581A priority Critical patent/EP1839332A2/fr
Priority to JP2007551665A priority patent/JP4975642B2/ja
Priority to CN2006800081591A priority patent/CN101142669B/zh
Publication of WO2006077216A2 publication Critical patent/WO2006077216A2/fr
Publication of WO2006077216A3 publication Critical patent/WO2006077216A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de formation d'une structure (30) comprenant une couche prélevée (2) à partir d'une plaque donneuse (10), la plaque donneuse (10) comprenant avant prélèvement une première couche (1) en Si1-xGex et une deuxième couche (2) sur la première couche (1) en Si1-yGey (x, y étant respectivement compris entre 0 et 1, et x étant différent de y), le procédé comprenant les étapes suivantes : a) implantation d'espèces atomiques pour former une zone de fragilisation (4) sous la deuxième couche (2) ; b) collage de la plaque donneuse (10) à une plaque réceptrice (20) ; c) apport d'énergie pour détacher les couches prélevées (1' et 2) de la plaque donneuse (10) au niveau de la zone de fragilisation (4) ; d) recuit thermique rapide (encore appelé RTA) mis en oeuvre à une température égale ou supérieure à environ 1000°C pendant une durée ne dépassant pas 5 minutes ; e) gravure sélective de la partie restante de la première couche (1') vis à vis de la deuxième couche (2).
PCT/EP2006/050261 2005-01-19 2006-01-17 Formation et traitement d'une structure en sige WO2006077216A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06703581A EP1839332A2 (fr) 2005-01-19 2006-01-17 Formation et traitement d'une structure en sige
JP2007551665A JP4975642B2 (ja) 2005-01-19 2006-01-17 ＳｉＧｅ構造の形成および処理
CN2006800081591A CN101142669B (zh) 2005-01-19 2006-01-17 SiGe结构的形成和处理

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0500524 2005-01-19
FR0500524A FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
US11/145,482 2005-06-02
US11/145,482 US7232737B2 (en) 2005-01-19 2005-06-02 Treatment of a removed layer of silicon-germanium

Publications (2)

Publication Number Publication Date
WO2006077216A2 WO2006077216A2 (fr) 2006-07-27
WO2006077216A3 true WO2006077216A3 (fr) 2007-02-08

Family

ID=36692598

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/050261 WO2006077216A2 (fr) 2005-01-19 2006-01-17 Formation et traitement d'une structure en sige

Country Status (3)

Country Link
EP (1) EP1839332A2 (fr)
KR (1) KR20070090251A (fr)
WO (1) WO2006077216A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009056169A1 (fr) * 2007-10-31 2009-05-07 Robert Bosch Gmbh Anneau de courroie d'entraînement et procédé de fabrication de celui-ci
US9870940B2 (en) * 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (fr) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Substrat du type SOI fabriqué par collage
EP1193740A2 (fr) * 2000-09-29 2002-04-03 Canon Kabushiki Kaisha Procédé de recuit d'un substrat du type SOI et substrat du type SOI
WO2003103026A1 (fr) * 2002-06-03 2003-12-11 Tien-Hsi Lee Procedes permettant le transfert d'une couche sur un substrat
US20040053477A1 (en) * 2002-07-09 2004-03-18 S.O.I. Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US20040060900A1 (en) * 2002-10-01 2004-04-01 Ann Waldhauer Apparatuses and methods for treating a silicon film
US20040195656A1 (en) * 2003-02-28 2004-10-07 Bruno Ghyselen Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003168789A (ja) * 2001-11-29 2003-06-13 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961312A2 (fr) * 1998-05-15 1999-12-01 Canon Kabushiki Kaisha Substrat du type SOI fabriqué par collage
EP1193740A2 (fr) * 2000-09-29 2002-04-03 Canon Kabushiki Kaisha Procédé de recuit d'un substrat du type SOI et substrat du type SOI
WO2003103026A1 (fr) * 2002-06-03 2003-12-11 Tien-Hsi Lee Procedes permettant le transfert d'une couche sur un substrat
US20040053477A1 (en) * 2002-07-09 2004-03-18 S.O.I. Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US20040060900A1 (en) * 2002-10-01 2004-04-01 Ann Waldhauer Apparatuses and methods for treating a silicon film
US20040195656A1 (en) * 2003-02-28 2004-10-07 Bruno Ghyselen Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1839332A2 *

Also Published As

Publication number Publication date
WO2006077216A2 (fr) 2006-07-27
KR20070090251A (ko) 2007-09-05
EP1839332A2 (fr) 2007-10-03

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