KR20070090251A - ＳｉＧｅ 구조체 제조 및 처리방법 - Google Patents

ＳｉＧｅ 구조체 제조 및 처리방법 Download PDF

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Publication number
KR20070090251A
KR20070090251A KR1020077016429A KR20077016429A KR20070090251A KR 20070090251 A KR20070090251 A KR 20070090251A KR 1020077016429 A KR1020077016429 A KR 1020077016429A KR 20077016429 A KR20077016429 A KR 20077016429A KR 20070090251 A KR20070090251 A KR 20070090251A
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KR
South Korea
Prior art keywords
layer
temperature
proceeds
donor wafer
heat treatment
Prior art date
Application number
KR1020077016429A
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English (en)
Korean (ko)
Inventor
니콜라스 다발
Original Assignee
에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0500524A external-priority patent/FR2880988B1/fr
Application filed by 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 filed Critical 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
Publication of KR20070090251A publication Critical patent/KR20070090251A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
KR1020077016429A 2005-01-19 2006-01-17 ＳｉＧｅ 구조체 제조 및 처리방법 KR20070090251A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0500524 2005-01-19
FR0500524A FR2880988B1 (fr) 2005-01-19 2005-01-19 TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
US11/145482 2005-06-02
US11/145,482 US7232737B2 (en) 2005-01-19 2005-06-02 Treatment of a removed layer of silicon-germanium

Publications (1)

Publication Number Publication Date
KR20070090251A true KR20070090251A (ko) 2007-09-05

Family

ID=36692598

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077016429A KR20070090251A (ko) 2005-01-19 2006-01-17 ＳｉＧｅ 구조체 제조 및 처리방법

Country Status (3)

Country Link
EP (1) EP1839332A2 (fr)
KR (1) KR20070090251A (fr)
WO (1) WO2006077216A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170016269A (ko) * 2015-08-03 2017-02-13 삼성전자주식회사 반도체 장치의 나노시트를 형성하는 방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009056169A1 (fr) * 2007-10-31 2009-05-07 Robert Bosch Gmbh Anneau de courroie d'entraînement et procédé de fabrication de celui-ci

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
US6660606B2 (en) * 2000-09-29 2003-12-09 Canon Kabushiki Kaisha Semiconductor-on-insulator annealing method
JP2003168789A (ja) * 2001-11-29 2003-06-13 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
WO2003103026A1 (fr) * 2002-06-03 2003-12-11 Tien-Hsi Lee Procedes permettant le transfert d'une couche sur un substrat
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170016269A (ko) * 2015-08-03 2017-02-13 삼성전자주식회사 반도체 장치의 나노시트를 형성하는 방법

Also Published As

Publication number Publication date
WO2006077216A2 (fr) 2006-07-27
EP1839332A2 (fr) 2007-10-03
WO2006077216A3 (fr) 2007-02-08

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Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E601 Decision to refuse application