EP1817795A1 - Feuille metallisee pour etablissement de contact en nappe - Google Patents

Feuille metallisee pour etablissement de contact en nappe

Info

Publication number
EP1817795A1
EP1817795A1 EP05815728A EP05815728A EP1817795A1 EP 1817795 A1 EP1817795 A1 EP 1817795A1 EP 05815728 A EP05815728 A EP 05815728A EP 05815728 A EP05815728 A EP 05815728A EP 1817795 A1 EP1817795 A1 EP 1817795A1
Authority
EP
European Patent Office
Prior art keywords
insulating film
substrate
metallization
contact surface
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05815728A
Other languages
German (de)
English (en)
Inventor
Karl Weidner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1817795A1 publication Critical patent/EP1817795A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Definitions

  • the invention relates to a method for contacting one or more electrical contact surfaces on a surface of a substrate and / or at least one component, comprising the step of laminating at least one insulating film of electrically insulating plastic material on the surfaces of the substrate and the component under vacuum, so that the insulating film the surface is tightly covered with the contact surface or surfaces and adheres to this surface.
  • WO03 / 030247 discloses a method of contacting, comprising the further steps of exposing each contact surface to be contacted on the surface by opening respective windows in the film, and contacting each exposed contact surface with a layer of electrically conductive material. According to this method, at least one printed conductor is produced after the surface contacting in and / or on the layer of the electrically conductive material. To produce a multilayer device, the steps of laminating, exposing, contacting and producing the printed conductor are carried out several times.
  • a disadvantage of the conventional contacting method is the effort to be made for contacting, in particular of components on a surface of a substrate. A large number of process steps are required.
  • Allow components on a substrate surface The object is achieved by a method according to the main claim and a device according to the independent claim. Advantageous embodiments can be found in the subclaims.
  • the present method is used to contact only a substrate structure or at least one component on a substrate or at least one component with a substrate together.
  • At least one metallization formed on at least one surface side of the insulating film. This serves to provide interconnects or trace or
  • connection structures can already be formed by means of conventional methods prior to lamination.
  • the films can be produced with one-sided metallization or with two-sided metallization on an insulating film.
  • a metallized insulating film is particularly suitable over the entire surface, part of the surface or pre-structured with conductor tracks copper coating a plastic film.
  • Other metals in particular comparable in electrical resistivity or in processability, may also be used.
  • Windows can be easily generated mechanically, eg, by punching, chemically, eg by etching, or physically, by lasing, plasma opening, before or after the respective laminating step.
  • the contacting may be performed by inserting the metallization toward the electrical contact surface or by leading the electrical contact surface out to the metallization.
  • the contacting takes place at an advantageous pressure and at an advantageous temperature. Surface contact is preferred.
  • Suitable components are electronic components, LEDs, semiconductor chips or power semiconductor chips. A multiplicity of process steps of conventional contacting methods can be dispensed with.
  • Suitable substrates are any circuit carriers based on organic or inorganic substances.
  • Such substrates include PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
  • the lamination is advantageously carried out in a vacuum press. Vacuum thermoforming, hydraulic vacuum pressing, vacuum gas pressure pressing or similar laminating methods are conceivable for this purpose.
  • the pressure is advantageously applied isostatically.
  • the lamination takes place for example at temperatures of 100 0 C to 25O 0 C and a pressure of 1 bar to 10 bar.
  • the exact process parameters of the lamination, ie pressure, temperature, time, etc., depend inter alia on the topology of the substrate, the plastic material of the insulating film and the thickness of the insulating film.
  • a physical or chemical deposition of the electrically conductive material is advantageously carried out.
  • Such physical methods are sputtering and vapor deposition (Physical Vapor Deposition, PVD).
  • the chemical deposition can be carried out from the gaseous phase (chemical vapor deposition, CVD) and / or liquid phase (liquid phase chemical vapor deposition). It is also conceivable that initially by one of these methods, a thin electrically conductive sub-layer is applied, on which then a thicker electrically conductive sub-layer is electrodeposited.
  • a substrate having a surface which is equipped with one or more semiconductor chips, in particular power semiconductor chips, on each of which one or more contact surfaces to be contacted is or are present, and wherein the at least one insulating film
  • This surface is vacuum-laminated so that the insulating film closely covers and adheres to this surface including each semiconductor chip and each pad, including each semiconductor chip.
  • the insulating film is designed, for example, so that in particular a height difference of up to about 5 mm can be overcome.
  • the height difference is caused inter alia by the topology of the substrate and by the semiconductor chips arranged on the substrate.
  • SMD surface mounted device components can be applied, for example soldered on.
  • the insulating film may consist of any thermoplastics, thermosets and mixtures thereof.
  • a film of a plastic material on polyimide (PI), polyethylene (PE), polyphenol, is advantageously used as film.
  • the film may have an adhesive coating to improve the adhesion on the surface.
  • This additional insulating film has no opening, but preferably in the region of the opening on the metallization.
  • a substrate with a surface equipped with one or more power semiconductor chips is used.
  • Metallizations on different surface sides electrically connected to each other. This can be done via pins.
  • Insulating films made of a plastic material on polyimide, polyethylene, polyphenol, Polyetheretherketon- and / or epoxy-based and used as one-sided or two-sided metallizations copper, aluminum, iron and / or silver or similar electrical conductors.
  • Plastic film can thus be coated on one side of the surface or on both surfaces with metal.
  • pure metal layers can also be used.
  • connection structure corresponds to the required connection of electrical or electronic components that can be applied to a substrate by conventional methods.
  • the metal structure can be produced, for example, via a photolithographic process. Conventional structuring methods are equally applicable.
  • the metallization of the insulating film can be structured by laser ablation, stamping, etching or by a photolithographic process.
  • each exposed contact surface can be carried out by means of thermal pressing, soldering and / or gluing the metalized insulating foil having the metallization.
  • additional metallized connecting foils having at least one metallization may be used.
  • the connecting foils can be fixed by soldering or gluing.
  • the Antitle ist each exposed contact surface by means of soldering and / or gluing the metallized insulating film, that is, the metallization having insulating performed.
  • the contacting takes place areally.
  • the contacting can take place from the metallized insulating film into the exposed contact surface.
  • the execution of the exposed contact surface outwards to the metal interconnects is also feasible with appropriate provision of the contact surfaces.
  • the lamination of the Isolier Anlagen von Heidelberg Kunststoffmaschine is repeated such that a multilayer structure is generated. Likewise, insulating layer thicknesses can thereby be increased.
  • a metallized insulating film with a thickness (d), for example, in particular in the range of 25 to 250 microns is used.
  • an insulating covering on the side of the uppermost insulating film facing away from the substrate, and a metal layer applied to this insulating cover to produce a hermetic seal and direct contact of the metal layer by means of a direct metal connection to an edge region of the substrate.
  • the metal layer serves as a mechanical protection, as a cover, with heat-dissipating properties. Between metal layer and the one Metallized insulating foil, the insulating cover serves as electrical insulation.
  • FIG. 1 shows an illustration of a first exemplary embodiment of a device or the method according to the invention
  • FIG. 2 shows an illustration of a second exemplary embodiment of the device according to the invention or of the method
  • FIG. 3 shows an illustration of a third embodiment of the device according to the invention
  • Fig. 4 is a highly simplified plan view of the third embodiment of the device according to the invention Shen.
  • FIG. 1 shows the construction of a device according to an embodiment with at least one electrical contact surface 1 on a surface of a substrate 2 and / or at least one arranged on the substrate
  • Component 3 On the surfaces of the substrate 1 and the component 3 is at least one electrically insulating Insulating film 4, which bears tightly against the underlying surface and adheres, laminated by vacuum. At least one metallization 5 is applied to at least one surface side of the at least one insulating film 4.
  • the insulating film 4 has at least one window 6 in the contact surface 1, in which the contact surface 1 is in contact with the metallization 5 in a planar manner.
  • an insulating cover 7 is applied to the insulating film 4, and a metal layer 8 is applied to the insulating cover 7, wherein a direct contact of the
  • Metal layer is produced by means of a direct metal connection to an edge region of the substrate for producing a hermetic seal of the device.
  • a cooling body 9 is arranged above the hermetic seal and below the substrate.
  • each exposed contact surface 1 by means of soldering and / or gluing the metallized insulating film 4a is performed. Comparable connection methods are also applicable.
  • the contacting takes place areally.
  • the contacting can take place from the metallized insulating film 4a into the exposed contact surface.
  • the execution of metallized connecting foils 4b (provided separately or as a continuation of the contact surface 1) from the exposed contact surface 1 to the outside to the metal interconnects 5 is also feasible with appropriate provision of the contact surfaces 1.
  • Fig. 3 shows how a metallized insulating film 4a exposed over the outer edges of the substrate 2 and structured for connection to external terminals can be used. This can also compensate for differences in height. This type of flexible AnAuthierung replaces or complements additional connector connections or comparable connection solutions.
  • the film and copper thicknesses can be variably adapted to the respective mechanical, electrical, thermal and comparable requirements.
  • the metallized insulating film 4 a is produced over an insulating film 4 on the left side of the substrate 2 beyond the substrate 2 over a support 10 with non-adhesive properties, for example a Teflon structure 10.
  • the Teflon layer 10 can be removed or separated from the insulating films 4 and 4a in such a way that they are exposed or exposed to the substrate 2.
  • Fig. 4 shows a highly simplified view of FIG. 3 from above.
  • the exposed insulating films 4 and 4a are clearly visible. These each extend beyond the surface of the substrate 2.
  • a hermetic cover of the device by means of a metal layer 8 over an insulating cover 7 may additionally be produced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de mise en contact d'au moins une surface de contact électrique (1) sur une surface d'un substrat (2) et/ou d'au moins un composant (3) disposé sur ce substrat (2), en particulier une puce semi-conductrice. Ce procédé consiste à appliquer sous vide au moins une feuille d'isolation (4) constituée d'une matière plastique électriquement isolante sur les surfaces du substrat (2) et du composant qui présentent la surface de contact (1), puis à mettre à nu la surface de contact (1) à mettre en contact sur les surfaces par ouverture d'une fenêtre (6) dans la couche d'isolation (4). L'invention se caractérise en ce que la surface de contact (1) mise à nu est mise en contact en nappe avec au moins une métallisation (5) sur une couche d'isolation (4).
EP05815728A 2004-11-29 2005-11-21 Feuille metallisee pour etablissement de contact en nappe Withdrawn EP1817795A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004057494A DE102004057494A1 (de) 2004-11-29 2004-11-29 Metallisierte Folie zur flächigen Kontaktierung
PCT/EP2005/056094 WO2006058850A1 (fr) 2004-11-29 2005-11-21 Feuille metallisee pour etablissement de contact en nappe

Publications (1)

Publication Number Publication Date
EP1817795A1 true EP1817795A1 (fr) 2007-08-15

Family

ID=35735117

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05815728A Withdrawn EP1817795A1 (fr) 2004-11-29 2005-11-21 Feuille metallisee pour etablissement de contact en nappe

Country Status (6)

Country Link
US (1) US7910470B2 (fr)
EP (1) EP1817795A1 (fr)
JP (1) JP2008522394A (fr)
CN (1) CN100472783C (fr)
DE (1) DE102004057494A1 (fr)
WO (1) WO2006058850A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007043001A1 (de) * 2007-09-10 2009-03-12 Siemens Ag Bandverfahren für elektronische Bauelemente, Module und LED-Anwendungen
DE102007057346B3 (de) * 2007-11-28 2009-06-10 Fachhochschule Kiel Laminierte Leistungselektronikbaugruppe
DE102008003788A1 (de) * 2008-01-10 2009-07-16 Robert Bosch Gmbh Elektrische Schaltungsanordnung mit mindestens einem Leistungshalbleiter und Verfahren zu deren Herstellung
US8410600B2 (en) * 2009-10-02 2013-04-02 Arkansas Power Electronics International, Inc. Semiconductor device with protecting film and method of fabricating the semiconductor device with protecting film
CN102104083B (zh) * 2009-11-30 2012-05-23 杜邦太阳能有限公司 薄膜光伏面板及其制造方法
DE102010012457B4 (de) * 2010-03-24 2015-07-30 Semikron Elektronik Gmbh & Co. Kg Schaltungsanordnung mit einer elektrischen Komponente und einer Verbundfolie
DE102011083423A1 (de) * 2011-09-26 2013-03-28 Siemens Aktiengesellschaft Kontaktfederanordnung und Verfahren zur Herstellung derselben
US8716870B2 (en) * 2011-12-16 2014-05-06 General Electric Company Direct write interconnections and method of manufacturing thereof
US20130264721A1 (en) 2012-04-05 2013-10-10 Infineon Technologies Ag Electronic Module
DE102012218561A1 (de) * 2012-10-11 2014-04-17 Siemens Aktiengesellschaft Elektronikmodul, Mehrfachmodul und Verfahren zum Herstellen eines Elektronikmoduls
WO2016080333A1 (fr) * 2014-11-21 2016-05-26 株式会社村田製作所 Module
DE102017210894A1 (de) * 2017-06-28 2019-01-03 Robert Bosch Gmbh Elektronikmodul und Verfahren zur Herstellung eines Elektronikmoduls

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL159818B (nl) * 1972-04-06 1979-03-15 Philips Nv Halfgeleiderinrichting, bevattende een flexibele isolerende folie, die aan een zijde is voorzien van metalen geleider- sporen.
US4918811A (en) * 1986-09-26 1990-04-24 General Electric Company Multichip integrated circuit packaging method
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
DE4219410A1 (de) * 1992-06-13 1993-12-16 Hoechst Ag Heißsiegelfähige, antistatisch beschichtete Folien und Folienlaminate, Verfahren zu deren Herstellung und deren Verwendung
US5336928A (en) * 1992-09-18 1994-08-09 General Electric Company Hermetically sealed packaged electronic system
US5492586A (en) * 1993-10-29 1996-02-20 Martin Marietta Corporation Method for fabricating encased molded multi-chip module substrate
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
DE19617055C1 (de) 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
US6239980B1 (en) * 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6710456B1 (en) * 2000-08-31 2004-03-23 Micron Technology, Inc. Composite interposer for BGA packages
US7432116B2 (en) * 2001-02-21 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Method and apparatus for film deposition
DE10121970B4 (de) 2001-05-05 2004-05-27 Semikron Elektronik Gmbh Leistungshalbleitermodul in Druckkontaktierung
US6788724B2 (en) * 2001-07-06 2004-09-07 Intel Corporation Hermetically sealed external cavity laser system and method
DE10136743B4 (de) * 2001-07-27 2013-02-14 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelementes
AU2002340750A1 (en) * 2001-09-28 2003-04-14 Siemens Aktiengesellschaft Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces
DE10164502B4 (de) * 2001-12-28 2013-07-04 Epcos Ag Verfahren zur hermetischen Verkapselung eines Bauelements
US7208347B2 (en) * 2003-02-28 2007-04-24 Siemens Aktiengesellschaft Connection technology for power semiconductors comprising a layer of electrically insulating material that follows the surface contours
DE10308928B4 (de) * 2003-02-28 2009-06-18 Siemens Ag Verfahren zum Herstellen freitragender Kontaktierungsstrukturen eines ungehäusten Bauelements
CN100468670C (zh) * 2003-02-28 2009-03-11 西门子公司 带有大面积接线的功率半导体器件的连接技术
DE10314172B4 (de) * 2003-03-28 2006-11-30 Infineon Technologies Ag Verfahren zum Betreiben einer Anordnung aus einem elektrischen Bauelement auf einem Substrat und Verfahren zum Herstellen der Anordnung
JP4471735B2 (ja) * 2004-05-31 2010-06-02 三洋電機株式会社 回路装置
DE102006009723A1 (de) * 2006-03-02 2007-09-06 Siemens Ag Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006058850A1 *

Also Published As

Publication number Publication date
WO2006058850A1 (fr) 2006-06-08
US20080093727A1 (en) 2008-04-24
CN100472783C (zh) 2009-03-25
CN101061582A (zh) 2007-10-24
DE102004057494A1 (de) 2006-06-08
US7910470B2 (en) 2011-03-22
JP2008522394A (ja) 2008-06-26

Similar Documents

Publication Publication Date Title
EP1817795A1 (fr) Feuille metallisee pour etablissement de contact en nappe
WO2003030247A2 (fr) Procede d&#39;etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d&#39;un substrat pourvu de surfaces de contact electriques
DE102011088218B4 (de) Elektronisches Leistungsmodul mit thermischen Kopplungsschichten zu einem Entwärmungselement und Verfahren zur Herstellung
EP1597757A2 (fr) Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface
DE10314172B4 (de) Verfahren zum Betreiben einer Anordnung aus einem elektrischen Bauelement auf einem Substrat und Verfahren zum Herstellen der Anordnung
DE102004019431A1 (de) Hybrider Leiterplattenaufbau zur kompakten Aufbautechnik von elektrischen Bauelementen
WO2016016140A1 (fr) Support de circuit, module électronique, procédé servant à fabriquer un support de circuit
WO2016193038A1 (fr) Procédé de connexion électrique d&#39;un composant au moyen de la liaison galvanique d&#39;une pièce de contact à pores ouverts, et ensemble composant correspondant
WO2009034008A2 (fr) Procédé sur bande pour composants électroniques, modules et applications del
DE102011083627A1 (de) Verfahren zur Kontaktierung eines elektronischen Bauteils und Baugruppe mit einem elektronischen Bauteil auf einem Substrat
EP1597755A2 (fr) Structures de mise en contact autoportantes produites directement sur des composants sans boitier
DE102006012007B4 (de) Leistungshalbleitermodul mit oberflächenmontierbaren flachen Außenkontakten und Verfahren zur Herstellung desselben und dessen Verwendung
EP0862209B1 (fr) Procédé de fabrication d&#39;un substrat métal-céramique
DE102009040627B4 (de) Halbleiterbauelement und Verfahren zum Herstellen eines elektronischen Systems
EP2100331A1 (fr) Module de composant électronique et son procédé de fabrication
WO2004077547A2 (fr) Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues
EP2294613B1 (fr) Modules électriques plans d&#39; électronique de puissance pour des applications sous haute température et procédé de fabrication correspondant
WO2014097835A1 (fr) Substrat multicouche en résine
WO2006058860A2 (fr) Dispositif d&#39;echange thermique, procede pour fabriquer ce dispositif d&#39;echange thermique, ensemble compose d&#39;un composant et dudit dispositif d&#39;echange thermique et procede pour fabriquer cet ensemble
WO2001097285A2 (fr) Composant electronique constitue d&#39;un boitier et d&#39;un substrat
EP1987536B1 (fr) Procédé de fabrication sélective de stratifiés en feuilles pour l&#39;emballage et pour l&#39;isolation de composants électroniques et de structures fonctionnelles sans boîtiers
WO2005101480A2 (fr) Circuit monte sur un substrat notamment electroconducteur par connexion planaire
WO2005078793A1 (fr) Procede pour realiser un module de puissance, et module de puissance
DE102004019442A1 (de) An planarer Verbindung angeordneter Kühlkörper
EP3154081A2 (fr) Procédé de fabrication de modules électroniques par connexion d&#39;un élément métallique à une surface céramique d&#39;un substrat par une pâte à base de poudre métallique

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20070413

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20120601