Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0041—Arrangements at the transmitter end
  • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L2001/0092—Error control systems characterised by the topology of the transmission link
  • H04L2001/0094—Bus

Definitions

• the invention relates to a system including a signal or data bus, and in particular to a method and apparatus for reducing ground bounce in the buses of high speed, high density integrated circuits that use fault tolerant error correcting codes.
• FIG. 1 shows a schematic illustration of a typical fault tolerant bus structure 1.
• the bus structure 1 comprises a communication bus 3 for communicating data between an encoder 5 and decoder 7.
• the bus 3 receives output data 9 from the encoder 5, and provides input data 11 to the decoder 7.
• One fault tolerant method is known as 'dual-rail encoding'.
• dual-rail encoding a data bit is copied, and the copy can be used to correct errors in the data bit.
• Figure 2 shows a prior art dual-rail bus structure 20.
• the input data bits dO, dl, d2 and d3 are the signals provided to the encoder 22. Respective copies cO, cl, c2 and c3 of the data bits dO, dl, d2 and d3 are created.
• a parity bit, Tparity is calculated for the data bits to be transmitted using a parity tree 24 comprising, for example, exclusive OR gates 26, 28 and 30.
• the transmitted data parity bit, Tparity, data bits dO, dl, d2 and d3, and their copies cO, cl, c2 and c3 are transmitted over a communications bus 32 to a decoder 34. During transmission, the transmitted data bits and their copies may become 'faulty', that is, the transmitted bit may be detected as a '1' instead of a '0', or vice versa.
• the data bits DO, Dl, D2 and D3 and the copies CO, Cl, C2 and C3 received at the decoder 34 may, or may not, be the same as the data bits dO, dl, d2 and d3 and copy bits cO, cl, c2, c3 transmitted by the encoder 22.
• a received data parity bit, Rparity is calculated for the data bits DO, Dl, D2 and D3 received from the communications bus 32 by parity tree 36, which is identical in structure to parity tree 24 in the encoder 22.
• a multiplexer control bit, sO is determined by comparing the received data parity bit, Rparity, with the transmitted data parity bit, Tparity, received over the communications bus 32.
• the comparison is performed by an exclusive OR gate 38.
• the multiplexer control bit sO is fed into a plurality of multiplexers MuxO, Muxl, Mux2 and Mux3 that act as correction circuits.
• Each multiplexer MuxO, Muxl, Mux2 and Mux3 receives a respective received data signal DO, Dl, D2 or D3 and a corresponding received copy of the data signal CO, Cl, C2 or C3.
• the multiplexer control bit sO controls whether each multiplexer outputs the received data signal or the received copy of the data signal.
• the multiplexer control bit, sO When the received data parity bit, Rparity, is the same as the transmitted data parity bit, Tparity, the multiplexer control bit, sO, is a '0', which instructs the multiplexers MuxO, Muxl, Mux2 and Mux3, to output the received data bits DO, Dl, D2 and D3.
• the received data parity bit, Rparity is different to the transmitted data parity bit, Tparity, the multiplexer control bit, sO, is a ' 1', which instructs the multiplexers MuxO, Muxl, Mux2 and Mux3, to output the received copies of the transmitted data bits CO, Cl, C2 and C3.
• a module for transmitting a plurality of data bits to another module via a communication bus comprising: means adapted to generate respective copies of the data bits; means adapted to invert the respective copies of the data bits; and means adapted to transmit, via the communication bus, the plurality of data bits and their respective inverted copies to the other module.
• the module has means for generating a first parity bit from the plurality of data bits, wherein the means adapted to transmit is further adapted to transmit, with the plurality of data bits and their respective inverted copies, the first parity bit to the other module.
• the means for generating a first parity bit comprises one or more logic gates.
• the module further comprises means adapted to generate an inverted copy of the first parity bit and wherein the means adapted to transmit is further adapted to transmit, with the plurality of data bits, their respective inverted copies and the first parity bit, the inverted copy of the first parity bit to the other module.
• a module for receiving a plurality of data bits from another module via a communication bus comprising: means adapted to receive the plurality of data bits and respective inverted copies of the data bits from the other module; means adapted to detect the presence of one or more errors in the received data bits; means adapted to select the received data bits as the output of the module in the event that the means adapted to detect the presence of one or more errors does not detect any errors, and to select the inverse of the respective received inverted copies of the data bits as the output of the module in the event that the means adapted to detect detects the presence of one or more errors.
• the means adapted to receive is further adapted to receive a first parity bit from the other module, and the module further comprises means for generating a second parity bit from the received data bits, and wherein the means adapted to detect the presence of one or more errors in the received data bits is adapted to compare the first and second parity bits.
• the means for generating a second parity bit comprises one or more logic gates.
• the means adapted to detect the presence of one or more errors in the received data bits comprises a logic gate.
• the means adapted to select comprises one or more multiplexers, each multiplexer having a received data bit and the inverse of its respective received inverted copy as inputs, with each multiplexer being operable in response to a control signal output by the means adapted to detect.
• the means adapted to select comprises one or more multiplexers, each multiplexer having the inverse of a received data bit and its respective received inverted copy as inputs, with each multiplexer being operable in response to a control signal output by the means adapted to detect, and wherein the output of the module is the inverse of the output of each multiplexer.
• a system comprising a module adapted to transmit as described above, and a module adapted to receive as described above, the modules being connected via a communication bus.
• a method of reducing ground bounce in a system in which a plurality of data bits are to be transmitted from a first module to a second module via a communication bus; the system being able to detect errors in the received data bits; the method comprising: in the first module: generating respective copies of the data bits to be transmitted; inverting the respective copies of the data bits; and transmitting, via the communication bus, the plurality of data bits and their respective inverted copies to the second module.
• the number of lines carrying a high signal will be the same as the number of wires carrying a low signal (ensuring DC stability) and, when there is a bus transition, the number of transitions from a high signal to a low signal will be the same as the number of transitions from a low signal to a high signal (ensuring AC stability).
• the plurality of data bits and their respective inverted copies are received from the first module, the presence of one or more errors in the received data bits is determined, the received data bits are used as the output of the second module in the event that one or more errors are not detected in the received data bits, and the respective copies of the data bits are used as the output of the second module in the event that one or more errors are detected in the received data bits.
• a first parity bit is generated from the plurality of data bits to be transmitted and the first parity bit is transmitted to the second module with the plurality of data bits and their respective inverted copies.
• the first parity bit is received from the first module a second parity bit is generated from the received data bits and the step of detecting one or more errors in the received data bits comprises comparing the first and second parity bits.
• the first module an inverted copy of the first parity bit is generated and transmitted to the second module with the plurality of data bits, their respective inverted copies and the first parity bit.
• Figure 1 is a schematic illustration of a typical fault tolerant bus structure.
• Figure 2 shows a prior art dual-rail bus structure.
• Figure 3 shows a system using dual-rail encoding according to a first embodiment of the present invention.
• Figure 4 shows an alternative system using dual-rail encoding according to the first embodiment of the present invention.
• Figure 5 shows a system using dual-rail encoding according to a second embodiment of the present invention.
• Figure 6 is a flow chart illustrating a method of reducing ground bounce according to the invention.
• the problem of ground bounce in a structure that uses dual-rail encoding is reduced by increasing the AC and DC stability of the code used to transmit the data. That is, AC and DC stability is achieved when the number of lines transitioning from a high signal to a low signal is the same as the number of lines transitioning from a low signal to a high signal; and the number of lines carrying a high signal is the same as the number of lines carrying a low signal.
• Figure 3 shows a system using dual-rail encoding according to a first embodiment of the present invention. In the system 50, there are four input data rails carrying data bits dO, dl, d2 and d3.
• the output of the first module 52 is DC stable.
• the number of transitions from a high signal to a low signal will be the same as the number of transitions from a low signal to a high signal. Therefore, the output of the first module 52 is AC stable. Hence, the problem of ground bounce in the communication bus 54 caused by transitions on the data lines has been reduced.
• the data bits dO, dl , d2 and d3 and their respective inverted copies cO', cl', c2' and c3', forming the output of the first module 52, are transmitted to a second module 56 via the communication bus 54.
• the first and second modules 52, 56 may not be separate circuit components from the communication bus 54, but they may form a single integrated unit.
• the first module 52 may be the driver for the communication bus 54
• the second module 56 may be the receiver.
• the transmitted data bits and their respective inverted copies may become 'faulty', that is, the transmitted bit may be detected as a '1' instead of a '0', or vice versa.
• data bits DO, Dl, D2 and D3 and the respective inverted copies CO', Cl', C2' and C3' received at the second module 56 may, or may not, be the same as the data bits dO, dl, d2 and d3 and respective inverted copy bits cO', cl', c2', c3' transmitted by the first module 52.
• a parity bit, Tparity is calculated by the first module 52 and provided to the second module 56.
• This parity bit is calculated in the first module 52 for the data bits to be transmitted using parity tree 58, which, in this illustrated embodiment, comprises exclusive OR gates 60, 62 and 64. However, it will be appreciated that the parity tree 58 may comprise other combinations of logic gates.
• the first module 52 then transmits the transmitted data parity bit, Tparity, to the second module 56 along with data bits dO, dl, d2 and d3, and their respective inverted copies cO', cl', c2' and c3' via the communications bus 54.
• the second module 56 calculates a received data parity bit, Rparity, for the received data bits DO, Dl, D2 and D3.
• the received parity bit, Rparity is calculated using parity tree 66, which is identical in structure to parity tree 58 in the first module 52.
• the second module 56 then compares the received data parity bit, Rparity, with the transmitted data parity bit, Tparity, received over the communications bus 54.
• the comparison is performed by exclusive OR gate 68, although it will be appreciated that the comparison may be performed by other types of logic gates.
• the output of the exclusive OR gate 68 is a multiplexer control bit sO.
• the multiplexer control signal sO is fed into a plurality of dual-input multiplexers MuxO, Muxl, Mux2 and Mux3 that act as correction circuits for the second module 56.
• Each multiplexer, MuxO, Muxl, Mux2 and Mux3 receives a respective received data bit DO, Dl, D2 or D3 and a corresponding received inverted copy of the data bit CO,' Cl', C2' or C3'.
• the multiplexer control bit sO determines which of the signals input into the multiplexer is to be used as the output of the multiplexer. When the multiplexer control bit is low (i.e. a '0'), the output of the multiplexer will be the received data bit. However, when the multiplexer control bit is high (i.e. a ' 1'), the output of the multiplexer will be the received inverted copy of the associated data bit.
• each received data bit DO, Dl, D2 and D3 is inverted by respective inverters 700, 701, 702 and 703 before they are input into the respective multiplexers MuxO, Muxl , Mux2 and Mux3.
• FIG. 4 shows an alternative structure for inverting the received inverted copies of the data bits relative to the received data bits.
• each received inverted copy CO', Cl' , C2' and C3' is inverted by respective inverters 740, 741, 742 and 743 before they are input into the respective multiplexers MuxO, Muxl, Mux2 and Mux3.
• the multiplexer control bit sO is a '0', which instructs the multiplexers MuxO, Muxl, Mux2 and Mux3, to output the received data bits DO, Dl, D2 and D3.
• the multiplexer control signal sO is a T, which instructs the multiplexers MuxO, Muxl, Mux2 and Mux3, to output the received copies of the transmitted data bits CO, Cl, C2 and C3.
• the first module generates an inverted copy of the transmitted data parity bit, Tparity, and transmits this to the second module, along with the data bits, their respective inverted copies, and the transmitted data parity bit.
• a system in accordance with the second embodiment of the present invention is shown in Figure 5.
• features that are common to the first embodiment of the invention illustrated in Figures 3 and 4) are given the same reference numeral.
• the transmitted data parity bit, Tparity is copied, inverted (by inverter 76) and is transmitted across the communication bus 54 to the second module 56.
• FIG. 6 is a flow chart illustrating the method of reducing ground bounce according to the invention.
• step 1002 copies of data bits that are to be transmitted from a first module to a second module across a communication bus are generated.
• step 1004 the copies of the data bits are inverted, i.e. for a data bit having a value '0', the inverted copy will have a value '1'.
• step 1006 the copies of the data bits and the original data bits are transmitted via the communication bus to the second module. Therefore, the problem of ground bounce in a structure that uses dual-rail encoding is reduced as the AC and DC stability of the code used to transmit the data is increased.
• the second module receives, via the communication bus, the plurality of data bits and their respective inverted copies from the first module and detects the presence of one or more errors in the received data bits. If no errors are detected in the received data bits, the received data bits are used as the output of the second module. However, if one or more errors are detected in the received data bits, the respective copies of the data bits are used as the output of the second module.
• a first parity bit may be generated from the plurality of data bits to be transmitted, and the first parity bit is transmitted to the second module with the plurality of data bits and their respective inverted copies. At the second module, the first parity bit is received. The second module then generates a second parity bit from the received data bits.
• This second parity bit can then be compared with the received first parity bit to determine whether there are one or more errors in the received data bits.
• an inverted copy of the first parity bit can be generated in the first module.
• This inverted copy of the first parity bit can be transmitted to the second module with the plurality of data bits, their respective inverted copies and the first parity bit.

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• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Computer Hardware Design (AREA)
• Detection And Correction Of Errors (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

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• 2005
  • 2005-02-23 EP EP05703029A patent/EP1735711A1/en not_active Ceased
  • 2005-02-23 WO PCT/IB2005/050656 patent/WO2005088465A1/en not_active Application Discontinuation
  • 2005-02-23 KR KR1020067017739A patent/KR20070006765A/ko not_active Application Discontinuation
  • 2005-02-23 JP JP2007501398A patent/JP2007527066A/ja active Pending
  • 2005-02-23 CN CNA2005800066864A patent/CN1926526A/zh active Pending

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