Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/08—Clock generators with changeable or programmable clock frequency
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/06—Clock generators producing several clock signals

Definitions

• This invention relates to a programmable up/down clock generator, a method for manufacturing same, a method of programmable clock signal generation, and a clock signal generated by such method.
• a programmable up/down clock generator a method for manufacturing same, a method of programmable clock signal generation, and a clock signal generated by such method.
• it may be required to change the frequency of the operative clock signal in an integrated circuit, for power or performance management.
• many semiconductor devices are provided with an active and a standby mode of operation. Power consumption in the standby mode is reduced with respect to that in the active mode to increase efficiency during periods of time in which the device is powered up but idle.
• One method to reduce power consumption in the standby mode is to reduce the frequency of operation of various circuits that must continuously operate while the device is powered up.
• an electronic device for generating a clock signal for an integrated circuit comprising means for generating a first output clock signal at a first frequency, means for delaying said first output clock signal by means of a variable control signal, said variable control signal being synchronized to a local clock signal, and means for generating a second output clock signal at a second frequency defined by said variable control signal.
• the present invention extends to a method of manufacturing an electronic device as defined above, and a clock signal generated by means of the electronic device as defined above.
• a method of generating a clock signal for an integrated circuit comprising generating a first output clock signal at a first frequency, delaying said first output clock signal by means of a variable control signal, synchronizing said variable control signal to a local clock signal, and generating a second output clock signal at a second frequency defined by said variable control signal.
• the electronic device may be arranged to switch between at least two frequencies, and the means for delaying the first output clock signal may comprise a two- or multiple- way delay element, such as a D-type flip-flop or the like.
• the delay element preferably has as its inputs the variable control signal and the local clock signal.
• the outputs of the delay element may be fed as drive signals to a multiplexer or the like, located between the input and the output of the device.
• the present invention may extend to apparatus for generating a clock signal, comprising a plurality of electronic devices, as defined above.
• the electronic devices may be cascaded in a loop, each device having a respective variable control signal and output, wherein the frequency of the clock signal generated by the oscillator can be varied by varying the output of the respective electronic device.
• the oscillator may further comprise an up/down FIFO or the like, for receiving a signal defining a required change in frequency of the output clock signal, and for changing the output of an electronic device accordingly, so as to effect the desired change in output clock signal frequency.
• Fig. 1 is a schematic circuit diagram of a two-way delay element for use in clock generation apparatus according to an exemplary embodiment of the present invention
• Fig. 2 is a schematic circuit diagram of the element of Fig. 1, with the D-type flip-flop omitted for clarity
• Fig. 3 is a schematic block diagram illustrating the topology of an oscillator according to an exemplary embodiment of the present invention
• Fig. 4 is a schematic circuit diagram of an oscillator according to an exemplary embodiment of the present invention
• Fig. 5 is a graphical illustration of clock waveforms obtainable using apparatus according to an exemplary embodiment of the present invention.
• the clock enabling circuit is intended to generate an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock.
• US Patent No. 6,275,546 relates generally to a switching circuit for switching between two separate, generally free-running input clock signals that may be of the same or different frequency and phase, so as to produce a glitch-free output clock signal that is synchronized to one of the input clock signals.
• 2003/0074595 Al describes a circuit including a dynamically alterable output clock value generated from an input clock value, and a sample cycle output that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
• the circuit provides a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously.
• the present invention is intended to provide a mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change). Referring to Fig.
• a programmable up/down clock generator according to an exemplary embodiment of the present invention, comprises a synchronized dual-way element which is most preferably constructed as a single cell. It will be appreciated that the circuital implementation of the present invention may vary, although the basic function thereof will not.
• the element comprises a multiplexer 10 having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer 10 via a set of generic combinatorial delay elements 12, and the multiplexer output is fed to the output (Out) via an inverter 14.
• the element further comprises a D-type flip-flop 16 having as its "D" input a programming signal (Fk).
• a D-type flip-flop is a digital logic device that stores the status of its "D” input whenever its clock input (CP) makes a certain transition (i.e. low to high or high to low), and the output(s) "Q” show the currently stored value.
• two outputs "Q” and “Qn” from the D-type flip-flop provide respective drive signals to the multiplexer 10, and the delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal Fk. This signal is synchronized on the rising edge of the local clock (sync_ck). It is this latter aspect which enables the circuit to achieve the object of the present invention. Referring to Fig.
• the exemplary element of Fig. 1 is illustrated with the synch rising flip-flop 16 omitted, so as to more clearly illustrate the overall operation of the circuit.
• the basic operation of a circuit according to the present invention is that the output signal (Out) of the clock generator is delayed using a variable control signal Fk which is synchronized to a local clock using, for example, the D-type flip-flop 16 included in the circuit of Fig. 1.
• an oscillator can be created by cascading a plurality of such elements 20 in a loop, each having a respective control signal F.
• a drive circuit for the oscillator illustrated in Fig. 3 is shown schematically in Fig.
• the drive circuit comprises an up/down FIFO 22, and the frequency of the oscillator can be changed by changing the values on the Rl - R9 signals.
• the patterns on the Rl - R9 signals must be such that only one delay element 24 is re-programmed at a time. This can be accomplished using the up/down FIFO 22, which enables passing from pattern 0000001 to 1111111 (and vice versa) by simple logical shifting. In the case of this exemplary embodiment, shift left increases the frequency of the oscillator ("up" signal) and shift right decreases the frequency ("down" signal).
• the present invention provides a mechanism to generate a clock signal for an integrated circuit, or a part thereof, which enables the frequency to be safely changed substantially continuously (i.e. with a gradual frequency change), without any spurious transitions.
• the present invention does not require the use of an external oscillator, and is compatible with standard structural testing solutions, for example, scan chains. Apparatus according to the present invention finds application in, among other things, systems where frequency is changed for power or performance management, as discussed above.
• a two-way delay element is configured using the D-type flip-flop 16.
• multiple-way delay elements may be employed.
• the topology of the oscillator may be different to that illustrated in Fig. 3 of the drawings, as will be appreciated by a person skilled in the art.
• the synchronized interface required for the invention to work may be realized in a different manner to that of the illustrated embodiment, and various designs for the up/down FIFO in the circuit of Fig. 4 are envisaged.
• any reference signs placed between parentheses shall not be construed as limiting the claim.
• the term "comprising” does not exclude the presence of elements or steps other than those listed in a claim.
• the terms "a” or " an” does not exclude a plurality.
• the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
• the mere fact that measures are recited in mutually different independent claims does not indicate that a combination of these measures cannot be used to advantage.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Pulse Circuits (AREA)
• Manipulation Of Pulses (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 2005
  • 2005-02-28 EP EP05708859A patent/EP1728139A2/en not_active Ceased
  • 2005-02-28 CN CNB2005800066366A patent/CN100422901C/zh not_active Expired - Fee Related
  • 2005-02-28 JP JP2007501424A patent/JP2007526575A/ja active Pending
  • 2005-02-28 WO PCT/IB2005/050713 patent/WO2005088421A2/en not_active Application Discontinuation

Non-Patent Citations (1)

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