EP1728139A2 - Generation d'horloge programmable - Google Patents

Generation d'horloge programmable

Info

Publication number
EP1728139A2
EP1728139A2 EP05708859A EP05708859A EP1728139A2 EP 1728139 A2 EP1728139 A2 EP 1728139A2 EP 05708859 A EP05708859 A EP 05708859A EP 05708859 A EP05708859 A EP 05708859A EP 1728139 A2 EP1728139 A2 EP 1728139A2
Authority
EP
European Patent Office
Prior art keywords
clock signal
output
frequency
signal
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05708859A
Other languages
German (de)
English (en)
Inventor
Francesco Pessolano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP05708859A priority Critical patent/EP1728139A2/fr
Publication of EP1728139A2 publication Critical patent/EP1728139A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Definitions

  • This invention relates to a programmable up/down clock generator, a method for manufacturing same, a method of programmable clock signal generation, and a clock signal generated by such method.
  • a programmable up/down clock generator a method for manufacturing same, a method of programmable clock signal generation, and a clock signal generated by such method.
  • it may be required to change the frequency of the operative clock signal in an integrated circuit, for power or performance management.
  • many semiconductor devices are provided with an active and a standby mode of operation. Power consumption in the standby mode is reduced with respect to that in the active mode to increase efficiency during periods of time in which the device is powered up but idle.
  • One method to reduce power consumption in the standby mode is to reduce the frequency of operation of various circuits that must continuously operate while the device is powered up.
  • an electronic device for generating a clock signal for an integrated circuit comprising means for generating a first output clock signal at a first frequency, means for delaying said first output clock signal by means of a variable control signal, said variable control signal being synchronized to a local clock signal, and means for generating a second output clock signal at a second frequency defined by said variable control signal.
  • the present invention extends to a method of manufacturing an electronic device as defined above, and a clock signal generated by means of the electronic device as defined above.
  • a method of generating a clock signal for an integrated circuit comprising generating a first output clock signal at a first frequency, delaying said first output clock signal by means of a variable control signal, synchronizing said variable control signal to a local clock signal, and generating a second output clock signal at a second frequency defined by said variable control signal.
  • the electronic device may be arranged to switch between at least two frequencies, and the means for delaying the first output clock signal may comprise a two- or multiple- way delay element, such as a D-type flip-flop or the like.
  • the delay element preferably has as its inputs the variable control signal and the local clock signal.
  • the outputs of the delay element may be fed as drive signals to a multiplexer or the like, located between the input and the output of the device.
  • the present invention may extend to apparatus for generating a clock signal, comprising a plurality of electronic devices, as defined above.
  • the electronic devices may be cascaded in a loop, each device having a respective variable control signal and output, wherein the frequency of the clock signal generated by the oscillator can be varied by varying the output of the respective electronic device.
  • the oscillator may further comprise an up/down FIFO or the like, for receiving a signal defining a required change in frequency of the output clock signal, and for changing the output of an electronic device accordingly, so as to effect the desired change in output clock signal frequency.
  • Fig. 1 is a schematic circuit diagram of a two-way delay element for use in clock generation apparatus according to an exemplary embodiment of the present invention
  • Fig. 2 is a schematic circuit diagram of the element of Fig. 1, with the D-type flip-flop omitted for clarity
  • Fig. 3 is a schematic block diagram illustrating the topology of an oscillator according to an exemplary embodiment of the present invention
  • Fig. 4 is a schematic circuit diagram of an oscillator according to an exemplary embodiment of the present invention
  • Fig. 5 is a graphical illustration of clock waveforms obtainable using apparatus according to an exemplary embodiment of the present invention.
  • the clock enabling circuit is intended to generate an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock.
  • US Patent No. 6,275,546 relates generally to a switching circuit for switching between two separate, generally free-running input clock signals that may be of the same or different frequency and phase, so as to produce a glitch-free output clock signal that is synchronized to one of the input clock signals.
  • 2003/0074595 Al describes a circuit including a dynamically alterable output clock value generated from an input clock value, and a sample cycle output that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
  • the circuit provides a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously.
  • the present invention is intended to provide a mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change). Referring to Fig.
  • a programmable up/down clock generator according to an exemplary embodiment of the present invention, comprises a synchronized dual-way element which is most preferably constructed as a single cell. It will be appreciated that the circuital implementation of the present invention may vary, although the basic function thereof will not.
  • the element comprises a multiplexer 10 having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer 10 via a set of generic combinatorial delay elements 12, and the multiplexer output is fed to the output (Out) via an inverter 14.
  • the element further comprises a D-type flip-flop 16 having as its "D" input a programming signal (Fk).
  • a D-type flip-flop is a digital logic device that stores the status of its "D” input whenever its clock input (CP) makes a certain transition (i.e. low to high or high to low), and the output(s) "Q” show the currently stored value.
  • two outputs "Q” and “Qn” from the D-type flip-flop provide respective drive signals to the multiplexer 10, and the delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal Fk. This signal is synchronized on the rising edge of the local clock (sync_ck). It is this latter aspect which enables the circuit to achieve the object of the present invention. Referring to Fig.
  • the exemplary element of Fig. 1 is illustrated with the synch rising flip-flop 16 omitted, so as to more clearly illustrate the overall operation of the circuit.
  • the basic operation of a circuit according to the present invention is that the output signal (Out) of the clock generator is delayed using a variable control signal Fk which is synchronized to a local clock using, for example, the D-type flip-flop 16 included in the circuit of Fig. 1.
  • an oscillator can be created by cascading a plurality of such elements 20 in a loop, each having a respective control signal F.
  • a drive circuit for the oscillator illustrated in Fig. 3 is shown schematically in Fig.
  • the drive circuit comprises an up/down FIFO 22, and the frequency of the oscillator can be changed by changing the values on the Rl - R9 signals.
  • the patterns on the Rl - R9 signals must be such that only one delay element 24 is re-programmed at a time. This can be accomplished using the up/down FIFO 22, which enables passing from pattern 0000001 to 1111111 (and vice versa) by simple logical shifting. In the case of this exemplary embodiment, shift left increases the frequency of the oscillator ("up" signal) and shift right decreases the frequency ("down" signal).
  • the present invention provides a mechanism to generate a clock signal for an integrated circuit, or a part thereof, which enables the frequency to be safely changed substantially continuously (i.e. with a gradual frequency change), without any spurious transitions.
  • the present invention does not require the use of an external oscillator, and is compatible with standard structural testing solutions, for example, scan chains. Apparatus according to the present invention finds application in, among other things, systems where frequency is changed for power or performance management, as discussed above.
  • a two-way delay element is configured using the D-type flip-flop 16.
  • multiple-way delay elements may be employed.
  • the topology of the oscillator may be different to that illustrated in Fig. 3 of the drawings, as will be appreciated by a person skilled in the art.
  • the synchronized interface required for the invention to work may be realized in a different manner to that of the illustrated embodiment, and various designs for the up/down FIFO in the circuit of Fig. 4 are envisaged.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the term "comprising” does not exclude the presence of elements or steps other than those listed in a claim.
  • the terms "a” or " an” does not exclude a plurality.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the mere fact that measures are recited in mutually different independent claims does not indicate that a combination of these measures cannot be used to advantage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

La présente invention se rapporte à un mécanisme destiné à générer un signal d'horloge pour un circuit intégré ou une partie d'un tel circuit, de façon que sa fréquence puisse en toute sécurité être modifiée en continu (c'est-à-dire avec une modification de fréquence progressive) sans que des signaux parasites ou déformés ne soient générés sur la ligne de sortie d'horloge. Dans un mode de réalisation exemplaire, l'invention a également trait à un dispositif électronique qui comprend un multiplexeur (10) possédant deux signaux d'entrée, le second étant une version différée du premier, qui sont générés par la fourniture de l'entrée au multiplexeur (10) par l'intermédiaire d'un ensemble de circuits à retard combinatoires génériques (12), et par la fourniture de la sortie du multiplexeur à la sortie (Sortie) par l'intermédiaire d'un inverseur (14). Ledit élément comprend également une bascule bistable de type D (16), dont l'entrée « D » est un signal de programmation (Fk), et les deux sorties « Q » et « Qn » fournissent des signaux d'entraînement respectifs au multiplexeur (10). Le retard du signal de sortie (Sortie) par rapport au signal d'entrée (Entrée) dépend de la valeur du signal de programmation (Fk), lequel est synchronisé sur le front montant de l'horloge locale (sync_ck).
EP05708859A 2004-03-04 2005-02-28 Generation d'horloge programmable Ceased EP1728139A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05708859A EP1728139A2 (fr) 2004-03-04 2005-02-28 Generation d'horloge programmable

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP04100876 2004-03-04
EP05708859A EP1728139A2 (fr) 2004-03-04 2005-02-28 Generation d'horloge programmable
PCT/IB2005/050713 WO2005088421A2 (fr) 2004-03-04 2005-02-28 Generation d'horloge programmable

Publications (1)

Publication Number Publication Date
EP1728139A2 true EP1728139A2 (fr) 2006-12-06

Family

ID=34960643

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05708859A Ceased EP1728139A2 (fr) 2004-03-04 2005-02-28 Generation d'horloge programmable

Country Status (4)

Country Link
EP (1) EP1728139A2 (fr)
JP (1) JP2007526575A (fr)
CN (1) CN100422901C (fr)
WO (1) WO2005088421A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104038183B (zh) * 2014-05-28 2017-01-18 钢研纳克检测技术有限公司 用于生成光谱探测系统的多路触发信号的设备及方法
US9660799B1 (en) * 2015-11-24 2017-05-23 Intel Corporation Changing the clock frequency of a computing device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4191998A (en) * 1978-03-29 1980-03-04 Honeywell Inc. Variable symmetry multiphase clock generator
US4316148A (en) * 1979-09-04 1982-02-16 Sperry Corporation Variable frequency logic clock
JPH06502264A (ja) * 1990-10-12 1994-03-10 インテル・コーポレーション 動的に切替え自在な多周波数クロック発生器
US5977805A (en) * 1998-01-21 1999-11-02 Atmel Corporation Frequency synthesis circuit tuned by digital words
US6654900B1 (en) * 2000-04-19 2003-11-25 Sigmatel, Inc. Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements
JP3450293B2 (ja) * 2000-11-29 2003-09-22 Ｎｅｃエレクトロニクス株式会社 クロック制御回路及びクロック制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
JP2007526575A (ja) 2007-09-13
CN100422901C (zh) 2008-10-01
CN1926494A (zh) 2007-03-07
WO2005088421A3 (fr) 2006-03-16
WO2005088421A2 (fr) 2005-09-22

Similar Documents

Publication Publication Date Title
US6600345B1 (en) Glitch free clock select switch
US5790609A (en) Apparatus for cleanly switching between various clock sources in a data processing system
EP0840195B1 (fr) Dispositif et méthode pour séquencer les horloges dans un système de traitement de données
US5315181A (en) Circuit for synchronous, glitch-free clock switching
US6563349B2 (en) Multiplexor generating a glitch free output when selecting from multiple clock signals
JP5317356B2 (ja) クロック制御信号生成回路、クロックセレクタ、及び情報処理装置
US8299827B2 (en) High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider
US6784699B2 (en) Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
US20080046773A1 (en) Systems and Methods for Dynamic Clock Frequencies for Low Power Design
US9143164B2 (en) Scalable serializer
KR100487654B1 (ko) 저전력 플립플롭 회로
US20110309865A1 (en) Parallel synchronizing cell with improved mean time between failures
US20050140398A1 (en) Clock switching circuit
US6801074B2 (en) Clock switching circuit
US7003683B2 (en) Glitchless clock selection circuit
EP1728139A2 (fr) Generation d'horloge programmable
KR20050099714A (ko) 고집적 저전력 글리치리스 클럭 선택회로 및 이를구비하는 디지털 프로세싱 시스템
US6249157B1 (en) Synchronous frequency dividing circuit
US7049864B2 (en) Apparatus and method for high frequency state machine divider with low power consumption
JP3542351B2 (ja) クロック切り替え回路
US6075398A (en) Tunable digital oscillator circuit and method for producing clock signals of different frequencies
JP2003188719A (ja) 分周回路
US7253673B2 (en) Multi-phase clock generator and generating method for network controller
CN113504809A (zh) 一种多路时钟的动态切换方法、装置及系统
CN113904661A (zh) 一种控制电路、控制方法、时钟触发器件和相关设备

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20061004

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NXP B.V.

17Q First examination report despatched

Effective date: 20090303

R17C First examination report despatched (corrected)

Effective date: 20090903

REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20180407