WO2005088421A3 - Programmable clock generation - Google Patents

Programmable clock generation Download PDF

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Publication number
WO2005088421A3
WO2005088421A3 PCT/IB2005/050713 IB2005050713W WO2005088421A3 WO 2005088421 A3 WO2005088421 A3 WO 2005088421A3 IB 2005050713 W IB2005050713 W IB 2005050713W WO 2005088421 A3 WO2005088421 A3 WO 2005088421A3
Authority
WO
WIPO (PCT)
Prior art keywords
multiplexer
input
signal
output
clock
Prior art date
Application number
PCT/IB2005/050713
Other languages
French (fr)
Other versions
WO2005088421A2 (en
Inventor
Francesco Pessolano
Original Assignee
Koninkl Philips Electronics Nv
Francesco Pessolano
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Francesco Pessolano filed Critical Koninkl Philips Electronics Nv
Priority to EP05708859A priority Critical patent/EP1728139A2/en
Priority to JP2007501424A priority patent/JP2007526575A/en
Publication of WO2005088421A2 publication Critical patent/WO2005088421A2/en
Publication of WO2005088421A3 publication Critical patent/WO2005088421A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Abstract

A mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change) without spurious signals or glitches being created on the clock output line. A electronic device according to an exemplary embodiment, comprises a multiplexer (10) having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer (10) via a set of generic combinatorial delay elements (12) and the multiplexer output id fed to the output (Out) via an inverter (14). The element further comprises a D-type flip-flop (16) having as its 'D' input a programming signal (Fk), and the two outputs 'Q' and 'Qn' from the D-type flip-flop provided respective drive signals to the multiplexer (10). The delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal (Fk), which is synchronized on the rising edge of the local clock (sync_ck).
PCT/IB2005/050713 2004-03-04 2005-02-28 Programmable clock generation WO2005088421A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05708859A EP1728139A2 (en) 2004-03-04 2005-02-28 Programmable clock generation
JP2007501424A JP2007526575A (en) 2004-03-04 2005-02-28 Programmable clock generation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100876.4 2004-03-04
EP04100876 2004-03-04

Publications (2)

Publication Number Publication Date
WO2005088421A2 WO2005088421A2 (en) 2005-09-22
WO2005088421A3 true WO2005088421A3 (en) 2006-03-16

Family

ID=34960643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/050713 WO2005088421A2 (en) 2004-03-04 2005-02-28 Programmable clock generation

Country Status (4)

Country Link
EP (1) EP1728139A2 (en)
JP (1) JP2007526575A (en)
CN (1) CN100422901C (en)
WO (1) WO2005088421A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104038183B (en) * 2014-05-28 2017-01-18 钢研纳克检测技术有限公司 Device and method for generating multiple paths of trigger signals of spectrum detection system
US9660799B1 (en) * 2015-11-24 2017-05-23 Intel Corporation Changing the clock frequency of a computing device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4191998A (en) * 1978-03-29 1980-03-04 Honeywell Inc. Variable symmetry multiphase clock generator
US4316148A (en) * 1979-09-04 1982-02-16 Sperry Corporation Variable frequency logic clock
US5481697A (en) * 1990-10-12 1996-01-02 Intel Corporation An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies
US20020070783A1 (en) * 2000-11-29 2002-06-13 Nec Corporation Clock control circuit and method
US6654900B1 (en) * 2000-04-19 2003-11-25 Sigmatel, Inc. Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977805A (en) * 1998-01-21 1999-11-02 Atmel Corporation Frequency synthesis circuit tuned by digital words

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4191998A (en) * 1978-03-29 1980-03-04 Honeywell Inc. Variable symmetry multiphase clock generator
US4316148A (en) * 1979-09-04 1982-02-16 Sperry Corporation Variable frequency logic clock
US5481697A (en) * 1990-10-12 1996-01-02 Intel Corporation An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies
US6654900B1 (en) * 2000-04-19 2003-11-25 Sigmatel, Inc. Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements
US20020070783A1 (en) * 2000-11-29 2002-06-13 Nec Corporation Clock control circuit and method

Also Published As

Publication number Publication date
WO2005088421A2 (en) 2005-09-22
JP2007526575A (en) 2007-09-13
CN1926494A (en) 2007-03-07
CN100422901C (en) 2008-10-01
EP1728139A2 (en) 2006-12-06

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