WO2005088421A2

WO2005088421A2 - Programmable clock generation

Info

Publication number: WO2005088421A2
Application number: PCT/IB2005/050713
Authority: WO
Inventors: Francesco Pessolano
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-03-04
Filing date: 2005-02-28
Publication date: 2005-09-22
Also published as: CN1926494A; CN100422901C; JP2007526575A; WO2005088421A3; EP1728139A2

Abstract

A mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change) without spurious signals or glitches being created on the clock output line. A electronic device according to an exemplary embodiment, comprises a multiplexer (10) having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer (10) via a set of generic combinatorial delay elements (12) and the multiplexer output id fed to the output (Out) via an inverter (14). The element further comprises a D-type flip-flop (16) having as its 'D' input a programming signal (Fk), and the two outputs 'Q' and 'Qn' from the D-type flip-flop provided respective drive signals to the multiplexer (10). The delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal (Fk), which is synchronized on the rising edge of the local clock (sync&lowbar;ck).

Description

Programmable clock generation

This invention relates to a programmable up/down clock generator, a method for manufacturing same, a method of programmable clock signal generation, and a clock signal generated by such method. There are many circumstances in which it may be required to change the frequency of the operative clock signal in an integrated circuit, for power or performance management. For example, many semiconductor devices are provided with an active and a standby mode of operation. Power consumption in the standby mode is reduced with respect to that in the active mode to increase efficiency during periods of time in which the device is powered up but idle. One method to reduce power consumption in the standby mode is to reduce the frequency of operation of various circuits that must continuously operate while the device is powered up. This may be achieved by providing dual oscillator frequencies: a higher frequency to drive the circuits at full speed during operation in the active mode, and a lower frequency to drive the circuits at a lower speed, thereby reducing the power consumed by the circuits during operation in the standby mode. Similarly, the demand for ever higher performance from computers generally, and microprocessors and microcontrollers in particular, has led to various enhancements, including higher clock rates and simpler instruction sets. Consequently, the control and flexibility of clock speeds and rates for all integrated circuits has become critical. We have now devised an improved arrangement, and it is an object of the present invention to provide a method and apparatus for generating a clock signal for an integrated circuit, or a part thereof, such that the frequency thereof can be changed substantially continuously (i.e. with a gradual frequency change, while maintaining continuity in the clock signal as it changes between the different frequencies), without any spurious signals or glitches being created on the clock output line. In accordance with the present invention, there is provided an electronic device for generating a clock signal for an integrated circuit, the device comprising means for generating a first output clock signal at a first frequency, means for delaying said first output clock signal by means of a variable control signal, said variable control signal being synchronized to a local clock signal, and means for generating a second output clock signal at a second frequency defined by said variable control signal. The present invention extends to a method of manufacturing an electronic device as defined above, and a clock signal generated by means of the electronic device as defined above. Also in accordance with the present invention, there is provided a method of generating a clock signal for an integrated circuit, the method comprising generating a first output clock signal at a first frequency, delaying said first output clock signal by means of a variable control signal, synchronizing said variable control signal to a local clock signal, and generating a second output clock signal at a second frequency defined by said variable control signal. The electronic device may be arranged to switch between at least two frequencies, and the means for delaying the first output clock signal may comprise a two- or multiple- way delay element, such as a D-type flip-flop or the like. The delay element preferably has as its inputs the variable control signal and the local clock signal. The outputs of the delay element may be fed as drive signals to a multiplexer or the like, located between the input and the output of the device. The present invention may extend to apparatus for generating a clock signal, comprising a plurality of electronic devices, as defined above. The electronic devices may be cascaded in a loop, each device having a respective variable control signal and output, wherein the frequency of the clock signal generated by the oscillator can be varied by varying the output of the respective electronic device. The oscillator may further comprise an up/down FIFO or the like, for receiving a signal defining a required change in frequency of the output clock signal, and for changing the output of an electronic device accordingly, so as to effect the desired change in output clock signal frequency. These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiment described herein.

An embodiment of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which: Fig. 1 is a schematic circuit diagram of a two-way delay element for use in clock generation apparatus according to an exemplary embodiment of the present invention; Fig. 2 is a schematic circuit diagram of the element of Fig. 1, with the D-type flip-flop omitted for clarity; Fig. 3 is a schematic block diagram illustrating the topology of an oscillator according to an exemplary embodiment of the present invention; Fig. 4 is a schematic circuit diagram of an oscillator according to an exemplary embodiment of the present invention; and Fig. 5 is a graphical illustration of clock waveforms obtainable using apparatus according to an exemplary embodiment of the present invention.

In known arrangements, clock generation normally requires a reference clock, which can then be used to produce clock signals having frequencies which are multiples of the reference clock frequency. However, a major disadvantage of these known arrangements is that only multiples of the reference clock frequency are available, and standard solutions tend to introduce glitches on the clock line. US Patent No. 5,808,486 describes a clock enabling circuit which generates an output clock signal having the same frequency, same duty cycle and a fixed phase relationship to an input clock signal when an enable signal is present. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The clock enabling circuit is intended to generate an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. US Patent No. 6,275,546 relates generally to a switching circuit for switching between two separate, generally free-running input clock signals that may be of the same or different frequency and phase, so as to produce a glitch-free output clock signal that is synchronized to one of the input clock signals. US Patent Application Publication No. 2003/0074595 Al describes a circuit including a dynamically alterable output clock value generated from an input clock value, and a sample cycle output that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer. The circuit provides a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. As stated above, the present invention is intended to provide a mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change). Referring to Fig. 1 of the drawings, a programmable up/down clock generator according to an exemplary embodiment of the present invention, comprises a synchronized dual-way element which is most preferably constructed as a single cell. It will be appreciated that the circuital implementation of the present invention may vary, although the basic function thereof will not. In the illustrated example, the element comprises a multiplexer 10 having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer 10 via a set of generic combinatorial delay elements 12, and the multiplexer output is fed to the output (Out) via an inverter 14. The element further comprises a D-type flip-flop 16 having as its "D" input a programming signal (Fk). In general, a D-type flip-flop is a digital logic device that stores the status of its "D" input whenever its clock input (CP) makes a certain transition (i.e. low to high or high to low), and the output(s) "Q" show the currently stored value. In the case of this exemplary embodiment of the invention, two outputs "Q" and "Qn" from the D-type flip-flop provide respective drive signals to the multiplexer 10, and the delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal Fk. This signal is synchronized on the rising edge of the local clock (sync_ck). It is this latter aspect which enables the circuit to achieve the object of the present invention. Referring to Fig. 2 of the drawings, the exemplary element of Fig. 1 is illustrated with the synch rising flip-flop 16 omitted, so as to more clearly illustrate the overall operation of the circuit. Thus, as will be apparent to a person skilled in the art, the basic operation of a circuit according to the present invention is that the output signal (Out) of the clock generator is delayed using a variable control signal Fk which is synchronized to a local clock using, for example, the D-type flip-flop 16 included in the circuit of Fig. 1. Referring to Fig. 3 of the drawings, an oscillator can be created by cascading a plurality of such elements 20 in a loop, each having a respective control signal F. A drive circuit for the oscillator illustrated in Fig. 3 is shown schematically in Fig. 4 of the drawings. The drive circuit comprises an up/down FIFO 22, and the frequency of the oscillator can be changed by changing the values on the Rl - R9 signals. In order to change the frequency of the oscillator, the patterns on the Rl - R9 signals must be such that only one delay element 24 is re-programmed at a time. This can be accomplished using the up/down FIFO 22, which enables passing from pattern 0000001 to 1111111 (and vice versa) by simple logical shifting. In the case of this exemplary embodiment, shift left increases the frequency of the oscillator ("up" signal) and shift right decreases the frequency ("down" signal). In order to ensure correct operation and avoid problems, it is necessary to synchronizes the above-mentioned pattern with the generated clock signal (CK) using, for example, D-type flip-flops 26, of which only one is illustrated in Fig. 4. It is for this reason that the flip-flop 16 in the circuit of Fig. 1 is necessary, which flip-flop must be located in close proximity to its respective delay element to avoid races. The presence of this flip-flop (or its equivalent) is implied in the circuit of Fig. 2, and when using the circuit of Fig. 1, this circuit should be included in the delay element of the oscillator loop. The apparatus of the present invention allows the clock frequency to be continuously changed without any spurious transition, and exemplary waveforms are illustrated in Fig. 5 of the drawings, illustrating tests performed in respect of changing clock frequencies from 2GHz to around 100MHz. Control of the frequency of the generated clock is relatively very simple, as no clock work as such is required. On the contrary, the desired control is achieved using only two signals, "up" and "down". Thus, the present invention provides a mechanism to generate a clock signal for an integrated circuit, or a part thereof, which enables the frequency to be safely changed substantially continuously (i.e. with a gradual frequency change), without any spurious transitions. The present invention does not require the use of an external oscillator, and is compatible with standard structural testing solutions, for example, scan chains. Apparatus according to the present invention finds application in, among other things, systems where frequency is changed for power or performance management, as discussed above. An embodiment of the present invention has been described above by way of example only, and it will be apparent to a person skilled in the art that modifications and variations can be made to the described embodiments without departing from the scope of the invention as defined by the appended claims. For example, in the exemplary embodiment illustrated in, and described with reference to, Fig. 1, a two-way delay element is configured using the D-type flip-flop 16. However, in alternative embodiments, multiple-way delay elements may be employed. The topology of the oscillator may be different to that illustrated in Fig. 3 of the drawings, as will be appreciated by a person skilled in the art. The synchronized interface required for the invention to work may be realized in a different manner to that of the illustrated embodiment, and various designs for the up/down FIFO in the circuit of Fig. 4 are envisaged. Further, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The term "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The terms "a" or " an" does not exclude a plurality. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that measures are recited in mutually different independent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An electronic device for generating a clock signal (out) for an integrated circuit, the device comprising means for generating a first output clock signal (out) at a first frequency, means (16) for delaying said first output clock signal by means of a variable control signal (Fk), said variable control signal (Fk) being synchronized to a local clock signal (sync_ck), and means for generating a second output clock signal (out) at a second frequency defined by said variable control signal (Fk).

2. An electronic device according to claim 1, arranged to switch between at least two frequencies

3. An electronic device according to claim 1 or claim 2, wherein the means (16) for delaying the first output clock signal comprises a two- or multiple- way delay element.

4. An electronic device according to claim 3, wherein said delay element comprises a D-type flip-flop (16).

5. An electronic device according to claim 3 or claim 4, wherein the delay element (16) has as its inputs the variable control signal (Fk) and the local clock signal (sync_ck).

6. An electronic device according to any one of claims 3 to 5, wherein the outputs (Q, Qn) of the delay element (16) are fed as drive signals (SO, SI) to a multiplexer (10) located between an input (In) and an output (Out) of the electronic device.

7. Apparatus for generating a clock signal, comprising a plurality of electronic devices (24) according to any one of claims 1 to 6.

8. Apparatus according to claim 7, wherein the electronic devices (24) are cascaded in a loop, each device (24) having a respective variable control signal (F1-F9) and output.

9. Apparatus according to claim 8, wherein the frequency of the clock signal generated by the apparatus can be varied by varying the output (R1-R9) of a respective electronic device (24).

10. Apparatus according to any one of claims 7 to 9, further comprising an up/down FIFO (22), for receiving a signal defining a required change in frequency of the output clock signal (out), and for changing the output (R1-R9) of an electronic device (24) accordingly, so as to effect the desired change in output clock signal frequency.

11. A method of generating a clock signal for an integrated circuit, the method comprising generating a first output clock signal (out) at a first frequency, delaying said first output clock signal by means of a variable control signal (Fk), synchronizing said variable control signal to a local clock signal (sync_ck), and generating a second output clock signal (out) at a second frequency defined by said variable control signal (Fk).

12. A method of manufacturing an electronic device according to any one of claims 1 to 6.

13. A method of manufacturing apparatus according to any one of claims 7 to 10.

14. A clock signal generated by an electronic device according to any one of claims 1 to 6, apparatus according to any one of claims 7 to 10, or by means of a method according to claim 11.