EP1681719A2 - Halbleiterelement mit geteilter Anschlußfläche - Google Patents

Halbleiterelement mit geteilter Anschlußfläche Download PDF

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Publication number
EP1681719A2
EP1681719A2 EP05077999A EP05077999A EP1681719A2 EP 1681719 A2 EP1681719 A2 EP 1681719A2 EP 05077999 A EP05077999 A EP 05077999A EP 05077999 A EP05077999 A EP 05077999A EP 1681719 A2 EP1681719 A2 EP 1681719A2
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EP
European Patent Office
Prior art keywords
gate
pad
gate pad
semiconductor device
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05077999A
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English (en)
French (fr)
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EP1681719A3 (de
Inventor
Robert J. Campbell
Monty B. Hayes
John R. Fruth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Delphi Technologies Inc
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Delphi Technologies Inc
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Publication date
Application filed by Delphi Technologies Inc filed Critical Delphi Technologies Inc
Publication of EP1681719A2 publication Critical patent/EP1681719A2/de
Publication of EP1681719A3 publication Critical patent/EP1681719A3/de
Withdrawn legal-status Critical Current

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Definitions

  • the present invention is generally directed to a semiconductor device and, more specifically, to a semiconductor device with a split pad design.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • IGBT insulated-gate bipolar-transistor
  • MOSFET metal-oxide semiconductor field-effect transistor
  • IGBT insulated-gate bipolar-transistor
  • MOSFET semiconductor device The remaining surface of a MOSFET semiconductor device is typically covered by another conductor, which contacts and interconnects the source region of all of the cells.
  • the cellular structure allows for the achievement of relatively low voltage drop across the power device, i.e., low drain-to-source resistance, when it is in the on-state and, thus, relatively low power dissipation for the power device.
  • the device 1A includes a substrate or device body 1, which includes a plurality of cells formed therein.
  • a conductive gate pad 2 is centrally located along one edge of the substrate 1 and is connected to a conductive gate signal ring 3 that extends along a periphery of the substrate 1. Extending from the ring 3 are a plurality of conductive gate signal fingers 4, which are utilized provide a gate signal to a gate region of each of the cells.
  • a conductive source plate 5 includes a central pad area 6 with source fingers 7 providing electrical connection to a source of each of the cells.
  • At least one such device has located a gate pad in a corner of the device.
  • a semiconductor device 10A with a gate pad 12 located at a corner of a device body 10 is shown.
  • the source metallization is not shown.
  • a gate signal ring 13 traverses the periphery of the device body 10 with an interconnected gate finger 14 traversing through a center of the device body 10 and connecting halves of the gate signal ring 13.
  • gate signal ring and fingers In general, designers have attempted to design gate signal ring and fingers to allow parallel cells within a semiconductor device to turn on and off with minimal propagation delay between the cells and to allow current to flow in a uniform manner across the power device.
  • the gate signal runners have been made of a variety of materials, e.g., metals, polysilicon or a combination of metal and polysilicon, and have had various configurations depending on the physical dimensions and operating frequency of the device. For devices operating at lower frequencies, a relatively simple gate structure that traverses the periphery of the device has generally been suitable. However, devices operating at higher frequencies have generally required additional gate fingers (see Fig. 1) to allow for uniform propagation of the gate signal from a gate pad of the device to all of the parallel cells.
  • Gate pads have usually been centered along one of the edges of the semiconductor device or located at a center of the device. In a typical semiconductor device that implements wire bonding, the gate pad provides an interconnect point between the cells of the device and an external lead or device.
  • MOSFET (IGBT) devices are interconnected to external circuitry by soldering the drain (collector) and wire bonding the gate and source (gate and emitter) to other interconnects.
  • Other solderable MOSFET devices such as flip-chip devices, have been configured to allow for drain, source and gate interconnects to be achieved with a solder connection.
  • IGBT devices have been constructed such that collector, gate and emitter connections are made through a solder connection.
  • leakage current tests, gate stress tests, avalanche tests and energy tests of the semiconductor device may be adversely affected, when integrated electronic components are coupled to the gate of the device. While the previously mentioned tests may be omitted on semiconductor devices that include integrated components and other circuitry, omitting the tests may allow semiconductor devices with high gate leakage currents or latent defects to be placed in a production electronic product that may then experience premature failure in the field.
  • What is needed is a technique that allows semiconductor devices that include a device body including a plurality of parallel cells and at least one integrated electronic component to be tested without the test results associated with the plurality of parallel cells being adversely affected by the at least one integrated electronic component.
  • a semiconductor device includes a device body, a gate pad and a gate signal distribution runner.
  • the device body includes a plurality of parallel cells and at least one integrated electronic component.
  • the gate pad is located on a surface of the device body and includes a first portion and a second portion that are electrically isolated.
  • the gate signal distribution runner is electrically coupled to and extends from the first portion of the gate pad.
  • the gate signal distribution runner provides a gate signal to a gate of each of the plurality of parallel cells.
  • at least one integrated electronic component is electrically coupled to the second portion of the gate pad.
  • the plurality of parallel cells defines a metal-oxide semiconductor field-effect transistor (MOSFET).
  • the plurality of parallel cells defines an insulated-gate bipolar-junction transistor (IGBT).
  • the gate signal distribution runner is made of one of a metal and a polysilicon.
  • the metal is aluminum.
  • the integrated electronic component includes at least one of a resistor, a diode and a zener diode.
  • the first and second portions of the gate pad are electrically interconnected after testing of the parallel cells.
  • a semiconductor device includes a device body, a pad and a signal distribution runner.
  • the device body includes a plurality of parallel cells and at least one integrated electronic component.
  • the pad is located on a surface of the device body and includes a first portion and a second portion that are electrically isolated.
  • the signal distribution runner is electrically coupled to and extends from the first portion of the pad.
  • the signal distribution runner provides a signal to a same terminal of each of the plurality of parallel cells.
  • at least one integrated electronic component is electrically coupled to the second portion of the pad.
  • gate pad and gate signal distribution runners are utilized to provide gate signal distribution to a plurality of parallel cells of the devices.
  • the distribution of the gate signal controls the turn-on and turn-off characteristics of the device.
  • the gate pad has been a single metalized pad, which has been connected to an external package pin by a wire bond or solder interconnect.
  • integrated electronic components may provide control or protection functions for the power device.
  • additional complex logic or driver circuitry may be integrated within the device and be connected to various input/output pads to provide additional functionality.
  • the addition of the integrated electronic components and circuitry to the gate of the device affects the ability of a test engineer to accurately determine device characteristics, such as current leakage, gate stress and avalanche and also affects energy tests performed on the device.
  • the gate pad of the semiconductor device is partitioned to allow the semiconductor device to be tested, without the additional electronic components.
  • the pads are rejoined after testing such that the integrated electronic components are connected to the plurality of parallel cells that form the semiconductor device.
  • the electronic components may be added back into the circuit through soldering the partitioned gate pad together or wire bonding the partitioned gate pad together during the wire bonding process.
  • the present invention is applicable to the semiconductor devices that have top-side solderable or wire-bonded gate connections. It should be appreciated that a semiconductor device configured in this manner can be tested at the wafer level or at a die level using standard probe cards. In this manner, the probe cards and the tester hardware allow the various resistors, conventional diodes and/or zener diodes to be switched into or out of the circuit, thus, allowing full functional and parametric tests to occur at a wafer level. Further, special tests, such as gate level stress tests, energy tests and avalanche tests can also be performed without the test results being affected by the additional electronic components. When the semiconductor device is assembled into its package or system, the two or more split gate areas are then connected together through a solder connection or a wire bond.
  • edge patterns of the various portions of the gate pad may be optimized to ensure proper bridging during the solder reflow or wire bond process.
  • the present invention is also generally applicable to any input or output integrated circuit pad that has circuitry or protection devices attached to it that would adversely affect testing of the device. It should be appreciated that testing the integrated circuit (IC) with the option of switching circuitry in or out at the wafer level may also be generally desirable.
  • gate pad 304 of semiconductor device 300 is split into portions 304A and 304B.
  • the portion 304B is coupled to at least one integrated electronic component (not shown in Fig. 3), which may, for example, include a resistor, conventional diode or zener diode.
  • the semiconductor device 300 includes a device body 302 that has integrated therein a plurality of parallel cells (not shown), whose gates are coupled to the portion 304A of the gate pad 304 by peripheral gate runner 306 and middle gate runner 308.
  • the portion 304A is interconnected to the portion 304B, the electronic components connected to the portion 304B are connected between the devices gate and source (for a MOSFET) or gate to emitter or gate to collector for an IGBT.
  • the semiconductor device 300 is protected from transients and/or other circuitry integrated within the device body 302 is functional.
  • Fig. 4A shows an exemplary gate pad 400 that includes portions 402, 404, 406 and 408. It should be appreciated that one of the portions, e.g., portion 408, is coupled to gate runners to provide a gate signal to a plurality of parallel cells integrated in a device body of an associated semiconductor.
  • Fig. 4B shows an exemplary gate pad 410 that includes portions 412 and 414, one of which would be connected to a gate of each of the plurality of parallel cells.
  • Fig. 4C shows another exemplary gate pad 420, including portions 422 and 424, one of which is connected to the gate of a plurality of cells and the other of which is connected to at least one integrated electronic component.
  • Fig. 4D shows the pad 420 of Fig. 4C with the portions 422 and 424 interconnected by a wire 430 through a wire bonding process.
  • Fig. 5A is an electrical schematic of a semiconductor device 500 that includes a MOSFET 503 and an integrated electronic component 501, e.g., a resistor. As is shown in Fig. 5A, the resistor 501 is coupled between a first portion 502A of gate pad 502 and a source of the MOSFET 503. A gate of the MOSFET 503 is coupled to a second portion 502B of the gate pad 502.
  • Fig. 5B is an electrical schematic of a device 510 that is similar to the device 500 of Fig. 5A, with the exception that a pair of zener diodes 511 are coupled between the first portion 502A of the gate pad 502 and a source of a FET 513.
  • Fig. 5A is an electrical schematic of a semiconductor device 500 that includes a MOSFET 503 and an integrated electronic component 501, e.g., a resistor.
  • the resistor 501 is coupled between a first portion 502A of gate pad 502 and a source
  • 5C is an electrical schematic of a semiconductor device 520 that includes an insulated-gate bipolar-junction transistor (IGBT) 523, whose gate is coupled to the second portion 502B of the gate pad 502.
  • IGBT insulated-gate bipolar-junction transistor
  • Fig. 5D is an electrical schematic of a semiconductor device 530 that is similar to the semiconductor device 520 of Fig. 5C, with the exception that a gate pad 540 is divided into three portions, 540A, 540B and 540C.
  • a pair of zener diodes 531 are coupled between a first portion 540A of the gate pad 540 and a collector of a IGBT 533.
  • a resistor 535 is coupled between a second portion 540B of the gate pad 540 and an emitter of the IGBT 533.
  • a gate of the IGBT 533 is coupled to a third portion 540C of the gate pad 540.
  • the various portions of the gate pads 502 (540) of the semiconductor devices 500, 510 and 520 (530) are electrically interconnected.
  • a semiconductor device with a split pad design has been disclosed herein that advantageously allows for testing of a primary semiconductor device without the test results being affected by an integrated electronic component that is included in the semiconductor device.
EP05077999A 2005-01-13 2005-12-27 Halbleiterelement mit geteilter Anschlußfläche Withdrawn EP1681719A3 (de)

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