EP1609175A1 - Procede et appareil pour le developpement a sec de photoresist multicouche - Google Patents

Procede et appareil pour le developpement a sec de photoresist multicouche

Info

Publication number
EP1609175A1
EP1609175A1 EP04704022A EP04704022A EP1609175A1 EP 1609175 A1 EP1609175 A1 EP 1609175A1 EP 04704022 A EP04704022 A EP 04704022A EP 04704022 A EP04704022 A EP 04704022A EP 1609175 A1 EP1609175 A1 EP 1609175A1
Authority
EP
European Patent Office
Prior art keywords
recited
time
period
gas
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04704022A
Other languages
German (de)
English (en)
Inventor
Vaidyanathan Balasubramaniam
Koichiro Inazawa
Rich Wise
Arpan P. Mahorowala
Siddhartha Panda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
International Business Machines Corp
Original Assignee
Tokyo Electron Ltd
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/640,577 external-priority patent/US7344991B2/en
Application filed by Tokyo Electron Ltd, International Business Machines Corp filed Critical Tokyo Electron Ltd
Publication of EP1609175A1 publication Critical patent/EP1609175A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de gravure d'une couche de revêtement antireflet organique (ARC) sur un substrat se trouvant dans un système de traitement au plasma, qui consiste à : introduire un gaz de procédé comprenant de l'ammoniac (NH3) et un gaz de passivation ; former un plasma à partir du gaz de procédé ; et exposer le substrat au plasma. Le gaz de procédé peut, par exemple, être du NH3 et un gaz hydrocarboné tel qu'au moins un parmi C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10,et C6H12. Par ailleurs, la chimie de traitement consiste également à ajouter de l'hélium. L'invention porte également sur un procédé de formation d'un masque bicouche pour graver une couche mince sur un substrat, qui consiste à : former la couche mince sur le substrat ; former une couche d'ARC sur la couche mince ; former un motif de photorésist sur la couche d'ARC ; et transférer le motif de photorésist sur la couche d'ARC par un procédé de gravure utilisant un gaz de procédé comprenant de l'ammoniac (NH3), et un gaz de passivation.
EP04704022A 2003-03-31 2004-01-21 Procede et appareil pour le developpement a sec de photoresist multicouche Withdrawn EP1609175A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US640577 2000-08-17
US45843003P 2003-03-31 2003-03-31
US458430P 2003-03-31
US48422503P 2003-05-05 2003-05-05
US484225P 2003-05-05
US10/640,577 US7344991B2 (en) 2002-12-23 2003-08-14 Method and apparatus for multilayer photoresist dry development
PCT/US2004/001405 WO2004095551A1 (fr) 2003-03-31 2004-01-21 Procede et appareil pour le developpement a sec de photoresist multicouche

Publications (1)

Publication Number Publication Date
EP1609175A1 true EP1609175A1 (fr) 2005-12-28

Family

ID=33314234

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04704022A Withdrawn EP1609175A1 (fr) 2003-03-31 2004-01-21 Procede et appareil pour le developpement a sec de photoresist multicouche

Country Status (5)

Country Link
EP (1) EP1609175A1 (fr)
JP (1) JP2006522480A (fr)
KR (1) KR100989107B1 (fr)
TW (1) TWI228751B (fr)
WO (1) WO2004095551A1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049052B2 (en) * 2003-05-09 2006-05-23 Lam Research Corporation Method providing an improved bi-layer photoresist pattern
US7700494B2 (en) 2004-12-30 2010-04-20 Tokyo Electron Limited, Inc. Low-pressure removal of photoresist and etch residue
US8709706B2 (en) * 2011-06-15 2014-04-29 Applied Materials, Inc. Methods and apparatus for performing multiple photoresist layer development and etching processes
JP6495025B2 (ja) 2014-01-31 2019-04-03 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ 真空統合ハードマスク処理および装置
US9984858B2 (en) * 2015-09-04 2018-05-29 Lam Research Corporation ALE smoothness: in and outside semiconductor industry
US10727073B2 (en) 2016-02-04 2020-07-28 Lam Research Corporation Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces
KR102642011B1 (ko) 2018-03-30 2024-02-27 램 리써치 코포레이션 내화성 금속들 및 다른 고 표면 결합 에너지 재료들의 원자 층 에칭 및 평활화 (smoothing)
WO2020102085A1 (fr) 2018-11-14 2020-05-22 Lam Research Corporation Procédés de fabrication de masques durs utiles dans la lithographie de nouvelle génération
KR102431292B1 (ko) 2020-01-15 2022-08-09 램 리써치 코포레이션 포토레지스트 부착 및 선량 감소를 위한 하부층
KR20220137082A (ko) * 2020-02-04 2022-10-11 램 리써치 코포레이션 금속-함유 euv 레지스트의 건식 현상 성능을 개선하기 위한 도포 후 처리/노출 후 처리
US20220004105A1 (en) * 2020-07-01 2022-01-06 Applied Materials, Inc. Dry develop process of photoresist
US11621172B2 (en) 2020-07-01 2023-04-04 Applied Materials, Inc. Vapor phase thermal etch solutions for metal oxo photoresists
US20240053684A1 (en) * 2022-08-15 2024-02-15 Tokyo Electron Limited Cyclic Method for Reactive Development of Photoresists

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100718A (ja) * 2001-09-26 2003-04-04 Tokyo Electron Ltd エッチング方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3371143B2 (ja) * 1991-06-03 2003-01-27 ソニー株式会社 ドライエッチング方法
JP2897569B2 (ja) * 1991-12-30 1999-05-31 ソニー株式会社 レジストパターン形成時に用いる反射防止膜の条件決定方法と、レジストパターン形成方法
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
JP2958284B2 (ja) * 1997-03-27 1999-10-06 ホーヤ株式会社 転写マスク及びその製造方法並びにパターン転写方法
US6143476A (en) * 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
US6352937B1 (en) * 1998-04-27 2002-03-05 Sony Corporation Method for stripping organic based film
JP3637768B2 (ja) * 1998-04-27 2005-04-13 松下電器産業株式会社 トイレ装置
JP2002538604A (ja) * 1999-02-26 2002-11-12 トリコン ホールディングス リミティド ポリマー層の処理方法
GB9904427D0 (en) * 1999-02-26 1999-04-21 Trikon Holdings Ltd Method treating an insulating layer
JP2001345380A (ja) * 2000-05-31 2001-12-14 Toshiba Corp 半導体装置の製造方法および半導体装置
JP2002093778A (ja) * 2000-09-11 2002-03-29 Toshiba Corp 有機膜のエッチング方法およびこれを用いた半導体装置の製造方法
JP2002169302A (ja) * 2000-12-04 2002-06-14 Sony Corp 半導体装置の製造方法
US6841483B2 (en) * 2001-02-12 2005-01-11 Lam Research Corporation Unique process chemistry for etching organic low-k materials
US6599437B2 (en) * 2001-03-20 2003-07-29 Applied Materials Inc. Method of etching organic antireflection coating (ARC) layers
US6630407B2 (en) * 2001-03-30 2003-10-07 Lam Research Corporation Plasma etching of organic antireflective coating
JP2002351092A (ja) * 2001-05-29 2002-12-04 Matsushita Electric Ind Co Ltd エッチング方法
KR100479600B1 (ko) * 2001-06-28 2005-04-06 주식회사 하이닉스반도체 콘택 형성 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100718A (ja) * 2001-09-26 2003-04-04 Tokyo Electron Ltd エッチング方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2004095551A1 *

Also Published As

Publication number Publication date
JP2006522480A (ja) 2006-09-28
TW200425247A (en) 2004-11-16
KR20050112115A (ko) 2005-11-29
WO2004095551A1 (fr) 2004-11-04
TWI228751B (en) 2005-03-01
KR100989107B1 (ko) 2010-10-25

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