EP1588409A1 - Composant semi-conducteur a couche mince et son procede de production - Google Patents

Composant semi-conducteur a couche mince et son procede de production

Info

Publication number
EP1588409A1
EP1588409A1 EP04705375A EP04705375A EP1588409A1 EP 1588409 A1 EP1588409 A1 EP 1588409A1 EP 04705375 A EP04705375 A EP 04705375A EP 04705375 A EP04705375 A EP 04705375A EP 1588409 A1 EP1588409 A1 EP 1588409A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor body
carrier
thin film
film semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04705375A
Other languages
German (de)
English (en)
Inventor
Peter Stauss
Andreas PLÖSSL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10303978A external-priority patent/DE10303978A1/de
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP1588409A1 publication Critical patent/EP1588409A1/fr
Withdrawn legal-status Critical Current

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the invention relates to a semiconductor component according to the preamble of patent claim 1 and a method for its production according to the preamble of patent claim 13.
  • Semiconductor components of the type mentioned contain a thin film semiconductor body and a carrier on which the semiconductor body is attached.
  • Thin-film semiconductor bodies are used, for example, in optoelectronic components in the form of thin-film light-emitting diode chips.
  • a thin-film light-emitting diode chip is characterized in particular by the following characteristic features: on a first one facing a carrier element
  • a reflective layer is applied or formed on the main surface of a radiation-generating epitaxial layer sequence, which reflects at least some of the electromagnetic radiation generated in the epitaxial layer sequence back into the latter;
  • a thin-film light-emitting diode chip is a Lambert surface emitter in good approximation;
  • the epitaxial layer sequence has a thickness in the range of 20 ⁇ m or less, in particular in the range of 10 ⁇ m; and the epitaxial layer sequence contains at least one semiconductor layer with at least one surface which has a mixing structure which, in the ideal case, leads to an approximately ergodic distribution of the light in the epitaxial epitaxial layer sequence, ie it has a scattering behavior that is as ergodic as possible.
  • a basic principle of a thin-film light-emitting diode chip is described, for example, in I. Schnitzer et al. , Appl. Phys. Lett. 63 (16), October 18, 1993, 2174 - 2176, the disclosure content of which is hereby incorporated by reference. It should be noted that while the present invention relates particularly to thin film light emitting diode chips, it is not so limited. Rather, the present invention is suitable not only for thin-film light-emitting diode chips but also for all other thin-film semiconductor bodies.
  • a semiconductor layer is first produced on a suitable substrate, subsequently connected to the carrier and then detached from the substrate.
  • a plurality of semiconductor bodies are produced, each of which is attached to the corresponding carrier.
  • the substrate used to produce the semiconductor layer is removed from the semiconductor layer and does not simultaneously serve as a carrier in the component.
  • This manufacturing process has the advantage that different materials can be used for the substrate and the carrier.
  • the respective materials can thus be adapted largely independently of one another to the different requirements for the production of the semiconductor layer on the one hand and the operating conditions on the other hand.
  • the carrier can thus be optimized in accordance with its mechanical, thermal and optical properties, while the substrate is selected in accordance with the requirements for producing the semiconductor layer.
  • the epitaxial production of a semiconductor layer in particular places numerous special demands on the epitaxial substrate.
  • the substrate should withstand the epitaxial conditions, in particular temperatures up to over 1000 ° C., and be suitable for the epitaxial growth and growth of a layer of the semiconductor material in question that is as homogeneous as possible.
  • Detachment of the semiconductor layer from the epitaxial substrate can be achieved, for example, by irradiating the semiconductor-substrate interface with laser radiation.
  • the laser radiation is absorbed in the vicinity of the interface and there causes an increase in temperature until the semiconductor material decomposes.
  • Such a method is known for example from the publication WO 98/14986.
  • the frequency-tripled radiation of a Q-switched Nd: Yag laser at 355 nm is used.
  • the laser radiation is radiated through the transparent sapphire substrate onto the semiconductor layer and in an approximately 100 nm thick boundary layer
  • GaN substrate GaN arsenide substrate
  • thinning for example grinding the carrier after the semiconductor layer has been applied and detached from the epitaxial substrate, as a result of which the effort involved in production and the risk of breakage in the carrier increase.
  • this component should be technically simple and inexpensive to manufacture. Furthermore, it is an object of the invention to provide a corresponding manufacturing process.
  • germanium carriers it is provided according to the invention to form a semiconductor component with a thin film semiconductor body, which is arranged on a carrier containing germanium.
  • a germanium substrate is preferably used as the carrier.
  • these carriers are briefly referred to as "germanium carriers”.
  • a thin film semiconductor body is to be understood as a substrate-free semiconductor body, that is to say an epitaxially manufactured semiconductor body, from which the epitaxial substrate on which the semiconductor body was originally grown has been removed.
  • the semiconductor body can be glued to the germanium carrier, for example.
  • a soldered connection is preferably formed between the thin film semiconductor body and the carrier.
  • Such a solder joint generally has a higher temperature resistance and better thermal conductivity than adhesive joints.
  • an electrically good conductive connection between the carrier and the semiconductor body is created by means of a soldered connection without additional effort, which connection can also serve for contacting the semiconductor body.
  • Germanium carriers are much easier to process than arsenic carriers, with no toxic arsenic waste in particular. This will reduce the overall manufacturing effort. Furthermore, germanium carriers are characterized by a higher mechanical stability, which makes it possible to use thinner carriers and, in particular, to do without subsequent grinding of the carrier for thinning. After all, germanium carriers are significantly cheaper than comparable GaAs carriers.
  • the thin film semiconductor body is soldered onto the germanium carrier.
  • a gold-germanium solder connection is preferably formed for this purpose.
  • a firm, temperature-resistant and electrically and thermally highly conductive connection is thus achieved. Since the melting temperature of the gold-germanium compound that is produced is higher than the temperatures that usually arise during assembly of a finished component, for example when soldering onto a printed circuit board, the
  • the invention is particularly suitable for semiconductor bodies based on III-V compound semiconductors, including in particular the compounds Al x Ga ⁇ - x As with O ⁇ x ⁇ l, In x Al y Ga ⁇ - x - y P, In x As y Ga ⁇ - x _ y P, In x Al y Ga ⁇ - x _ y As, In x Al y Ga ! - x - y N, each with O ⁇ x ⁇ l, 0 ⁇ y-sl, O ⁇ x + y ⁇ l, and In x Ga ⁇ - x As ⁇ - y N y with O ⁇ x ⁇ l, O ⁇ y ⁇ l are to be understood.
  • III-V compound semiconductors including in particular the compounds Al x Ga ⁇ - x As with O ⁇ x ⁇ l, In x Al y Ga ⁇ - x - y P, In x As y Ga ⁇ - x _ y P, In x Al y Ga ⁇ - x _ y As
  • Sapphire or silicon carbide substrates are often used for the epitaxial production of the aforementioned nitride compound semiconductor In x Al y Ga ⁇ - x - y N. Since sapphire substrates are on the one hand electrically insulating and therefore do not allow vertically conductive component structures, and on the other hand silicon carbide substrates are comparatively expensive and brittle and therefore require complex processing, the further processing of nitride-based semiconductor bodies as thin film semiconductor bodies, that is to say without an epitaxial substrate, is special advantageous.
  • the thin film semiconductor body is first grown on a substrate, subsequently a germanium carrier, such as a germanium wafer, is applied to the side of the carrier facing away from the substrate, and then the thin film semiconductor body
  • the thin film semiconductor body is preferably soldered onto the carrier.
  • a gold layer is applied to the carrier and the thin film semiconductor body on the connection side. These gold layers are subsequently brought into contact, the pressure and temperature being chosen so that a gold-germanium melt is formed which solidifies to form a gold-germanium eutectic.
  • the gold layer can also be applied only to the carrier or the thin-film semiconductor body. It is also possible to apply a gold-germanium alloy instead of the gold layer or layers. Since the carrier itself contains germanium, on the one hand alloy problems as can occur with GaAs substrates are avoided. On the other hand, the germanium carrier with respect to the gold germanium Melt a germanium reservoir that facilitates the formation of the eutectic.
  • the substrate can be removed by means of a grinding or etching process. These steps are preferably combined so that the substrate is first ground down to a thin residual layer and then the remaining layer is etched off.
  • An etching process is particularly suitable for semiconductor layers on In x Al y Ga ⁇ _ x - y P- or In x As y Ga ⁇ - x . y P base grown on a GaAs epitaxial substrate.
  • the etching depth is expediently set by means of an etching stop, so that the GaAs epitaxial substrate is etched down to the semiconductor layers based on In x Al y Gaai x - y P or In x As y Ga ⁇ _ x - y P.
  • the substrate is preferably detached by means of laser radiation.
  • the substrate-semiconductor interface is irradiated with laser radiation through the substrate.
  • the radiation is absorbed in the vicinity of the interface between the semiconductor layer and the substrate and there leads to a temperature increase until the semiconductor material decomposes, the substrate detaching from the semiconductor layer.
  • a Q-switched Nd YAG laser with frequency tripling or an excimer
  • Laser which emits in the ultraviolet spectral range, for example.
  • pulsed operation of the excimer laser is advisable.
  • pulse durations of less than or equal to 10 ns have proven to be advantageous.
  • FIG. 1 shows a schematic illustration of an exemplary embodiment of a semiconductor component according to the invention
  • FIGS. 2a to 2d show a schematic representation of a first exemplary embodiment of a production method according to the invention using four intermediate steps
  • FIGS. 3a to 3e show a schematic illustration of a second exemplary embodiment of a production method according to the invention using five intermediate steps.
  • the semiconductor component shown in FIG. 1 has a carrier 4 in the form of a germanium substrate, on which a thin film semiconductor body 2 is fastened by means of a solder layer 5.
  • the thin film semiconductor body 2 preferably comprises a plurality of semiconductor layers that were first grown on an epitaxial substrate (not shown) that was removed after the semiconductor body had been applied to the carrier 4.
  • the design as a thin film component is particularly suitable for radiation-emitting semiconductor bodies, since absorption of the radiation generated and thus a reduction in the radiation yield in the epitaxial substrate is avoided.
  • the semiconductor layers can be arranged in the form of a radiation-generating pn junction, which can furthermore contain a single or multiple quantum well structure.
  • a mirror layer is preferably arranged between the radiation-emitting layer of the thin-film semiconductor body and the germanium carrier. This layer reflects the radiation components emitted in the direction of the germanium carrier and thus increases the radiation yield.
  • WEI The mirror layer is preferably embodied as a metallic layer, which can be arranged in particular between the layer formed by the soldered connection and the thin-film semiconductor body. Highly reflecting mirrors can be formed, for example, by first arranging a dielectric layer on the thin film semiconductor body and then the preferably metallic mirror layer, the mirror layer advantageously being partially interrupted for the electrical contacting of the thin film semiconductor body.
  • germanium carrier being used instead of the GaAs carrier. Since the thermal expansion coefficient of germanium is similar to the thermal expansion coefficient of gallium arsenide, it is usually possible to replace conventional GaAs substrates with germanium substrates without additional effort in the manufacture and without deterioration of the component properties. In contrast, germanium is characterized by a slightly higher thermal conductivity compared to gallium arsenide.
  • germanium substrates are also advantageous because of their low price, their easier processing and their comparatively high mechanical stability.
  • GaAs substrates with a thickness of over 600 ⁇ m can be exchanged for germanium substrates with a thickness of 200 ⁇ m, which means that subsequent thinning of the substrate can be omitted.
  • FIG. 2a a semiconductor body 2 is applied to a substrate 1.
  • the semiconductor body 2 can also have a plurality of individual layers, for example on
  • the semiconductor body 2 is provided with a metallization 3a on the side facing away from the substrate.
  • a gold layer is preferably evaporated.
  • a germanium carrier 4 is provided, on which a metallization 3b, preferably also a gold layer, is applied in a corresponding manner.
  • metallizations 3a, 3b serve on the one hand to form the soldered connection between the semiconductor body 2 and the substrate 1 and on the other hand form an electrically good conductive ohmic contact.
  • one of the gold layers 3a, 3b can be used
  • Gold-antimony layer 3c are applied, antimony serving as the n-doping of the contact to be formed.
  • antimony arsenic or phosphorus can also be used for doping.
  • a p-contact can also be formed, for example with an aluminum, gallium or indium doping.
  • only one metallization 3a or 3b can be used within the scope of the invention, which is applied either to the semiconductor body 2 or to the germanium carrier 4.
  • the germnium carrier 4 and the substrate 1 are joined together with the semiconductor body 2, the temperature and pressure being selected so that the metallization 3a, 3b, 3c melts and subsequently solidifies as a soldered connection.
  • a gold-germanium melt initially forms, which forms on cooling optionally forms antimony-doped gold germanium eutectic as a solder joint.
  • Protrusions and other surface shapes deviating from one plane can advantageously also be enveloped (accommodated) with this melt, so that, in contrast to conventional methods, it is possible to deviate from a plane-parallel melt front.
  • particles on the surface of the semiconductor body are enveloped by the melt and embedded in the soldered connection.
  • the substrate 1 is removed.
  • the substrate 1 is first ground down to a thin residual layer and then the residual layer is etched off.
  • a thin film semiconductor body 2 remains, which is soldered onto a germanium carrier 4.
  • this method is particularly advantageous for In x Al y Ga ⁇ _ x -yP-based semiconductor bodies on GaAs epitaxial substrates.
  • the substrate is lifted off by means of a laser detachment method.
  • a semiconductor body 2 preferably based on a nitride compound semiconductor, is grown on a substrate 1.
  • the semiconductor body 2 can comprise a plurality of individual layers and can be designed as a radiation-emitting semiconductor body.
  • a sapphire substrate is particularly suitable as substrate 1.
  • the solder joint 5 is removed speaking formed the previous embodiment.
  • two gold layers can be provided as described there, which are applied on the one hand to the carrier and on the other hand to the semiconductor body.
  • the semiconductor layer 2 is irradiated with a laser beam 6 through the substrate 1.
  • the radiation energy is predominantly absorbed close to the interface between the semiconductor layer 2 and the substrate 1 in the semiconductor layer 2 and causes material decomposition at the interface, so that the substrate 1 can subsequently be lifted off.
  • the strong mechanical loads that occur due to material decomposition are absorbed by the solder layer, so that even semiconductor layers with a thickness of a few micrometers can be detached from the substrate without destruction.
  • An excimer laser in particular a XeF excimer laser, or a Q-switched Nd: YAG laser with frequency tripling is advantageous as the radiation source.
  • the laser radiation is preferably focused by means of suitable optics through the substrate onto the semiconductor layer 2, so that the energy density on the semiconductor surface is between 100 mJ / cm 2 and 1000 mJ / cm 2 , preferably between 200 mJ / cm 2 and 800 mJ / cm 2 lies.
  • the substrate 1 can thus be lifted off the semiconductor body without residues, FIG. 3e. This type of separation advantageously enables the substrate to be used again as an epitaxial substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Lasers (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un composant semi-conducteur comprenant un corps semi-conducteur à couche mince (2) placé sur un support (4) contenant du germanium. L'invention concerne également un procédé pour la production d'un tel composant semi-conducteur.
EP04705375A 2003-01-31 2004-01-27 Composant semi-conducteur a couche mince et son procede de production Withdrawn EP1588409A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10303978A DE10303978A1 (de) 2002-01-31 2003-01-31 Dünnfilmhalbleiterbauelement und Verfahren zu dessen Herstellung
DE10303978 2003-01-31
PCT/DE2004/000121 WO2004068567A1 (fr) 2003-01-31 2004-01-27 Composant semi-conducteur a couche mince et son procede de production

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EP1588409A1 true EP1588409A1 (fr) 2005-10-26

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EP (1) EP1588409A1 (fr)
JP (1) JP4904150B2 (fr)
KR (2) KR20110010839A (fr)
CN (1) CN100524619C (fr)
TW (1) TWI237909B (fr)
WO (1) WO2004068567A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100595937C (zh) 2002-08-01 2010-03-24 日亚化学工业株式会社 半导体发光元件及发光装置
US8368092B2 (en) 2004-01-26 2013-02-05 Osram Opto Semiconductors Gmbh Thin film LED comprising a current-dispersing structure
JP4906256B2 (ja) * 2004-11-10 2012-03-28 株式会社沖データ 半導体複合装置の製造方法
TWI248222B (en) * 2005-05-12 2006-01-21 Univ Nat Central Light emitting diode and manufacturing method thereof
DE102005025416A1 (de) * 2005-06-02 2006-12-14 Osram Opto Semiconductors Gmbh Lumineszenzdiodenchip mit einer Kontaktstruktur
DE102008026839A1 (de) * 2007-12-20 2009-07-02 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines optoelektronischen Bauelements in Dünnschichttechnik
DE102008008595A1 (de) * 2007-12-21 2009-06-25 Osram Opto Semiconductors Gmbh Oberflächenemittierender Halbleiterlaser und Verfahren zu dessen Herstellung
DE102008045653B4 (de) * 2008-09-03 2020-03-26 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil
US9550353B2 (en) * 2014-07-20 2017-01-24 X-Celeprint Limited Apparatus and methods for micro-transfer-printing
WO2020142208A1 (fr) * 2019-01-02 2020-07-09 Lumiode, Inc. Système et procédé de fabrication de structures d'affichage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0977280A2 (fr) * 1998-07-28 2000-02-02 Interuniversitair Micro-Elektronica Centrum Vzw Dispositifs émetteurs de radiation à rendement élevé et méthode pour fabriquer de tels dispositifs
JP2001015798A (ja) * 1999-06-29 2001-01-19 Toshiba Corp 半導体発光素子
WO2002033760A1 (fr) * 2000-10-17 2002-04-25 Osram Opto Semiconductors Gmbh Procede de fabrication d'un composant semi-conducteur a base de gan

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4120706A (en) * 1977-09-16 1978-10-17 Harris Corporation Heteroepitaxial deposition of gap on silicon substrates
US4749840A (en) * 1986-05-16 1988-06-07 Image Micro Systems, Inc. Intense laser irradiation using reflective optics
JP2908818B2 (ja) * 1989-09-18 1999-06-21 株式会社日立製作所 半導体装置の製造方法
US5326424A (en) * 1989-12-06 1994-07-05 General Motors Corporation Cubic boron nitride phosphide films
US5300756A (en) * 1991-10-22 1994-04-05 General Scanning, Inc. Method for severing integrated-circuit connection paths by a phase-plate-adjusted laser beam
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
US6958093B2 (en) * 1994-01-27 2005-10-25 Cree, Inc. Free-standing (Al, Ga, In)N and parting method for forming same
JP3269251B2 (ja) * 1994-03-31 2002-03-25 株式会社デンソー 積層型半導体装置の製造方法
US5787104A (en) * 1995-01-19 1998-07-28 Matsushita Electric Industrial Co., Ltd. Semiconductor light emitting element and method for fabricating the same
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5674758A (en) * 1995-06-06 1997-10-07 Regents Of The University Of California Silicon on insulator achieved using electrochemical etching
US5625202A (en) * 1995-06-08 1997-04-29 University Of Central Florida Modified wurtzite structure oxide compounds as substrates for III-V nitride compound semiconductor epitaxial thin film growth
DE19546443A1 (de) * 1995-12-13 1997-06-19 Deutsche Telekom Ag Optische und/oder elektrooptische Verbindung und Verfahren zur Herstellung einer solchen
EP1758169A3 (fr) * 1996-08-27 2007-05-23 Seiko Epson Corporation Méthode de séparation, procédé de transfert d'un dispositif à film mince, et dispositif d'affichage à cristaux liquides obtenu par application du procédé de transfert
US5828088A (en) * 1996-09-05 1998-10-27 Astropower, Inc. Semiconductor device structures incorporating "buried" mirrors and/or "buried" metal electrodes
DE19640594B4 (de) * 1996-10-01 2016-08-04 Osram Gmbh Bauelement
DE19706279A1 (de) * 1997-02-18 1998-08-20 Siemens Ag Laservorrichtung
US5838870A (en) * 1997-02-28 1998-11-17 The United States Of America As Represented By The Secretary Of The Air Force Nanometer-scale silicon-on-insulator photonic componets
DE69826053T2 (de) * 1997-03-26 2005-09-29 Canon K.K. Halbleitersubstrat und Verfahren zu dessen Herstellung
JPH10326884A (ja) * 1997-03-26 1998-12-08 Canon Inc 半導体基板及びその作製方法とその複合部材
US5998291A (en) * 1997-04-07 1999-12-07 Raytheon Company Attachment method for assembly of high density multiple interconnect structures
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
US6380097B1 (en) * 1998-05-11 2002-04-30 The United States Of America As Represented By The Secretary Of The Air Force Method for obtaining a sulfur-passivated semiconductor surface
US6331208B1 (en) * 1998-05-15 2001-12-18 Canon Kabushiki Kaisha Process for producing solar cell, process for producing thin-film semiconductor, process for separating thin-film semiconductor, and process for forming semiconductor
US6136141A (en) * 1998-06-10 2000-10-24 Sky Solar L.L.C. Method and apparatus for the fabrication of lightweight semiconductor devices
US6504180B1 (en) * 1998-07-28 2003-01-07 Imec Vzw And Vrije Universiteit Method of manufacturing surface textured high-efficiency radiating devices and devices obtained therefrom
US6169298B1 (en) * 1998-08-10 2001-01-02 Kingmax Technology Inc. Semiconductor light emitting device with conductive window layer
JP2000174350A (ja) * 1998-12-10 2000-06-23 Toshiba Corp 光半導体モジュール
US6744800B1 (en) * 1998-12-30 2004-06-01 Xerox Corporation Method and structure for nitride based laser diode arrays on an insulating substrate
US6280523B1 (en) * 1999-02-05 2001-08-28 Lumileds Lighting, U.S., Llc Thickness tailoring of wafer bonded AlxGayInzN structures by laser melting
KR100660310B1 (ko) * 1999-07-30 2006-12-22 닛폰 이타가라스 가부시키가이샤 반도체 웨이퍼로부터 칩을 다이싱하는 방법 및 다이싱 영역에 설치된 홈의 구조
US6287882B1 (en) * 1999-10-04 2001-09-11 Visual Photonics Epitaxy Co., Ltd. Light emitting diode with a metal-coated reflective permanent substrate and the method for manufacturing the same
US6864158B2 (en) * 2001-01-29 2005-03-08 Matsushita Electric Industrial Co., Ltd. Method of manufacturing nitride semiconductor substrate
US6902098B2 (en) * 2001-04-23 2005-06-07 Shipley Company, L.L.C. Solder pads and method of making a solder pad
US6814832B2 (en) * 2001-07-24 2004-11-09 Seiko Epson Corporation Method for transferring element, method for producing element, integrated circuit, circuit board, electro-optical device, IC card, and electronic appliance
DE10203795B4 (de) * 2002-01-31 2021-12-09 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Halbleiterbauelements
DE10303978A1 (de) * 2002-01-31 2003-11-27 Osram Opto Semiconductors Gmbh Dünnfilmhalbleiterbauelement und Verfahren zu dessen Herstellung
TWI226139B (en) * 2002-01-31 2005-01-01 Osram Opto Semiconductors Gmbh Method to manufacture a semiconductor-component
JP4986406B2 (ja) * 2005-03-31 2012-07-25 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0977280A2 (fr) * 1998-07-28 2000-02-02 Interuniversitair Micro-Elektronica Centrum Vzw Dispositifs émetteurs de radiation à rendement élevé et méthode pour fabriquer de tels dispositifs
JP2001015798A (ja) * 1999-06-29 2001-01-19 Toshiba Corp 半導体発光素子
WO2002033760A1 (fr) * 2000-10-17 2002-04-25 Osram Opto Semiconductors Gmbh Procede de fabrication d'un composant semi-conducteur a base de gan

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2004068567A1 *

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TWI237909B (en) 2005-08-11
US20060180804A1 (en) 2006-08-17
CN1745458A (zh) 2006-03-08
WO2004068567A1 (fr) 2004-08-12
JP2006518102A (ja) 2006-08-03
CN100524619C (zh) 2009-08-05
KR101058302B1 (ko) 2011-08-22
JP4904150B2 (ja) 2012-03-28
TW200417063A (en) 2004-09-01
KR20110010839A (ko) 2011-02-07

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