EP1532629A1 - Elektronische einrichtung zum verarbeiten von daten auf burst-weise - Google Patents

Elektronische einrichtung zum verarbeiten von daten auf burst-weise

Info

Publication number
EP1532629A1
EP1532629A1 EP03787950A EP03787950A EP1532629A1 EP 1532629 A1 EP1532629 A1 EP 1532629A1 EP 03787950 A EP03787950 A EP 03787950A EP 03787950 A EP03787950 A EP 03787950A EP 1532629 A1 EP1532629 A1 EP 1532629A1
Authority
EP
European Patent Office
Prior art keywords
circuit
burst
data
delay line
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03787950A
Other languages
English (en)
French (fr)
Inventor
Cornelis Hermanus Van Berkel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP03787950A priority Critical patent/EP1532629A1/de
Publication of EP1532629A1 publication Critical patent/EP1532629A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10527Audio or video recording; Data buffering arrangements

Definitions

  • the present invention relates to an electronic device comprising a first and a second circuit designed for processing data in a burst-wise manner, the first circuit being designed for processing a data packet during a burst and supplying the second circuit with processed data.
  • the present invention also relates to an information reading system for reading data in a burst-wise manner.
  • the present invention also relates to an information recording system for recording data in a burst-wise manner.
  • the present invention is particularly relevant for an optical disc apparatus for reading and/or recording data from and/or to an optical disc, e.g. a CD or DVD player and/or recorder.
  • an optical disc e.g. a CD or DVD player and/or recorder.
  • An electronic device designed for processing data in a burst-wise manner is known from Applicant's EP 0 429 139.
  • This patent describes an information recording and read system comprising a recording and a read device.
  • a digital signal to be processed often has a lower bit rate than that for which the recording or the read device has been designed originally.
  • the read device comprises a light beam, which might be designed for reading data from a disc at a bit rate of 36 megabits per second, while the bit rate of the read system for audio data is typically 128 kilobits per second, i.e. the data should exit the read system at a bit rate of 128 kilobits per second.
  • data are read from the disc and processed in a burst-wise manner at high bit rate.
  • a data packet is read by the reading device at high bit rate, during a burst.
  • a burst corresponds to a period of time during which a data packet is read at high bit rate.
  • an analogue signal corresponding to these data is detected, and this analogue signal is converted into a digital signal.
  • the reading and detection correspond to a processing of a data packet and require a first circuit comprising powering means for powering the light beam and detecting means for detecting a signal corresponding to the data packet read from the disc.
  • the conversion requires a second circuit comprising an analogue to digital converter.
  • an electronic device as described in the opening paragraph, is characterised in that it comprises a delay line between the first and the second circuit.
  • the first circuit is powered between the beginning of a burst and the delay introduced by the delay line.
  • the second circuit there is no need to power the second circuit until it is supplied with data, and the first processed data coming from the first circuit reaches the second circuit after the delay.
  • the first and second circuits are powered together during a time shorter than the duration of a burst. The duration of a high peak power is therefore reduced.
  • the delay line introduces a delay longer than the duration of a burst.
  • the peak power is split into two parts, corresponding to respectively the first and the second circuit. Therefore, instead of a high peak power, two peak powers are obtained having a substantially identical amplitude if the power consumptions of the first and second circuits are substantially identical. In such a case, this preferred embodiment allows to reduce the amplitude of the peak power by about 2.
  • the delay line is a surface acoustic wave delay line. This embodiment is particularly advantageous when the data coming from the first circuit are analogue data. Actually, a surface acoustic wave delay line is able to deal with analogue data. Furthermore, a surface acoustic wave delay line is a passive component. Introducing a surface acoustic wave delay line between the first and second circuits will therefore not increase the average power consumption, or only very slightly.
  • Fig. 1 is a block diagram showing an electronic device according to the invention, with first and second circuits and a delay line;
  • Figs. 2a to 2e show the power consumption of the first and second circuits of Fig.l, with and without a delay line;
  • Fig. 3 illustrates an information reading system according to the invention
  • Fig. 4 illustrates an information recording system according to the invention.
  • FIG. l An electronic device according to the invention is depicted in Fig. l.
  • Such an electronic device comprises a first circuit 101, a second circuit 102 and a delay line 103.
  • the first and the second circuit 101 and 102 are designed for processing data in a burst wise-manner. This means that the first and second circuit 101 and 102 are designed for processing a data packet during a short period of time, called a processing period, which period is shorter than the time between two processing periods. In between two processing periods, the first and second circuits 101 and 102 do not process data, and can therefore be switched off. This allows reducing the average power consumption of the electronic device.
  • the first circuit 101 is designed for applying a first processing to a data packet during a burst, and supplying the second circuit 102 with processed data.
  • the second circuit 102 is designed for applying a second processing to these processed data. This second processing occurs during the burst, or at least begins during the burst. This means that the first and second circuit 101 and 102 have to be powered together during a certain time, as will be explained in more detail in Fig.2. During the time where the first and second circuits 101 and 102 are powered together, there is a large peak power due to the power consumptions of the first and second circuits 101 and 102.
  • the delay line 103 allows reducing this large peak power.
  • the processed data after having been processed by the first circuit 101, the processed data reach the second circuit 102 after a certain delay determined by the characteristics of the delay line.
  • the processing period is a burst, which means that the second processing occurs during a burst, and suppose the delay is equal to the duration of the burst, Then the data packet is processed by the first circuit 101 during a burst, and the first processed data reach the second circuit 102 at the end of the burst. Therefore, the second circuit 102 can be switched of during the burst, and the first circuit 101 can be switched off at the end of the burst.
  • the peak power during the burst thus is only due to the power consumption of the first circuit 101 and the peak power after the burst is only due to the power consumption of the second circuit 102.
  • the duration of the processing period is equal to the duration of two bursts, as will be explained in more detail in Fig.2.
  • the delay line 103 can be a surface acoustic wave delay line.
  • a surface acoustic wave delay line comprises an input interdigital transducer and an output interdigital transducer, which are used as input and output electrodes mounted on a piezoelectric substrate.
  • an analogue signal is applied at the input electrode, stress is created between the electrodes by the piezoelectric effect. This stress causes the substrate to shrink and expand, forming a surface acoustic wave which propagates along the substrate to the output electrode.
  • the wave causes a potential difference, which is then seen as a voltage.
  • the signal applied at the input of the surface acoustic wave delay line is thus recopied at the output, after a certain delay, which depends inter alia on the characteristics of the interdigital transducer and the length of the piezoelectric substrate.
  • a certain delay typically from 0.1 microsecond to 100 microseconds.
  • a suitable delay is chosen in order to reduce the peak power. As will be explained in detail in Fig.2, a delay which is slightly superior to the duration of the burst leads to a good peak power reduction.
  • a surface acoustic wave delay line can receive analogue data at its input and deliver analogue data at its output.
  • this analogue to digital converter can be placed after the delay line.
  • the analogue to digital converter can be the second circuit 102.
  • an analogue to digital converter often consumes a high power and therefore contributes to the large peak power in the absence of a delay line, this large peak power is reduced by using the surface acoustic wave delay line, as will be explained in more detail in Fig.2.
  • the surface acoustic wave delay line is a passive component. Therefore, coupling data into the surface acoustic wave delay line and reading out requires little power. As a consequence, introducing a surface acoustic wave delay line between the first and second circuits 101 and 102 does not increase the average power consumption, or only very slightly.
  • the delay line 103 can also be a charge-coupled device.
  • a charge-coupled device comprises MOS capacitors. When electric charges are applied at an input of a charge-coupled device, these electric charges can be displaced from one capacitor to the next by applying a certain voltage to the capacitors. Such a charge-coupled device can thus play the role of a delay line, with a delay depending on the number of capacitors.
  • a charge-coupled device can be used when the data processed at the output of the first circuit 101 are analogue data.
  • the delay line 103 can also be a memory, like a static random access memory SRAM.
  • SRAM static random access memory
  • Using a SRAM memory is particularly advantageous when the data at the output of the first circuit 101 are digital data. These data are stored in the memory, and a microprocessor sends the data stored in the memory to the second circuit 102 after a predetermined delay.
  • Figs. 2a to 2e represent the power consumptions as a function of time of the first and second circuits without and with a delay line, depending on the characteristics of the delay line.
  • the first circuit applies a first processing to a data packet during a burst, which has a duration B
  • the second processing applies a second processing to the data processed by the first circuit.
  • This second processing occurs during the burst, which means that data processed by the first circuit are immediately processed by the second circuit.
  • the processing period PP is a burst.
  • the first and the second circuit are therefore powered together during the time B, which leads to a large peak power during this time.
  • Another data packet is then processed by the first and the second circuit after a time ⁇ B, which is larger than the time B.
  • the time ⁇ B can be 10 or 100 times larger than the time B.
  • Such a processing is done in a burst-wise manner, because the data are processed during bursts B, and the time ⁇ B between bursts is larger than the duration of a burst.
  • Fig. 2b there is no delay line between the first and the second circuit, but the second processing does not occur exactly during a burst, because the transfer of data from the first circuit to the second circuit requires a time ⁇ t.
  • Fig. 2a corresponds to an ideal situation.
  • the time ⁇ t is much smaller than the time B, so that the real situation can be compared to the ideal situation. In the following, only the ideal situation is therefore considered, in which a large peak power occurs during a burst when no delay line is used.
  • Fig. 2c a delay line is used, with a delay D slightly larger than the time B. The first circuit processes a data packet during the time B, and is then switched off.
  • a first peak power thus occurs during a time B, with an amplitude equal to the power consumption of the first circuit.
  • the first data processed by the first circuit reach the second circuit after the delay D.
  • the second circuit can therefore be switched off during the time D, and then powered in order to process data.
  • a second peak power thus occurs after the delay D, with an amplitude equal to the power consumption of the second circuit.
  • the duration of this second peak power is B, because the last data processed by the first circuit reach the second circuit after a time D+B.
  • the sum of the amplitudes of the first and the second peak power is equal to the amplitude of the large peak power of Fig. 2a.
  • the average power consumption thus remains the same with or without a delay line, or increases only very slightly with a delay line, but the use of a delay line allows reducing the amplitude of the peak powers.
  • the duration of the processing period PP is increased.
  • the duration of the processing period PP is equal to B+D. This is not a constraint, because the data are processed in a burst-wise manner, and the time between two bursts is often much larger than the duration of a burst.
  • a delay line is used, with a delay D equal to the time B.
  • the duration of the processing period PP is two times the time B.
  • the average power still remains the same, and the amplitude of the peak powers is reduced.
  • a delay line is used, with a delay D slightly smaller than the time B.
  • the first and the second circuit are powered together during a time equal to B-D, because the first data processed by the first circuit reach the second circuit before the end of the burst.
  • a large peak power thus occurs during this time B-D.
  • Using such a delay line is advantageous if one only wants to reduce the duration of the large peak power. If one wants to suppress the large peak power, the delay lines of Fig. 2c and 2d are more appropriate.
  • Fig. 3 illustrates an information reading system according to the invention.
  • Such a reading system comprises an optical pickup 300, comprising powering means 301 for powering a light beam 302 and detecting means 304 for detecting a reflected light beam 303, an amplifier 310, a delay line 320, an analogue to digital converter 330, a digital processor 340 and a buffer 350.
  • This information reading system is designed for reading information recorded on an optical disc 360.
  • the invention might be carried out with any reading system comprising powering means for powering a reading device designed for reading a track on a recording medium.
  • the invention might be applied to a magneto-optical reading system.
  • the powering means 301, the detecting means 304 and the amplifier 310 form a first circuit.
  • the analogue to digital converter forms a second circuit.
  • the disc 360 has a spiral track and is rotated by a motor.
  • the system might further comprise a tracking device to ensure that the centre of the light beam 302 coincides with the middle of a given track, a focus control for keeping the light beam 302 in focus on the disc 360, and a radial positioning device, e.g. an actuator, to move the optical pickup 300 in a radial direction relative to the disc 360.
  • a tracking device to ensure that the centre of the light beam 302 coincides with the middle of a given track
  • a focus control for keeping the light beam 302 in focus on the disc 360
  • a radial positioning device e.g. an actuator
  • the light beam 302 is powered during a burst for reading a data packet located in a given portion of the disc 360 at a high reading bit rate.
  • the duration of a burst might be, for example, a few microseconds.
  • the reading bit rate might be, for example, 36 megabits per second.
  • the light beam 303 reflected from the disc 360 is detected by the detecting means 304, which might be a photodiode.
  • the light beam 302 and the detecting means 304 form a reading device.
  • the digital signal is then read from the buffer 350 at a bit rate lower than the high reading rate.
  • This bit rate might be, for example, 128 kilobits per second.
  • Data can be read from the buffer 350 until it is empty, or until a degree of filing of the buffer 350 is under a specific limit.
  • the buffer 350 might be of the First-In-First-Out type. When the degree of filing of the buffer 350 is under this specific limit, the light beam 302 is powered during another burst and positioned at the end of the portion of the disc scanned during the preceding burst, in order to read another data packet recorded on the disc 360. Such a positioning is described in EP 0 429 139.
  • Fig. 4 illustrates an information recording system according to the invention.
  • a recording system comprises a buffer 400, a digital processor 410, a digital to analogue converter 420, a delay line 430, a control circuit 440 and an optical pickup 450 comprising powering means 451 for powering a light beam 452.
  • the digital to analogue converter forms a first circuit.
  • the powering means 451 and the control circuit 440 form a second circuit.
  • This information recording system is designed for recording information on an optical disc 460, which is rotated by a motor. Like the reading system of Fig.3, this recording system might further comprise a tracking device, a focus control and a radial positioning device. The recording of information on the disc 360 is described hereinafter.
  • Digital information to be recorded on the disc 460 is loaded in the buffer 400 at a low bit rate.
  • This buffer 400 might be of the First-In-First-Out type.
  • a data packet is fetched from the buffer 400 during a burst, at a higher bit rate.
  • this data packet is eventually pre-processed by the digital processor 410, and is converted into analogue information by the digital to analogue converter 420.
  • Such a conversion corresponds to a processing applied by the first circuit.
  • the digital processor 410 might form part of the first circuit.
  • the processing applied by the first circuit comprises the pre-processing by the digital processor 410 and the conversion by the digital to analogue converter 420.
  • the analogue information is sent to the input of the delay line 430.
  • the control circuit 440 controls the placement of the optical pickup 450 and the light beam 452 is powered by the powering means 451 in order to write the information to be recorded on a given portion of the disc 460.
  • the duration of a burst can, for example, be determined by a degree of filing of the buffer 400. For example, when the degree of filing of the buffer 400 exceeds a specific upper limit, data are fetched from the buffer 400 until the degree of filing of the buffer 400 is under a specific lower limit.
  • the next data packet is fetched from the buffer 400 when the degree of filing of this buffer 400 again reaches the specific upper limit.
  • the control circuits then places the optical pickup in order to write data at the end of the portion where data have been written during the preceding burst.
EP03787950A 2002-08-14 2003-08-05 Elektronische einrichtung zum verarbeiten von daten auf burst-weise Withdrawn EP1532629A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP03787950A EP1532629A1 (de) 2002-08-14 2003-08-05 Elektronische einrichtung zum verarbeiten von daten auf burst-weise

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP02292039 2002-08-14
EP02292039 2002-08-14
EP03787950A EP1532629A1 (de) 2002-08-14 2003-08-05 Elektronische einrichtung zum verarbeiten von daten auf burst-weise
PCT/IB2003/003367 WO2004017320A1 (en) 2002-08-14 2003-08-05 Electronic device for processing data in a burst-wise manner.

Publications (1)

Publication Number Publication Date
EP1532629A1 true EP1532629A1 (de) 2005-05-25

Family

ID=31725500

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03787950A Withdrawn EP1532629A1 (de) 2002-08-14 2003-08-05 Elektronische einrichtung zum verarbeiten von daten auf burst-weise

Country Status (6)

Country Link
EP (1) EP1532629A1 (de)
JP (1) JP2005535997A (de)
KR (1) KR20050040919A (de)
CN (1) CN1675706A (de)
AU (1) AU2003251105A1 (de)
WO (1) WO2004017320A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8132030B2 (en) 2006-06-27 2012-03-06 Koninklijke Philips Electronics N.V. Device and a method for managing power consumption of a plurality of data processing units

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366757A (ja) * 1986-09-08 1988-03-25 Mitsubishi Electric Corp フレキシブルデイスク装置のモ−タオン・デイレイ回路
JP3230319B2 (ja) * 1992-07-09 2001-11-19 ソニー株式会社 音響再生装置
US5422781A (en) * 1993-12-30 1995-06-06 Intel Corporation Sense amplifier timing method and apparatus for peak power production
JPH07221672A (ja) * 1994-02-01 1995-08-18 Kazuhiko Yamanouchi 分散型周波数拡散通信方式
JP2000200461A (ja) * 1999-01-06 2000-07-18 Sanyo Electric Co Ltd ディスク記録装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None *
See also references of WO2004017320A1 *

Also Published As

Publication number Publication date
CN1675706A (zh) 2005-09-28
WO2004017320A1 (en) 2004-02-26
KR20050040919A (ko) 2005-05-03
AU2003251105A1 (en) 2004-03-03
JP2005535997A (ja) 2005-11-24

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