Classifications

• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D3/00—Electroplating: Baths therefor
  • C25D3/02—Electroplating: Baths therefor from solutions
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D3/00—Electroplating: Baths therefor
  • C25D3/02—Electroplating: Baths therefor from solutions
  • C25D3/38—Electroplating: Baths therefor from solutions of copper
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/18—Electroplating using modulated, pulsed or reversing current
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/60—Electroplating characterised by the structure or texture of the layers
  • C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
  • C25D5/611—Smooth layers
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/60—Electroplating characterised by the structure or texture of the layers
  • C25D5/615—Microstructure of the layers, e.g. mixed structure
  • C25D5/617—Crystalline layers
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D7/00—Electroplating characterised by the article coated
  • C25D7/12—Semiconductors
  • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/7684—Smoothing; Planarisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

• This invention relates generally to semiconductor processing methods, and more particularly to electropolishing and electroplating methods for electropolishing and electroplating conductive layers on semiconductor devices.
• transistor devices are manufactured or fabricated on semiconductor wafers using a number of different processing steps to create transistor and interconnection elements.
• conductive (e.g., metal) trenches, vias, and the like are formed in dielectric materials as part of the semiconductor device. The trenches and vias couple electrical signals and power between transistors, internal circuit of the semiconductor devices, and circuits external to the semiconductor device.
• the semiconductor wafer may undergo, for example, masking, etching, and deposition processes to form the desired electronic circuitry of the semiconductor devices.
• multiple masking and etching steps can be performed to form a pattern of recessed areas in a dielectric layer on a semiconductor wafer that serve as trenches and vias for the interconnections.
• a deposition process may then be performed to deposit a metal layer over the semiconductor wafer thereby depositing metal both in the trenches and vias and also on the non-recessed areas of the semiconductor wafer.
• the metal deposited on the non-recessed areas of the semiconductor wafer is removed.
• CMP chemical mechanical polishing
• a wafer assembly is positioned on a CMP pad located on a platen or web.
• the wafer assembly includes a substrate having one or more layers and/or features, such as interconnection elements formed in a dielectric layer.
• a force is then applied to press the wafer assembly against the CMP pad.
• the CMP pad and the substrate assembly are moved against and relative to one another while applying the force to polish and planarize the surface of the wafer.
• a polishing solution often referred to as polishing slurry, is dispensed on the CMP pad to facilitate the polishing.
• the polishing slurry typically contains an abrasive and is chemically reactive to selectively remove from the wafer the unwanted material, for example, a metal layer, more rapidly than other materials, for example, a dielectric material.
• CMP methods can have several deleterious effects on the underlying semiconductor structure because of the relatively strong mechanical forces involved.
• the mechanical properties of the conductive materials for example copper and the low k films used in typical damascene processes.
• the Young Modulus of a low k dielectric film may be greater than 10 orders of magnitude lower than that of copper. Consequently, the relatively strong mechanical force applied on the dielectric films and copper in a CMP process, among other things, can cause stress related defects on the semiconductor structure that include delamination, dishing, erosion, film lifting, scratching, or the like.
• Another method for removing metal films deposited on the non-recessed areas of the dielectric layer includes electropolishing.
• the surface of the metal film topology is desirably planar to prevent recesses and the like that may degrade device performance.
• a metal layer may be deposited or removed from a wafer using an electroplating or electropolishing process.
• an electroplating or electropolishing process the portion of the wafer to be plated or polished is immersed within an electrolyte fluid solution and an electric charge is then applied to the wafer. These conditions result in copper being deposited or removed from the wafer depending on the relative electrical charges.
• an exemplary method for electroplating a conductive film on a wafer.
• One exemplary method includes electroplating a metal film on a semiconductor structure having recessed regions and non-recessed regions. The method includes electroplating within a first current density range before the metal layer is planar above recessed regions of a first density. Further, electroplating within a second current density range after the metal layer is planar above the recessed regions, where the second current density range is greater than the first current density range. In one example, the method further includes electroplating in the second current density range until the metal layer is planar above recessed regions of a second density, the second density being greater than the first density, and electroplating within a third current density range thereafter.
• Figs. 1A and IB illustrate cross-sectional views of interconnect structures after metal plating and electropolishing respectively;
• FIGs. 2A - 2C illustrate cross-sectional views of a metal film profile during an exemplary metal plating process
• Fig. 3 illustrates an exemplary relationship between hump size, leveler concentration, and plating current
• Fig. 4 illustrates the relationship between plating current and hump size with and without leveler
• FIGS. 5A - 5C illustrate cross-sectional views of metal film profiles during an exemplary metal plating process
• FIGS. 6A - 6C illustrate cross-sectional views of metal film profiles during an exemplary metal plating process
• Figs. 7A - 7C illustrate cross-sectional views of metal film profiles during an exemplary metal plating process
• FIGs. 8A - 8C illustrate cross-sectional views of metal film profiles during an exemplary metal plating process
• Fig. 9 illustrates a cross-sectional view of an interconnect structure with a dummy structure
• Figs. 10A and 10B illustrate cross-sectional views of a metal film profile during an exemplary metal plating process
• FIGs. 11A and 11B illustrate cross-sectional views of a metal film profile during an exemplary metal plating process
• Figs. 12A - 12C illustrate cross-sectional views of a metal film profile during an exemplary metal plating process
• FIGs. 13A - 13H illustrate exemplary plating current sequences
• Figs. 14A - 14C illustrate plan views of various exemplary dummy structures
• Figs. 15A - 15C illustrate plan views of various exemplary dummy structures
• FIGS. 16A - 16C illustrate plan views of various exemplary dummy structures
• FIGS. 17A - 17C illustrate plan views of various exemplary dummy structures
• Figs. 18A and 18B illustrate cross-sectional views of metal film profiles during exemplary metal plating processes
• Figs. 19A-19F illustrate an exemplary electropolishing process for a dual damascene structure
• FIGs. 20A-20D illustrate an exemplary electropolishing process for a semiconductor structure
• Figs. 21A-21D illustrate exemplary metal layers of different grain sizes formed on semiconductor structures
• Figs.22A-22C illustrate various exemplary images of a copper layer having a relatively large grain size
• Figs.23A-23C illustrate various exemplary images of a copper layer having a relatively small grain size
• Fig. 24 illustrates a graph showing a relationship between grain size and surface roughness of a copper layer after electropolishing
• Figs. 25A-25D illustrate a change in a metal layer grain size with respect to time
• Fig. 26 illustrates a graph showing a general relationship of the metal layer grain size with respect to time
• Fig. 27 illustrates a graph showing the general relationship of the grain growth rate with respect to the annealing temperature
• Fig. 28A illustrates an exemplary electropolishing apparatus
• Fig. 28B illustrates an exemplary process for electropolishing a wafer
• Figs. 29A-29D illustrate an exemplary process for electropolishing a portion of a wafer
• Figs. 30A-30D illustrate an exemplary process for electropolishing a semiconductor structure
• Fig. 30E illustrates an exemplary electropolished semiconductor structure having copper recesses
• Fig. 31 illustrates an exemplary forward and reverse pulse waveform for an electropolishing method
• Figs. 32A-32F illustrate an exemplary electropolishing process including a forward and reverse pulse waveform
• Fig.32 G illustrates an exemplary semiconductor structure electropolished with a forward and reverse pulse waveform.
• an exemplary method for plating planar metal films on semiconductor structures includes plating a metal film with increased planarity over interconnect structures formed on semiconductor wafers, for example, with reduced hump or over-plating and dishing.
• Various exemplary plating methods are described for forming improved planar metal films on patterned semiconductor structures by using combinations of chemistry, plating process sequences, and/or adding dummy structures within interconnect structures.
• the semiconductor industry generally uses copper in a damascene process to form metal interconnections in semiconductor devices.
• the damascene process patterns dielectric material with recessed regions and non-recessed regions as canal-like trenches and/or vias corresponding to the desired interconnects.
• a barrier and seed layer may be deposited on the dielectric material structure followed by copper plated on the barrier and/or seed layer. Copper on the non-recessed regions is typically polished away by chemical mechanical polishing (CMP).
• CMP includes both chemical (ion exchange) and mechanical (stress) processes to remove the copper layer on the non- recessed regions leaving copper in the trenches and/or vias, i.e., the recessed regions. Pressure applied on the polished surface may result in oxide loss, erosion, metal delamination, and dielectric lifting.
• copper is desirably integrated with low-k dielectrics and preferably with ultra-low-k dielectrics (k ⁇ 2.5).
• the multi-step low-k implementation strategy described above is very costly, carries high risk, and gives IC manufacturers a great deal of uncertainty for the success of device manufacturability.
• An exemplary process that reduces the mechanical damage to low-k dielectric structures includes electropolishing.
• An exemplary electropolishing process is described in U.S. Patent No. 6,395,152, entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on July 2, 1999, which is incorporated in its entirety by reference herein.
• FIG. 1A An exemplary profile of a copper film 104 plated by a conventional plating process on a damascene structure is shown in Fig. 1A.
• the semiconductor structure includes a dielectric layer
• the structure may further include a barrier layer 106 and other materials known in the art.
• the structure includes a pattern of recessed regions lOlr and non-recessed regions lOln corresponding to trenches and/or vias separated by dielectric layer 108.
• Metal or copper layer 104 is formed over the structure filling the recessed regions lOlr and formed over the non-recessed regions lOln.
• the underlying structure typically results in a non-planar surface topology of copper layer 104 located over structures in dielectric layer 108.
• the non-planar topology may include a hump 102 and recess 110 corresponding generally to the underlying densely spaced recessed regions lOlr and wide opening recessed regions respectively.
• Hump 102, recess 110, and other non-planar features may be caused, for example, by the plating chemistry in an electroplating process.
• Fig. IB illustrates the structure of Fig. 1A after an electropolishing process.
• Metal layer 104 is typically polished back to the surface of the non-recessed areas such that metal layer 104 within the recessed regions lOlr, i.e., the trenches and vias, is isolated from adjacent recessed regions lOlr.
• hump 102 may remain at least partially over the dense pattern area and dishing, shown by recessed region 110, may remain after electro-polishing due to the isotropic nature of the electropolishing. Humps and recesses may degrade the performance of the formed devices.
• a hump left above densely spaced trenches or vias may cause an electrical short circuit between adjacent lines and recesses may result in the reduction of the conductance of the formed interconnection lines.
• Plating a planar metal layer 104 may reduce humps and recesses and improve device performance.
• Figs. 2A-2C illustrate an exemplary electroplating process over time for plating copper layer 204 over a dielectric layer 208 having a plurality of densely spaced recessed regions 210r and non-recessed regions 210n.
• a plating bath includes three main additives, e.g., an accelerator, a suppressor, and a leveler.
• the primary function of the accelerator is to enhance the plating process within recessed regions; the primary function of suppressor is to suppress the plating process on the shoulder of the recessed regions; and the primary function of leveler is to level the surface profile of the plated film, mostly to level hump 202.
• the combination of accelerator and suppressor results in the super fill or bottom fill as illustrated in Fig.2A.
• the plating rate at the bottom of the trench or recessed region 210r is significantly higher than at the top and shoulder of the recessed region 210r.
• the chemicals in the trench region will continue to enhance the plating rate resulting in humps 202 as shown in Fig. 2B, which may run together over time to form a larger hump 202 as shown in Fig. 2C.
• Fig. 3 illustrates a relationship between leveler concentration and relative hump height (often referred to as the "over-plating burden") at increasing plating currents 394, 392, and 390.
• the relationship suggests that hump size may be reduced with sufficient concentrations of leveler and increased plating currents as shown in the graph as leveler concentration increases.
• Fig. 4 further shows a relationship between the plating current and hump size with leveler 498 and without leveler 496. As can be seen, the instance with leveler 498 may reduce the hump size at most plating currents. However, at large plating currents a hump may still occur despite leveler 498. Further, hump size is relatively greater at all currents without leveler.
• Figs. 5A - 5C show the profiles of metal film 504 over time during an exemplary plating process at a relatively small plating current li.
• the exemplary process includes directing electrolyte fluid at a rotating chuck holding a wafer, but as will be recognized, other methods such as immersion and the like may be used.
• the rotating chuck may rotate at a speed in the range of, e.g., 50-200 rpm, and preferably 125 rpm.
• a planar metal film 504 can be plated under the following exemplary process conditions:
• Electrolyte fluid such as ViaForm manufactured by Enthone-OMI
• Accelerator 1.5 to 2.5 ml/liter, preferably 2 ml/liter
• Suppressor 7 to 9 ml/liter, preferably: 8 mi/liter
• Leveler 1.25 to 1.75 ml/liter, preferably: 1.5 ml/liter
• Copper 16 to 20 gram/liter, preferably, 17.5 gram/liter
• Sulfuric Acid 150 to 200 gram liter, preferably 175 gram/liter
• Rotation speed of wafer 50 to 200 rpm, preferably 125 rpm
• the exemplary process plates copper layer 504 over dielectric layer 508, filling the recessed regions 510r and non-recessed regions 510n relatively quickly as seen at ti .
• recessed regions 510r are filled and metal layer 504 is relatively planar above the recessed and non-recessed regions 510r and 510n of dielectric layer 508.
• t 3 where t 3 is greater than t 2 , the exemplary process continues to plate metal layer 504 at a constant rate above recessed regions 510r and non-recessed regions 510n to create a planar metal layer 504 of a desired height above the structure.
• Figs. 6A — 6C show exemplary profiles of a metal film during a similar plating process, but at a relatively larger plating current than the process of Figs. 5A - 5C.
• the plating current density I 2 is in the range of 5mA/cm 2 to 30 mA/cm 2 , for example.
• the exemplary process at the relatively larger plating current produces humps 602 over recessed regions 610r at t 2 .
• the humps 602 may grow together to form a larger hump 602 at t 3 .
• Figs. 7A - 7C show exemplary profiles of a metal film profile during another exemplary metal plating process.
• the plating process is conducted at a relatively smaller current li similar to Figs. 5A-5C up to process time t 2 to produce a hump free profile of metal layer 704.
• the plating current may thereafter be increased to I 2 and plated to time t 3 , as illustrated in Fig. 7C, to a desired thickness of metal layer 704.
• the exemplary two-step plating process can achieve a planar metal film 704.
• the trenches or vias are fully plated to form a planar metal film 704 before increasing the current to a level where humps will form.
• a hump may appear above recessed region 7010r as the current is increased.
• Figs. 8A - 8C illustrate a metal film profile during a metal plating process where the plating current is increased to I 2 before the recessed regions 810r are filled. As shown in Fig. 8B, the small hump 802 develops due to the large plating current I 2 .
• the small individual humps grow into a large singular hump 802 as shown in Fig. 8C. It should be recognized that the current from ti to t 2 need not be constant and/or increase stepwise, but may increase smoothly during time ti to t 2 .
• dummy structure 980 can be added inside the recessed region 911r, e.g., a trench and/or pad area, as shown in Fig. 9.
• exemplary dummy structures may be found in U.S. Patent Application Serial No. 10/108,614, entitled ELECTROPLISHING METAL LAYERS ON WAFERS HAVING TRENCHES OR VIAS WITH DUMMY STRUCTURES, filed on March 27, 2002, which is incorporated in its entirety by reference herein.
• Figs. 10A and 10B show cross-sectional views of a plating profile during an exemplary plating process at a constant current over time.
• the plating process uses a relatively small current and leveler resulting in a flat profile above the relatively dense trench or vias lOlOr.
• the dummy structure area 1080 has more area to be plated resulting in a slight dishing 1020 of the final plating profile.
• the slight dishing 1020 will likely remain in the final profile after a subsequent electropolishing process as described above. Therefore, it is desirable to have a process that can plate a planar film on both densely spaced recessed regions lOlOr and the large trench area with dummy structure 1080.
• the size of dense trench or via region lOlOr can be in the range of 0.035 to 0.5 micron with spacing between the trench or between the via in the range of 0.035 to 0.5 micron.
• the dummy structure 1080 size may be in the range of 0.05 to 2.0 micron with space in the range of 0.05 to 2.0 micron, preferably 0.5 micron.
• the dummy structure should be designed with relatively small size and larger space to minimize the copper loss in the trenches.
• Figs. 11A and 11B show cross-sectional views of a plating profile during an exemplary plating process including varying the current over time.
• the structure includes dummy structure
• Copper film 1104 is plated at a relatively lower plating current li until dense recessed regions lllOr are filled as shown in Fig. 11 A.
• Recesses 1120 are formed in the relatively wider trenches/pad regions. The process continues to plate copper at a relatively higher plating current I 2 , i.e., where I 2 > li, and a hump will grow from dishing 1120 such that the hump effect offsets the dishing to plate a planar surface as shown in Fig. 11B.
• a hump does not form above the dense recessed regions lllOr because the dense trenches or vias have already been filled during the first portion of the process by using the relatively small plating current li.
• the two-step plating process results in a more planar profile of metal layer 1104 above the densely spaced recessed regions lllOr and the large trench and/or pad area having dummy structure 1180 formed therein.
• Figs. 18A and 18B show cross-sectional views of metal film profiles over exemplary dummy structures.
• the ratio of the depth H of a trench and/or pad to dummy structure space or width W between structures may be varied to increase the planarity of a metal film.
• the ratio of trench and/or pad height to dummy structure space is in the range of 0.3 to 2.0, and preferably 1.
• a deep trench will have a tendency to have more hump 1802 as shown in Fig. 18B, which will be used to balance the dishing 1810 for a wide space dummy structure, whereas a shallow trench will have a tendency to have less hump 1802 as shown in Fig. 18A.
• Figs. 12A - 12C show cross-sectional views of a plating profile during an exemplary plating process that varies the current over time.
• the interconnect structure in dielectric layer 1208 is similar to that shown in Figs. 11A and 11B, except that dummy structure 1280 is placed within the large trench or pad 1209, 1211 at space wi and space w 2 , where w 2 > Wi.
• An exemplary three- step plating process is described to plate a planar metal film 1204, e.g., that is hump-free and dishing-free, on densely spaced recessed regions 1210r and wide trench regions 1209 and 1211 adjacent dummy structure 1280.
• the exemplary process through times ti and t 2 are similar to those previously described in Figs. 11A and 11B with respect to increasing the current to create a planar topology above narrow recessed regions 1210r and narrow space wi.
• space w 2 still has dishing 1220 as shown in Fig. 12A.
• the current is further increased to I 3 to plate above w 2 .
• the process increases the plating current from I 2 to I 3 to fill the recess 1220 and continues to plate the structure through t 3 . Since the recessed region 1210r and 1209 have been previously filled with metal layer 1204 at ti and t 2 , the large current I 3 will not create a hump above these regions.
• the large plating current I 3 will create a hump above trench 1211 because trench 1211 was not fully filled before the plating process increases the current to I 3 , as illustrated in Fig. 12B.
• Figs. 13A - 13H show various exemplary plating current sequences over time that may be used to achieve a planar metal layer.
• the exemplary plating current sequences including both current level and timing may be adjusted according to the size, spacing, and density of trenches and vias as well as the size and space of a dummy structure.
• the current sequence over time is controlled such that the effects of hump and dishing during plating balance or offset each other to create a planar metal layer surface.
• the plating current can be linear as shown in Fig.
• the current sequences may decrease over periods of time as shown in Figs. 13G and 13H.
• the plating current begins at a relatively small current and grows larger as the plating process progresses.
• the plating power supply can be run in constant voltage mode.
• the above description can change from current to voltage or to pulse power supply.
• pulse waveforms may be used such as bipolar pulse, modified sine-wave, unipolar pulse, pulse reverse, pulse on pulse, and duplex pulse. Exemplary pulse wave forms are described in U.S. Patent No. 6,395,152, entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on July 2, 1999, which is incorporated in its entirety by reference herein.
• Figs. 14A - 14C are plan views of various exemplary dummy structures.
• Dummy structure may include a metal plug 1420 placed outside the trench, or the pad area, often referred to as the open area or field area, as shown in Fig. 14A.
• dielectric slots 1430 can be placed inside the large trench and/or pad area 1404, or dielectric dots 1450 can be placed inside the large trench and/or pad area 1404 as shown in Figs. 14B and 14C.
• Figs. 15A - 15C are plan views of additional exemplary dummy structures that may be included in relatively large vias or recessed regions.
• Metal plug dummy structure in Fig. 15A is similar to that illustrated in Fig. 14A, except the metal plug column 1522 is shifted lower relatively to metal column 1520.
• Metal plug dummy structure in Fig. 15B is similar to that shown in Fig. 15A, except metal plugs 1520 and 1522 are rotated 45 degrees, which may reduce the inductance and capacitance of metal plug 1520 and 1522.
• Dielectric dots 1550 that are placed inside the large trench and/or pad area 1504 as shown in Fig. 15C are similar to those illustrated in Fig. 14C, except that dielectric dots 1550 are rotated 45 degrees and individual columns are shifted lower relative to adjacent column of dielectric dots 1550. The size and spacing may be adjusted depending on the particular application and the like.
• Figs. 16A - 16C are plan views of additional exemplary dummy structures.
• Metal plug dummy structure as shown in Fig. 16A is similar to those illustrated in Fig. 14A, except the metal plug column 1622 is shifted at an angle ⁇ . The angle may be in the range of approximately 5 to 85 degrees, and preferably about 25 degrees.
• Dielectric slots 1630 as shown in Fig. 16B are similar to those illustrated in Fig. 14B, except that the dielectric slots 1630 are disconnected from each other in order to enhance the conductance of copper trench and/or pad 1604.
• Dielectric dots 1650 placed inside the large trench and/or pad area 1604 as shown in Fig. 16B are similar to those illustrated in Fig.
• dielectric dots 1650 are rotated 45 degrees. It should be recognized that the rotation angle of dielectric dots 1650 may be in the range of 0 to 90 degrees, and further that that dielectric dots 1650 may be shaped as squares, rectangles, circles, and the like.
• Fig. 17A - 17C are plan views of additional exemplary dummy structures.
• Metal plug dummy structures 1720 and 1722 as shown in Fig. 17A are similar to those illustrated in Fig. 14A, except the metal plug 1722 and 1722 are rotated about 45 degrees.
• Metal plugs 1722 and 1722 may be rotated between 0 and 90 degrees, and may be rotated at various degrees within a single structure.
• Dielectric slots 1730 as shown in Fig. 17B are similar to those illustrated in Fig. 16B, except that the dielectric slots 1730 are disconnected at similar locations along the horizontal direction.
• Dielectric dots 1750 placed inside the large trench and/or pad area 1704 as shown in Fig. 17C are similar to those illustrated in Fig. 14C, except that dielectric dots 1750 are shifted lower relative to adjacent columns of dielectric dots 1750.
• multi-layer metal interconnect structures may be fabricated with minimum recess and/or better planarity.
• a copper layer is formed over a dielectric structure including recessed areas and non-recessed areas.
• the copper layer is planarized at a height above the non-recessed regions, for example, through a CMP process and/or an electropolishing process with dummy structures in the dielectric structure.
• the planarized copper layer is then electropolished to a height below the non-recessed area height to form a recess.
• the non-recessed regions of the structure are then etched to planarize the copper layer with the non-recessed regions or reduce the recess of the copper layer.
• Fig. 19A illustrates an exemplary dual damascene structure after copper layer 1902, or other suitable conductive layer, has been formed over the structure.
• the dual damascene structure may be formed by any suitable method. For example, methods such as chemical vapor deposition (CVD), spin-on techniques, and the like may form the first dielectric layer 1912.
• the thickness of dietetic layer 1912 can be in the range of approximately 1000 A to 5000 A, and preferably 3000 A.
• An etch stop layer 1910 such as silicon nitride or silicon carbide (SiC) layer is deposited above the dielectric layer 1912.
• the thickness of etch stop layer 1910 can be in the range of approximately 200 A to 1000 A, and preferably 500 A.
• etch stop layer 1910 may be omitted and the etch timed to stop at the desired level to form the dual damascene structure.
• a second dielectric layer 1908 is deposited on etch stop layer 1910 by using CVD or spin-on techniques, for example. The thickness of second dielectric layer 1908 can be in the range of approximately 1000 A to 4000 A, and preferably 2000 A.
• a hard mask layer or a second etch stop layer 1906 is deposited on the second dielectric layer 1908.
• the hard mask layer or etch stop layer 1906 may be made of suitable materials such as SiO, SiC, SiN, and the like.
• the trench and via may be formed by successive formations of photo masks and etches as is known in the art. For example, a first photo mask may be formed for etching the trench followed by a second photo mask to etch the via.
• barrier layer 1904 is deposited by CVD, physical vapor deposition (PVD), or atomic layer deposition.
• the thickness of barrier layer 1904 can be in the range of 20 A to 250 A, depending on trench size and deposition techniques.
• Barrier layer 1904 may include any suitable material, such as Tantalum (Ta), TaN, Titanium (Ti), TiN, TaSiN, Tungsten (W), WN, WSiN, and the like.
• copper seed layer (not shown on drawing) can be deposited on barrier layer 1904 by CVD, PVD, or ALD. Then copper layer 1902 is deposited on copper seed layer, for example, by CVD, PVD, electroplating, electroless plating techniques, and the like.
• copper layer 1902 may include recessed regions 1916r corresponding to the trench and via areas depending on the particular deposition process. Planarity of copper layer 1902 may be increased by chemical mechanical polishing (CMP) a distance sufficient to remove the recess by including dummy structures within recesses of the dielectric structure for hump free plating techniques and the like. Copper layer 1902 is shown in Fig. 19B after a planarization process. An exemplary planarization method using a combination of CMP and electropolishing is described in U.S. application Serial No.
• Copper layer 1902 is polished from non-recessed regions 1916n by an electropolishing method to isolate the copper from adjacent trenches and vias (not shown).
• copper layer 1902 is polished to a height ⁇ h below the height of etch stop layer 1906 or non-recessed regions 1916n.
• the recess ⁇ h allows for a robust electropolishing process and increases the probability that all copper on the non-recessed portions 1916 has been removed.
• the ⁇ h can be in the range of 100 A to 1500 A, preferably 500 A.
• An exemplary process is described, e.g., in PCT Application No.
• PCT/US99/15506 entitled METHODS AND APPARATUS FOR ELECTROPOLISHTNG METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on July 8, 1999, the entire content of which is incorporated herein by reference.
• the recess of copper layer 1902 will cause poor planarity when another dielectric layer, masking layer, or the like is deposited over the structure.
• the poor planarity can cause defocus of a lithography process, and the like.
• barrier layer 1904 and in some instances a portion of hard mask layer 1906 may be etched away by plasma etching, wet etching, or the like to form a planar top surface of the structure as illustrated in Fig. ID.
• a portion of the hard mask layer 1906 is etched such that the surface level or height of copper layer 1902 is planar with the surface of the remaining portion of hard mask layer 1906.
• the polish of copper layer 1902 result in a ⁇ h less than the total thickness of barrier layer 1904 and the thickness of hard mask layer 1906. If ⁇ h is too great, the low dielectric constant k of dielectric layer 1908 will be exposed when barrier layer 1902 is etched away from the nonrecessed regions 1916r of the structure. This may lead to dielectric layer 1908 being etched, for example, by a plasma etch. Generally, the plasma etch rate of the low k material is higher than that of hard mask 1906 and copper layer 1902. An etch may also damage or increase the k of dielectric layer 1908 if dielectric layer 1908 is exposed.
• a polymer layer (not shown) may be formed on the surface of copper layer 1902 and hard mask layer 1906.
• the polymer layer is cleaned before additional layers are deposited.
• the polymer may be cleaned, for example, by a suitable plasma dry ashing process or chemical wet cleaning process.
• a dielectric layer 1926 such as silicon nitride or SiC can be formed on copper layer 1902 and hard mask layer 1906, as shown in Fig. 19E.
• the thickness of dielectric layer 1926 can be in the range of 200 A to 1000 A, and preferably 500 A. Additionally, a passivation layer or the like may be included over the structure.
• Fig. 19F the processes described in Fig. 19A may be repeated above dielectric layer 1926. Specifically, additional trenches and vias may be formed with a dielectric layer 1920 and dielectric layer 1924 formed on etch stop layers 1922 and 1926. Additionally, barrier layer 1916 may be formed over the structure as well as a seed layer (not shown) and copper layer 1914. A similar process to Figs. 19B-19E may be performed to produce a planar structure.
• Figs. 20A-20D illustrate another exemplary method for reducing the recess in a metal trench or metal pad after an electropolishing process. In this instance the structure includes a dielectric layer 2012 patterned with recessed regions 2016r and non-recessed regions 2016n.
• the non-recessed regions 2016r further include a multi-layer hard mask layer including, for example, a lower hard mask layer 2006 and upper hard mask layer 2007.
• the upper hard mask layer 2007 serves as a sacrificial layer to an etching process and the lower hard mask layer 2006 serves as an etch stop layer as described below.
• Hard mask layers 2007 and 2006 may be made of suitable materials such as SiO, SiC, SiN, and the like.
• a barrier/seed layer 2004 and metal layer 2002 are deposited over the structure filling the recessed regions 2016r.
• metal layer 2002 is planarized and electropolished to a height ⁇ h below the height of non-recessed regions 2016n as shown in Figs. 20B and 20C.
• Metal layer is preferably etched to a height substantially planar with lower mask 2006.
• Barrier layer 2004 and upper hard mask layer 2007 may be selectively etched away to lower mask hard layer 2006, where upper hard mask layer 2007 serves as a sacrificial layer and lower hard mask layer 2006 serves as an etch stop layer.
• the materials of upper hard mask layer 2007 and lower hard mask layer 2006 may be selected such that a plasma etch or the like removes upper hard mask layer 2007 and stops at lower hard mask layer 2006.
• the resulting surface of metal layer 2002 and lower hard mask layer 2006 are substantially parallel as illustrated in Fig. 20D.
• multi-layer metal e.g., copper, interconnect structure can be fabricated with minimum recess and/or better planarity.
• exemplary methods for reducing recesses in copper electropolishing have been described with respect to certain embodiments, examples, and applications, it will be apparent to those skilled in the art that various modifications and changes are contemplated.
• various dielectric materials and processing techniques to planarize the copper layer, polish the metal layer and the like may be used.
• the surface of the metal layer may be rough causing degradation of the performance of semiconductor devices.
• the surface of a copper layer after electropolishing can have a surface roughness of up to a few hundred nanometers. Increased surface roughness may result in poor planarization, surface corrosion, yield loss, and the like.
• the grain size of a metal layer can be controlled during various stages of exemplary plating and polishing processes to improve device performance and characteristics.
• additives such as brightener, leveler, and the like, can be used to control the grain size.
• the amount of time between the plating process and the electropolishing process can be shortened to reduce the grain size.
• an annealing process can be used to increase grain size after electropolishing to improve electrical characteristics. Electropolishing metal layers and metal interconnections on semiconductor devices is described, e.g., in U.S. Patent Application Serial No. 09/497,894, entitled METHODS AND APPARATUS FOR ELECTROPOLISHTNG METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on February 4, 2000, which is incorporated in its entirety by reference.
• the amount of surface roughness after electropolishing can depend, at least in part, on the microstructure of the metal layer being electropolished.
• Figs. 21A-21D illustrate a semiconductor wafer 1000 after an electropolishing process and including metal layers with different microstructures.
• the metal layers may also be formed within a trench or via of a semiconductor structure or the like.
• the size of the grains within the microstructure affect the surface roughness of the metal layer after electropolishing because the removal or polishing rate of the metal layer at the grain boundary and at the grain surfaces may differ.
• the polishing rate of the metal layer 2102 at different grain faces may differ. Accordingly, as illustrated in Figs.
• the surface topography after electropolishing can vary based on the size of the grains in the metal layer. Generally, the smaller the grain sizes the lower the surface roughness of the polished metal layer as seen in Fig. 21A. Similarly, the larger the grain size, the higher the surface roughness of polished metal layer as seen in Fig. 21D.
• Figs. 22A-22C show images of a copper layer having a relatively large grain size, e.g., a few microns.
• a scanning electron microscope (SEM) image of the copper layer surface after electropolishing is shown.
• a focused ion beam (FIB) image of the same copper layer surface after electropolishing is shown from the same location as shown in Fig. 22A.
• the images shown in Figs.22A and 22B indicate that the surface roughness of the copper layer can have a pattern that matches the pattern of the grains in the copper layer.
• Fig. 22C shows an atomic force microscope (AFM) image of the copper layer surface after electropolishing. Based on this AFM image, the mean roughness (R a ) of the copper layer surface is 14 nm, and the max height (R max ) of the copper layer surface is 113 nm.
• AFM atomic force microscope
• Figs. 23A-23C show images of a copper layer having a relatively small grain size, e.g., tens of nanometers.
• a scanning electron microscope (SEM) image of the copper layer surface before electropolishing is shown.
• a SEM image of the copper layer surface after electropolishing is shown.
• the images in Figs. 23A and 23B indicate that if a copper layer surface has a small grain size before electropolishing, the copper layer surface may have a smooth surface after electropolishing.
• Fig. 23C shows an atomic force microscope (AFM) image of the copper layer surface after electropolishing. Based on this AFM image, the mean roughness (R a ) of the copper layer surface is 3.6 nm, and the max height (R ma ⁇ ) of the copper layer surface is 30 nm.
• AFM atomic force microscope
• Fig. 24 is a graph showing the relationship between grain size and surface roughness of a copper layer surface after electropolishing for various chemicals included in an electrolyte fluid.
• the surface roughness after electropolishing increases as the grain size of the metal layer increases.
• a smaller grain size leads to a smoother and more planar copper layer surface topology after electropolishing.
• controlling and reducing the grain size may reduce the surface roughness of the copper layer, improve planarization, surface corrosion, and yield loss.
• additives may be included in the electrolyte fluid.
• Additives such as brightener, accelerator, suppressor, leveler, and the like, can be used alone or in combination during the plating process to control the grain structure and enhance the gap filling capability of a metal layer on a semiconductor structure.
• additives such as brightener, accelerator, leveler, and the like, can be added to a plating bath to control the grain size and grain structure.
• a ViaForm plating bath which is manufactured and commercially available from Enthone-OMI, can be used to obtain a smaller grain size, e.g., as grain size of less than a few hundred Angstroms.
• the ViaForm plating bath includes an accelerator, suppressor, and leveler.
• the accelerator has a concentration in the range of about 1.5 ml/liter to about 2.5 ml/liter, and preferably about 2 ml/liter.
• the suppressor has a concentration in the range of about 7 ml/liter to about 9 ml/liter, and preferably about 8 ml/liter.
• the leveler has a concentration in the range of about 1.25 ml/liter to about 1.75 ml/liter, and preferably about 1.5 ml/liter.
• FIGs. 25A-25D illustrate the change in a metal layer plated on a semiconductor wafer over a period of time.
• metal layer 2502 can have a microstructure with a small grain size on the order of a few nanometers.
• the grains in metal layer 2502 can grow to a size on the order of tens of nanometers.
• the grains in metal layer 2502 can continue to grow over time to a size on the order of hundreds of nanometers.
• the grains in metal layer 2502 can grow to a size on the order of a few microns.
• Fig. 26 is a graph showing the general relationship between the time after plating and the metal layer grain size. Shortly after plating a metal layer onto a semiconductor wafer or structure, the metal layer grain size can increase slowly from point A to B, where the grain size at point A is less than 100 Angstroms and at point B is less than 1000 Angstroms. Between points B and C, the metal layer grain size can increase more rapidly, where the grain size at point C is less than 10,000 Angstroms. Then, between points C and D, the metal layer can reach a saturated stage, in which the metal layer grain size generally increases more slowly if at all.
• the time between plating and electropolishing the metal layer to form a metal layer with reduced grain size is less than about 20 hours, and preferably less than about 5 hours.
• the time is preferably such that the grain size of the metal layer does not reach the micron, and more preferably the sub-micron size or less.
• Another exemplary process for control of metal layer grain size includes heating or annealing the metal layer after an electropolishing process.
• a metal layer may be plated, electropolished, and then annealed after the electropolishing process.
• the metal is heated for a period of time to allow grains within the microstructure of the metal layer to form new grains through a process typically called recrystallization.
• Thesb new grains can have different and relatively larger sizes from the grains in the microstructure before annealing that may increase the electrical characteristics of the metal.
• the metal layer may be chemical mechanically polished before the electropolishing process.
• Fig. 27 is a graph showing the relationship between grain growth rate and annealing temperature for copper plated onto seed layers of different thickness. Note that Fig.27 may depict the general relationship between grain size growth rate and annealing temperatures for other metals as well. Generally, the grain growth rate increases as the annealing temperature increases and the thickness of the thin film decreases. A seed layer thickness of less than 1,500A may be used, and preferably about 100A. Further, as the annealing temperature increases, the time for recrystallization of the copper microstructure decreases.
• the metal layer is electropolished before annealing. More particularly, the processes before electropolishing can be chosen to form small grain sizes in the metal layer in order to reduce surface roughness and increase planarity after electropolishing.
• the metal layer is then electropolished and thereafter the metal layer can be annealed using an appropriate annealing temperature, such as an annealing temperature between 100 °C and 300 °C, and preferably 150 °C, to form larger grain sizes within the metal layer.
• the metal layer may be annealed over a sufficient time period. These larger grain sizes can improve the electrical properties of the metal layer within vias, plugs, trenches, and the like, of the semiconductor device.
• the surface of the metal layer can remain smooth, while the electrical properties of the metal layer are improved.
• the metal layer may be heated to annealing temperatures by any suitable method such as an infrared source with a rapid thermal process, an oven, and the like.
• an exemplary method for reducing non-uniformity and recess in a metal trench or metal pad after an electropolishing process includes applying an alternating forward and reverse voltage pulse that may reduce the build-up of charge and improve copper recess uniformity and reduce the current loading effect.
• Fig. 28A illustrates an exemplary electropolishing apparatus, which has been previously disclosed in U.S. Patent No. 6,395,152, entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on July 9, 1999, the entire content of which is incorporated herein by reference, and in PCT Application No. PCT/US99/00964, entitled PLATING APPARATUS AND METHOD, filed on January 15, 1999, which is incorporated in its entirety by reference.
• wafer 2802 can be rotated around its center axis and may also be translated in the x-axis direction such that electrolyte fluid 2806 from nozzle 2810 can reach any location of the opposing major surface of wafer 2802.
• Nozzle 2810 can also be mobile and translate along the x-axis independent of wafer 2802.
• the trajectory of electrolyte fluid 2806 on wafer 2802 may be a spiral curve or other suitable trajectory to direct electrolyte fluid 2806 to desired portions of wafer 2802.
• Power supply 2812 can operate at a constant current DC, pulse or RF mode or constant voltage DC, pulse or RF mode to provide a potential difference between metal film 2804 and a nozzle electrode 2808 to electropolish a metal film or copper film 2804 on wafer 2802.
• Figs. 29A through 29D show the process of the stream of electrolyte fluid 2906 approaching die 2918 in more detail. If the power supply is running at a constant current, the current density will be low in Fig. 29A since the electrolyte column 2906 has not reached die 2918. During this portion the current is passed primarily through a barrier layer or the like formed on the wafer, which generally has a much lower conductivity than the metal layer.
• Figs. 30A-30D illustrate a cross-sectional view of the exemplary process.
• negative charge (electron) 3080 is built up on the interface between electrolyte fluid 3006 and barrier layer 3005 because barrier layer 3005 is difficult to polish.
• electrolyte fluid 3006 is adjacent copper trench 3020, the negative charge 3080 buildup on the surface of the electrolyte is discharged through trench 3020 thereby increasing the polishing rate of trench 3020, as shown in Fig. 30B.
• an exemplary electropolishing method is described using pulse or alternating current voltages to minimize the polishing rate differences over trenches and reduce or prevent copper recess.
• the relationship of polishing rate uniformity on trenches, pulse frequency, and nozzle tangential moving speed are varied to reduce copper recess in an electropolishing method.
• Fig. 31 shows an exemplary forward and reverse pulse waveform for an electropolishing method.
• the waveform region of A to B is the forward pulse
• waveform region of C to D is the reverse pulse.
• Vi is the forward pulse voltage and V is the reverse pulse voltage.
• t 0 is the pulse period, typically the time passed from A to E.
• the forward pulse width is ti and the reverse pulse width is t 2 .
• the duty cycle in percentage is t ⁇ /t 0 .
• Figs. 32 A - Fig. 32F illustrate an exemplary electropolishing method including the pulse waveform of Fig. 31.
• Fig. 32A shows electrolyte fluid 3206 approaching trench 3220 and as the pulse waveform is at point "A," and voltage Vj. As illustrated, the interface between electrolyte fluid 3206 and the surface of the wafer is filled with negative charge 3280.
• Fig. 32B illustrates the electrolyte fluid 3206 that has moved a distance Li to a location adjacent trench 3220, and pulse waveform is at point "B.” At this edge the pulse waveform moves to point "C," i.e. the reverse pulse region and voltage V 2 . The electrolyte interface at point C is charged by positive charge (ions) 3282, as shown in Fig. 32C. In this manner charge of electrolyte fluid 3206 is alternated at the interface between the relatively high conductive metal or copper layer in trench 3220 and the relatively low conductivity barrier layer 3205.
• Fig. 32F shows that as the pulse waveform moves to point "F," and the stream of electrolyte moves distance L 3 , the negative charge 3280 buildup on the interface of barrier and electrolyte will be discharged on the copper in trench 3220, which may cause a higher polishing rate.
• V is the tangential speed or velocity of nozzle relative to wafer surface
• tx is the forward pulse width (see Fig. 31).
• exemplary methods may include either reducing the duty cycle (t ⁇ /t 0 ) or increasing pulse frequency.
• the duty cycle can be in the range of 20% to 80%, preferably 50%.
• the frequency can be in the range of 100 kHz to 100 MHz, preferably 3 MHz.
• Velocity can be in the range of 100 mm/sec to 2000 mm/sec, preferably 500 mm/sec.
• a variety of pulse or alternative current/power supplies can be used in the exemplary methods, such as a RF power supply, triangle wave power supply, or any other type of power supply which can charge the interface between electrolyte 1008 and barrier to positive and negative side.

Landscapes

• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Metallurgy (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Organic Chemistry (AREA)
• Materials Engineering (AREA)
• Electrochemistry (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Crystallography & Structural Chemistry (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Electroplating Methods And Accessories (AREA)
• Electrodes Of Semiconductors (AREA)

Applications Claiming Priority (9)

Publications (2)

Family

ID=29255582

Family Applications (1)

Country Status (9)

Families Citing this family (32)

Citations (1)

Family Cites Families (16)

• 2003
  • 2003-04-11 CN CN038081660A patent/CN1685086B/zh not_active Expired - Fee Related
  • 2003-04-11 WO PCT/US2003/011417 patent/WO2003088316A2/en active Application Filing
  • 2003-04-11 AU AU2003226367A patent/AU2003226367A1/en not_active Abandoned
  • 2003-04-11 KR KR10-2004-7016217A patent/KR20040097337A/ko not_active Application Discontinuation
  • 2003-04-11 CA CA002479873A patent/CA2479873A1/en not_active Abandoned
  • 2003-04-11 EP EP03746750A patent/EP1495161A4/en not_active Withdrawn
  • 2003-04-11 TW TW092108452A patent/TWI267134B/zh active
  • 2003-04-11 US US10/510,656 patent/US20060049056A1/en not_active Abandoned
  • 2003-04-11 JP JP2003585151A patent/JP2005522587A/ja active Pending
• 2006
  • 2006-04-11 JP JP2006108820A patent/JP2006200043A/ja active Pending

Patent Citations (1)

Also Published As

Similar Documents

Legal Events