EP1456880A2 - Composant electronique et son procede de production - Google Patents

Composant electronique et son procede de production

Info

Publication number
EP1456880A2
EP1456880A2 EP02791626A EP02791626A EP1456880A2 EP 1456880 A2 EP1456880 A2 EP 1456880A2 EP 02791626 A EP02791626 A EP 02791626A EP 02791626 A EP02791626 A EP 02791626A EP 1456880 A2 EP1456880 A2 EP 1456880A2
Authority
EP
European Patent Office
Prior art keywords
plastic housing
layer
compound
printing
system carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02791626A
Other languages
German (de)
English (en)
Inventor
Martin Reiss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1456880A2 publication Critical patent/EP1456880A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to an electronic component with a semiconductor chip and a rewiring plate with a plastic housing and method for their production according to the type of the independent claims.
  • a plastic housing compound as is known from US Pat. No. 6,048,755.
  • the application of such a plastic housing compound is carried out, for example, by a high-pressure injection molding process, in which it is excluded by the high pressure that air bubbles can nestle in the plastic housing.
  • high pressure is not used, vacuum systems are required to print the plastic housing compound onto a system carrier, in which individual electronic components or a system carrier with several electronic components are printed with a plastic housing compound. In the case of vacuum printing, air inclusions are thus avoided, since the whole is carried out with the exclusion of air in a vacuum.
  • a vacuum printing system suitable for vacuum printing for enveloping a semiconductor chip or a plurality of semiconductor chips with a plastic housing compound is extremely costly and time-consuming since the entire printing system has to be accommodated in a vacuum unit and the printing process must take place in a vacuum chamber.
  • a high-pressure press system for applying a plastic housing high-pressure-resistant molded parts are again to be produced, some of which are Injection molding pressure of over 150 bar must withstand, which is also costly.
  • the object of the invention is to provide an electronic component and a method for its production, in which semiconductor chips with their rewiring plates can be packaged in a plastic housing compound without bubbles.
  • the electronic component has a plastic housing, which in turn has two plastic housing masses arranged one on top of the other.
  • One of these plastic housing compositions has a first layer which is uneven with respect to the outer sides of the plastic housing and which completely surrounds the edge regions of the semiconductor chip and partially covers the rear side of the semiconductor chip.
  • the electronic component has a second layer of plastic housing compound, which forms smooth upper sides for the outer sides of the plastic housing.
  • This two-layer plastic housing has the advantage that it can be manufactured using simple stencil printing technology under normal clean room conditions.
  • the first and the second layer made of a plastic housing composition differ in that after the first layer has been printed on, it has undergone a degassing step and is therefore virtually free of air bubbles.
  • the degassing process results in the surface of the first layer being uneven in relation to the outer sides of the plastic housing, since in the molten state the surface is sharp when printed Bubbles of edges and narrow gaps enclosed.
  • the unevenness of the surface of the first layer is not so great that a further degassing step would be required when printing the second layer from a plastic housing compound onto the first layer, so that the printed flat or smooth upper side as the outside of the second layer without degassing Plastic housing can be accepted.
  • Such a degassing system can comprise a vacuum chamber, from which only the air pressure can be pumped out, which can take place simultaneously for many components and also for several substrate carriers with several components. It has been found that the first layer of plastic housing compound can be degassed with a simple backing pressure of less than 50 mbar, so that the frequency and size of air bubbles in the first plastic layer despite the relatively steep edges on the edges of the individual semiconductor chips and despite in the column can be reduced between the semiconductor chips of a leadframe.
  • the first layer of plastic housing composition has an uneven surface with respect to the outer sides of the electronic component, this unevenness is compensated for by the second layer of plastic housing composition, so that only an uneven boundary phase between both plastic housing masses occurs within the plastic housing, but does not appear to the outside.
  • This uneven boundary phase therefore does not change the pleasing appearance of the electronic component and can only be demonstrated by means of corresponding sectional images in the plastic housing compound.
  • the first layer and the second layer are interlocked with one another via the uneven outer surface of the first layer, which forms an uneven boundary phase between the layers.
  • This interlocking can take place in that, after the first layer has been degassed, the second layer is applied to the first layer, which has not yet been completely crosslinked and cured. At the same time, it is thus possible for the crosslinking to take place beyond the border phase and thus to intensively anchor the two layers.
  • the electronic component has a bond channel opening in the rewiring plate.
  • This bond channel opening is filled with a plastic covering compound to protect bond connections.
  • This plastic masking compound can also be applied by stencil printing, which, however, is carried out separately from the manufacture of the housing on the underside of the electronic component, since the bonding channels are arranged in the rewiring plate on the side opposite the plastic housing, namely the active top side 27 of the semiconductor chip.
  • the semiconductor chips carried out in corresponding component positions.
  • the semiconductor chips are already attached to the system carrier via a double-adhesive film and in the All component connections have already been made in the bond channel of each component position.
  • the bond channel is already protected by a plastic cover.
  • the entire system carrier can then be covered with a plurality of semiconductor chips with a plastic housing compound on the rear sides of the semiconductor chips and at the same time the gaps between the semiconductor chips can be filled in as edge protection.
  • a first layer of viscous plastic housing compound is printed on the system carrier in order to fill up spaces between the semiconductor chips and to partially cover the rear sides of the semiconductor chips with the plastic housing compound. After this printing, a degassing process is carried out in that the system carrier with the first layer of plastic housing compound is stored in a vacuum chamber by pumping out the vacuum chamber.
  • a second layer of viscous plastic housing composition is printed onto the first layer of plastic housing composition.
  • the upper side of the first layer forms a relatively uneven outer surface 12, the second layer can nevertheless be applied to the rear sides of the semiconductor chips without inclusions of air bubbles and without degassing.
  • the first and second layers of viscous plastic housing compound are imprinted in an exemplary embodiment of the method using stencil printing technology.
  • stencil printing technique a stencil is placed over the system carrier and a caterpillar made of viscous plastic housing compound is spread over the opening with a spatula. pressed against the template.
  • a pressure is exerted on the spatula when the stencil is painted or squeegee, but this pressure does not correspond in any way to the high pressure during injection molding or is comparable with this in relation to the load on the system carrier.
  • the ventilation and pumping can preferably take place several times in succession during the storage of the first layer in the vacuum chamber before the second layer of plastic housing compound is printed on outside the vacuum chamber.
  • the method thus has the advantage that any desired number of prepared system carriers with first layers made of a plastic housing compound can be stored within the vacuum chamber, and thus a large number of electronic components can be outgassed with a first layer that is free of air bubbles. By venting the system several times, the degassed air can be rinsed off and pumped out several times.
  • the second layer of plastic housing composition is applied using the same printing stencil as the first layer of plastic housing composition. This means that the cost of stencils is extremely low and the reuse of the stencils for other system carriers for applying plastic housing compound to several electronic components is guaranteed.
  • a vacuum printer is required to create a plastic housing compound free of air bubbles on the electronic component. Furthermore, in contrast to vacuum printing, the time in which the vacuum is built up and broken down does not enter into the process time, that is to say the production time for units per hour is more favorable in the component and method according to the invention, namely by almost 50% than in the vacuum printer.
  • FIG. 1 shows a schematic cross section through an electronic component of a first embodiment of the invention
  • FIG. 2 shows a schematic diagram of a device for printing a viscous plastic housing compound between and on several semiconductor chips of a system carrier
  • FIG. 3 shows a flow diagram in four stages of a method for producing a plastic housing for the electronic component.
  • FIG. 1 shows a schematic cross section through an electronic component 1 of an embodiment of the invention.
  • the reference symbol 2 denotes the semiconductor chip.
  • the reference numeral 3 denotes a rewiring plate, the top surface 33 of which has a double-sided adhesive film 26 the active top 27 of the semiconductor chip 2 is connected.
  • the reference numeral 4 denotes a plastic housing, which is arranged on the upper side 33 of the rewiring plate three and envelops a rear side 10 and edge regions 8 and 9 of the semiconductor chip 2.
  • the rewiring plate 3 is constructed in multiple layers and has a solder stop layer 28 on its underside, which protects a structured metal layer 29 with rewiring lines 19.
  • the solder stop layer on the underside of the rewiring plate 3 leaves only external contact surfaces 30,. which solder balls 31 are arranged, free of the coating.
  • the rewiring plate 3 shown in FIG. 1 of an individual electronic component 1 is part of a system carrier 20 for several electronic components 1, which in turn has
  • the solder stop layer on the underside 21 of the system carrier 20 and the structured metal layer 29 are arranged on an insulating core plate 32 of the rewiring plate 3 or the system carrier 20.
  • this core plate also has a solder stop layer 28 on its upper side opposite the metal layer.
  • the effect of the different expansion coefficients between the solder stop layer 28 on the underside and the core plate 32 and the core plate 32 itself is compensated and compensated for.
  • the rewiring plate 3 or the system carrier 20 thus forms a laminate of four layers.
  • the symmetrical structure of a system carrier prevents it from being delivered warped or from subsequent process steps forming warps that result in unusable and non-functional electronic components 1.
  • the electronic component 1 has rows of solder balls 31.
  • a bond channel opening 14 is arranged in the center of the rewiring plate 3, which opens a bond channel 15 for attaching bond connections 16 between contact surfaces 34 on the top side 27 of the semiconductor chip and the rewiring lines 19 on the underside of the rewiring plate 3.
  • the sensitive bond connections 16 on the underside of the rewiring plate 3 and the upper side 27 of the semiconductor chip 2 are protected by filling with a plastic covering compound 17.
  • the rewiring plate 3 is connected to a larger system carrier 20 with several components 1.
  • This system carrier 20 has a plurality of component positions 18, in each of which a bond channel 15 and a semiconductor chip 2 are arranged.
  • the bond channels 15 of the system carrier 20 can be printed simultaneously and in parallel with a plastic covering compound 17 for all electronic components 1 after the bond connections 16 have been produced.
  • the top of the system carrier 20 and the back 10 of the semiconductor chips 2 can be printed with a plastic housing compound 23. If this printing is to be carried out without bubbles or with few air bubbles, vacuum printers or vacuum printing systems are used for this purpose.
  • the upper side of the system carrier 20 with the semiconductor chips 2 located thereon is printed with a plastic housing compound 23 by simple means by arranging a template over the system carrier 20 and one viscous bead made of plastic housing compound 23 is distributed with a spatula over the system carrier 20 and over the rear sides 10 of the semiconductor chips 2. Due to the viscous viscosity of the plastic housing compound 23 required for the application, this process cannot take place without bubbles.
  • the system carrier 20 and thus also the components 1 are printed in two steps with a plastic housing compound 23.
  • a first layer 5 is applied which, owing to the steep sections between the semiconductor chips 2, cannot be printed completely free of bubbles.
  • the system carrier 20 can be in a vacuum chamber. other system carriers are stacked and by repeatedly ventilating and pumping out the vacuum chamber, the plastic housing compound 23 of the first layer 5 is degassed and thus air bubbles are drawn out of the plastic housing compound 23. This creates a relatively uneven boundary phase on the first layer 5 of the plastic housing compound 23. This is identified by the reference symbol 13 in FIG. 1. After degassing, a second layer 6 is printed on this uneven boundary phase 13, and this multi-stage process can be used to ensure that a low-bubble plastic housing compound 23 now has the semiconductor chips 2 on it
  • FIG. 2 shows a schematic diagram of a device for printing on a viscous plastic housing compound 23 between and on a plurality of semiconductor chips 2 of a system carrier 20. Components with the same functions as in FIG. 1 are discussed with the same reference numerals and not separately.
  • the spatula 24 When printing the rear sides 10 of the semiconductor chips on the system carrier 20, the spatula 24 is first pressed onto the template 25 with a pressure force in direction A. For this purpose, it is held by the holder 35 and moved in direction B after a caterpillar made of plastic housing compound 23 has been built up in front of the spatula 24. When the spatula 24 is moved in the direction B, a rotating roller made of viscous plastic housing compound 23 forms, which rotates in the direction of the arrow C. This covers the rear sides 10 and the spaces 36 between the semiconductor chips 2. In particular, air bubble inclusions 22 are formed in the spaces 36.
  • the air bubble inclusions 22 are expelled from the first layer of plastic housing compound 23- by a degassing step.
  • the system carrier 20 is applied to the rear sides 10 of the semiconductor chips 2 after the application of the plastic housing composition 23 and the introduction of the plastic housing 23 in the spaces 36 between the semiconductor chips 2 lifted from the template 25 and placed in a vacuum chamber.
  • Air bubble inclusions 22 are expelled in the vacuum chamber, an uneven surface being formed.
  • This uneven surface is smoothed by printing the system carrier 20 once more with a plastic housing compound 23, as shown in FIG. 2.
  • the same stencil 25 can be used as for printing on the first layer. This creates a flat second layer of plastic housing compound 23, which already has no air bubble inclusions 22 because the critical gaps 36 are already filled with plastic housing compound 23 during the formation of the first layer.
  • FIG. 3 shows a flow diagram in four stages of a method for producing a plastic housing for the electronic component.
  • stage 1 the plastic housing composition is printed on the rear sides and in the spaces between the semiconductor chips of a system carrier.
  • the air bubble inclusions created in the first stage are placed in a vacuum chamber under one
  • the hardening can then begin or the hardening can be carried out at an elevated temperature.
  • the plastic housing compound crosslinks from the first and second layers to form a plastic housing packaging. Only after the curing stage, which is identified as stage 4 in FIG. 3, has been carried out, are solder balls arranged and soldered on the underside of the system carrier as external contacts. The system carrier can then be separated into individual electronic components according to the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Printing Methods (AREA)

Abstract

L'invention concerne un composant électronique (1) et son procédé de production. Ledit composant électronique (1) comporte une puce de semi-conducteur (2) et une plaque de modification de câblage (3), ainsi qu'un boîtier en matière plastique (4). Le boîtier en matière plastique (4) est divisé en deux parties en matière plastique (23) disposées l'une sur l'autre. Une de ces parties en matière plastique (23) est formée par une première couche (5) présentant une surface relativement inégale qui est apprêtée par une seconde couche (6) formant l'autre partie en matière plastique (23), de sorte que le composant électronique (1) est pourvu d'un boîtier en matière plastique (4) dont les faces extérieures sont lisses.
EP02791626A 2001-12-20 2002-12-11 Composant electronique et son procede de production Withdrawn EP1456880A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10163084A DE10163084A1 (de) 2001-12-20 2001-12-20 Elektronisches Bauteil und Verfahren zu seiner Herstellung
DE10163084 2001-12-20
PCT/DE2002/004529 WO2003054957A2 (fr) 2001-12-20 2002-12-11 Composant electronique et son procede de production

Publications (1)

Publication Number Publication Date
EP1456880A2 true EP1456880A2 (fr) 2004-09-15

Family

ID=7710250

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02791626A Withdrawn EP1456880A2 (fr) 2001-12-20 2002-12-11 Composant electronique et son procede de production

Country Status (4)

Country Link
US (1) US6998296B2 (fr)
EP (1) EP1456880A2 (fr)
DE (1) DE10163084A1 (fr)
WO (1) WO2003054957A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10163084A1 (de) 2001-12-20 2003-07-17 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung
JP2007123413A (ja) * 2005-10-26 2007-05-17 Elpida Memory Inc 半導体装置の製造方法
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
WO2013121866A1 (fr) * 2012-02-14 2013-08-22 株式会社村田製作所 Elément de composant électronique et module composé le comprenant
CN106206481A (zh) * 2016-05-05 2016-12-07 深圳信炜科技有限公司 生物识别模块及其制作方法、电子设备

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182837A (ja) * 1982-04-21 1983-10-25 Hitachi Ltd 樹脂封止半導体装置の製造方法
DE9314355U1 (de) * 1993-09-22 1994-01-20 ODS R. Oldenbourg Datensysteme GmbH, 81669 München Chipkarten-Modul und Chipkarte
JP2934174B2 (ja) 1995-08-29 1999-08-16 日本レック株式会社 電子部品の製造方法
US6962829B2 (en) * 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US6633611B2 (en) 1997-04-24 2003-10-14 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for region-based moving image encoding and decoding
JPH10303336A (ja) * 1997-04-30 1998-11-13 Nec Corp フリップチップ型半導体素子の樹脂封止構造
JP3453043B2 (ja) 1997-04-30 2003-10-06 東芝機械株式会社 旋回機構の数値制御装置
JP3351996B2 (ja) 1997-07-18 2002-12-03 松下電工株式会社 半導体装置の製造方法及び半導体装置
JP3180061B2 (ja) 1997-07-18 2001-06-25 松下電工株式会社 半導体装置の製造方法及び半導体装置
JP3145959B2 (ja) * 1997-07-18 2001-03-12 東レエンジニアリング株式会社 電子部品の樹脂封止方法
JP3163419B2 (ja) * 1997-08-22 2001-05-08 日本レック株式会社 電子部品の製造方法
JPH11102985A (ja) * 1997-09-26 1999-04-13 Mitsubishi Electric Corp 半導体集積回路装置
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
TW434850B (en) * 1998-12-31 2001-05-16 World Wiser Electronics Inc Packaging equipment and method for integrated circuit
TW502422B (en) * 2001-06-07 2002-09-11 Ultra Tera Corp Method for encapsulating thin flip-chip-type semiconductor device
DE10163084A1 (de) 2001-12-20 2003-07-17 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu seiner Herstellung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03054957A2 *

Also Published As

Publication number Publication date
US20040262780A1 (en) 2004-12-30
US6998296B2 (en) 2006-02-14
WO2003054957A3 (fr) 2003-09-25
WO2003054957A2 (fr) 2003-07-03
DE10163084A1 (de) 2003-07-17

Similar Documents

Publication Publication Date Title
EP0709805B1 (fr) Méthode de fabrication de porteurs d'informations incorporant des éléments et dispositif de mise en oeuvre de la méthode
DE29502080U1 (de) Vorrichtung zur Herstellung von Ausweiskarten und danach hergestellte Ausweiskarte
DE69300506T2 (de) Herstellungsverfahren von mehrlagigen keramischen Substraten.
DE69535481T2 (de) Karte mit mindestens einem elektronischen element
DE69209482T2 (de) Elektronikverpackung mit erhöhter Wärmeableitung und Verfahren zu ihrer Herstellung
DE60112133T3 (de) Neue, besonders leicht anzubringende klebefolie und deren herstellverfahren
DE102013103580A1 (de) Dreidimensional gestapelte Gehäuseanordnung und Verfahren zum Herstellen derselben
DE2453788A1 (de) Verfahren zur herstellung von schaltplatten mit gedruckten schaltungen
DE10156386A1 (de) Verfahren zum Herstellen eines Halbleiterchips
DE10127009A1 (de) Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform
DE19716912B4 (de) Verfahren zur Fixierung eines Chipmoduls in einer Chipkarte
DE4341867A1 (de) Verfahren zum Drucken eines Verbindungsmittels
DE102015100919A1 (de) Folienverbund mit elektrischer Funktionalität und Kontaktierung zum Kontaktieren eines elektrischen Leiters
CH646280A5 (de) Verfahren zur herstellung von verbindungszwischenstuecken.
EP1456880A2 (fr) Composant electronique et son procede de production
DE19627543B4 (de) Multi-Layer-Substrat sowie Verfahren zu seiner Herstellung
DE69930946T2 (de) Thermokopf, thermokopfeinheit und herstellungsverfahren dafür
DE69414846T2 (de) Methode zur elektrische Isolation von Kühlkörpern in elektronischen Leistungsschaltungen
DE102019216954A1 (de) Leiterplatten-Herstellungsverfahren
DE102004046629B4 (de) Verfahren zum Herstellen eines Bauelementes mit einem gedruckten Schaltkreis
EP0955160A2 (fr) Procédé pour la fabrication d'un manchon en particulier pour l'industrie de l'imprimerie
DE19645069C2 (de) Verfahren und Vorrichtung zur Herstellung von Chipkarten, ID-Karten oder dergleichen
DE102016220678A1 (de) Druckvorrichtung und Druckverfahren zum Auftragen eines viskosen oder pastösen Materials
DE2922304A1 (de) Verfahren zur herstellung gedruckter schaltungen, sowie dafuer verwendete leitende farbe und vorrichtung
DE112004000956B4 (de) Verfahren zur Ausbildung einer Verbindung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040526

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

RTI1 Title (correction)

Free format text: METHOD FOR PRODUCING AN ELECTRONIC COMPONENT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090701