Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/356104—Bistable circuits using complementary field-effect transistors
  • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
  • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
  • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
  • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
  • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Definitions

• the invention relates to a comparator with a reference voltage input and a difference voltage input together with an inverting output and a non-inverting output, wherein a switching threshold of the comparator may be predetermined by an upper threshold voltage and a lower threshold voltage with regard to the reference voltage.
• Comparators of the generic type are known. These act as difference voltage transformers and are known to be used to convert analog voltage signals into digital signals. Depending on the level of an input voltage superimposed over the reference voltage, the comparator switches at the output to a HIGH voltage level or a LOW voltage level. The reference voltage determines a threshold voltage, the output state being assumed to be HIGH when this is exceeded and LOW when it is fallen short of.
• the comparator To increase switching accuracy of the comparator, it is known to set an upper threshold voltage and a lower threshold voltage for the reference voltage (threshold voltage). The difference between the upper threshold voltage and the lower threshold voltage provides comparator hysteresis. The upper threshold voltage and the lower threshold voltage result in the fact that switching into the HIGH state requires the upper threshold voltage to be exceeded and switching into the LOW state requires the lower threshold voltage to be fallen short of. This hysteresis determined by the upper and lower threshold voltages ensures that the interference signal superimposed over the input signals does not have any effect on the switching state of the comparator.
• Comparators provided with hysteresis are known for example from US-PS 5,617,050, US-PS 5,798,663, US-PS 5,610,545, US-PS 5,528,185 and US-PS 6,166,566.
• Li these known comparators in each case a constant upper threshold voltage and a constant lower threshold voltage are set, i.e. the difference between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage is identical. It is an object of the invention to provide a comparator of the generic type which provides in a simple manner flexible adaptation to various applications.
• a comparator having the features of claim 1. Because the upper threshold voltage and the lower threshold voltage may be set independently of one another, it is advantageously possible to set the difference between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage to be asymmetric. In a preferred development of the invention, it is possible in particular to select the upper threshold voltage or the lower threshold voltage to be identical to the reference voltage and to design hysteresis thus only for the lower threshold voltage or for the upper threshold voltage.
• the channel widths of the p-channel transistors may be adjusted by a "metal-programmable" width or an "electrically programmable” width.
• the upper threshold voltage and/or the lower threshold voltage may be simply set independently of one another using methods known per se.
• Fig. 1 is a block diagram of a programmable comparator
• Figs. 2 and 3 show possible characteristic curves for the asymmetric comparator
• Fig. 4 shows a first example of embodiment of a comparator according to the invention
• Fig. 5 shows a second example of embodiment of a comparator according to the invention
• Fig. 6 shows a third example of embodiment of a comparator according to the invention.
• Fig. 1 is a block diagram of a comparator 100.
• a reference voltage NJREF is present at an input I ⁇ .
• a voltage is applied to another input I ⁇ P which results from superimposition of the reference voltage N_REF and a differential input voltage N_ T ⁇ .
• the reference voltage V_REF is constant, such that a HIGH voltage signal is obtained at an output OUTP if the differential input voltage N_IN is positive and a LOW voltage signal is obtained at the output OUTP if the differential input voltage N_ESf is negative.
• the respectively inverted signals are applied to the output OUT ⁇ .
• the structure and mode of operation of such comparators 100 are known, such that these will not be explained in any more detail in the context of the description.
• a first coupling element 12 is connected between the input I ⁇ P and the output
• the coupling elements 12 and 14 serve, in a manner still to be explained, in programming the hysteresis of the comparator 100.
• the coupling element 12 serves in setting an upper threshold voltage and the coupling element 14 in setting a lower threshold voltage of the comparator 100.
• the difference between upper threshold voltage and lower threshold voltage corresponds to the hysteresis of the comparator 100.
• the upper threshold voltage may be greater than/equal to the reference voltage N_REF and the lower threshold voltage may be lower than/equal to the reference voltage NJREF.
• the operation of two embodiments of the comparator 100 is clear from the characteristic curves illustrated in Figs. 2 and 3.
• the differential input voltage N_I ⁇ together with the HIGH voltage signal and LOW voltage signal present at the output OUTP are shown therein over the time t.
• the reference voltage NJREF together with the upper threshold voltage N_SO and the lower threshold voltage N_SU are constant over time.
• the difference N_SO - N_SU corresponds to the hysteresis 16.
• the differential input voltage N_DST is smaller than the upper threshold voltage N_SO in the period to to t 1 ⁇ such that the LOW voltage signal is present at the output OUTP.
• the differential input voltage N_I ⁇ rises above the upper threshold voltage V_SO, such that the comparator 100 switches to the HIGH voltage signal at the output OUTP.
• the comparator switches back to the LOW voltage signal at the output OUTP.
• the hysteresis 16 is symmetric, i.e. the difference between upper threshold voltage N_SO and reference voltage N_REF matches the difference between the reference voltage N_REF and the lower threshold voltage N_SU.
• an asymmetric hysteresis 16 of the comparator 100 is programmed.
• the upper threshold voltage NJSO here corresponds to the reference voltage NJREF, such that the hysteresis 16 corresponds to the difference between the reference voltage N_REF or upper threshold voltage N_SO and the lower threshold voltage N_SU.
• the output OUTP or OUT ⁇ is accordingly switched into the signal states HIGH or LOW in the event respectively of the upper threshold voltage NJSO being exceeded or the lower threshold voltage N_SU being fallen short of.
• asymmetric hystereses 16 of the comparator 100 may also be programmed.
• the lower threshold voltage N_SU may coincide with the reference voltage NJREF, while the upper threshold voltage NJSO is greater than the reference voltage N_REF.
• the comparator 100 may be designed with different voltage differences between the upper threshold voltage NJSO and the reference voltage NJREF and the reference voltage NJREF and the lower threshold voltage N_SU.
• the nub of the invention is to design the comparator 100 and its coupling elements 12 and 14 in such a way that the hysteresis 16 may be freely programmed, in particular asymmetrically programmed, i.e. the upper threshold voltage NJSO and the lower threshold voltage N_SU may be set independently of one another.
• Fig. 4, 5 and 6 show various circuit arrangements for the comparator 100, which allow mutually independent setting of the upper threshold voltage NJSO and the lower threshold voltage N_SU. It is clear from the circuit arrangement 10 shown in Fig. 4 that it is possible to go beyond a generally known standard construction of the comparator 100 with the n-channel transistors Ml and M4 and the p-channel transistors M2 and M5 by additionally connecting p-channel transistors M3 and M6.
• the p-channel transistor M6 constitutes the coupling element 12 and the p-channel transistor M3 the coupling element 14 (Fig. 1).
• All the p-channel transistors M2, M3, M5 and M6 have the same channel length LP and all the n-channel transistors Ml and M4 have the same channel length LN.
• the width ratios k3 or k6 the size of the hysteresis 16 and the position of the upper threshold voltage NJSO or of the lower threshold voltage NJSU respectively may be adjusted independently of one another relative to the reference voltage N_REF. If the comparator 100 is to be operated with hysteresis 16, the upper threshold voltage NJSO is obtained as follows: f 2*LN*I_BIAS ⁇ sqrt(k6) - 1
• the difference NJSO - NJSU may be determined for the hysteresis 16, wherein the following applies: f2*L ⁇ *I BIASV f sqrt(k6) -l l-sqrt(k3) ⁇
• comparators 100 with a hysteresis 16 or without hysteresis 16 may be obtained as a function of the width ratios k3 and k6.
• the width ratios k3 > 1 and k6 > 1 the upper threshold voltage NJSO and the lower threshold voltage NJSU may be adjusted independently of one another. If the width ratios k3 and k6 are of equal size, a comparator 100 is obtained with symmetric hysteresis 16. If the width ratios k3 and k6 are different, an asymmetric hysteresis 16 is obtained with regard to the reference voltage NJREF.
• Adjustment of the width ratios k3 and k6 for programming the hysteresis 16 may be achieved in various possible ways. On the one hand, there is the possibility of providing, on integration of the circuit arrangement 10, a fixed channel width W3 for the transistor M3 and a fixed channel width W6 for the transistor M6.
• a metal mask of the transistors M3 and M6 after integration thereof into the circuit arrangement 10, the latter may be adapted subsequently to a desired hysteresis 16.
• a "metal-programmable" channel width may be set for the transistors M3 and M6.
• the hysteresis 16 may be dynamically adapted to various instances of application of the comparator 100.
• This "electrically programmable" channel width may thus be set for the transistors M3 and M6. Both the setting of metal-programmable and of electrically programmable channel widths are generally known, such that they will not be explained in any more detail in the context of the present description.
• Fig. 5 shows a modified embodiment of the circuit arrangement 10 according to Fig. 4.
• the voltage level at the output OUTP or at the inverting output OUTN in the HIGH state may assume the value of the supply voltage NDD.
• the voltage potential 0 Nolt cannot be achieved. This may be desirable in the case of various application options for the comparator 100, in particular with subsequent digital circuits.
• Fig. 6 shows a further embodiment of the circuit arrangement 10, in which the p-channel transistors M3 and M6 are each subdivided into parallel-connected p- channel transistors M3 ⁇ and M3 2 and M6 ⁇ and M6 2 respectively.
• the p-channel transistor M3 2 may be connected via a switching means S3 to the supply voltage NDD and the p- channel transistor M6 2 via a switching means S6 to the supply voltage NDD.
• S3 the switching means S3 to the supply voltage NDD
• S6 switching means
• This programming could be refined by subdividing the p-channel transistors M3 or M6 into more than two parallel-connected p- channel transistors, of which at least two would be connected to the supply voltage NDD via corresponding switching means S.
• various setting options for the hysteresis 16 are then obtained, which, as explained, may also be asymmetric. LIST OF REFERENCE NUMERALS

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• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Manipulation Of Pulses (AREA)
• Measurement Of Current Or Voltage (AREA)

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  • 2001-09-15 DE DE2001145656 patent/DE10145656A1/de not_active Withdrawn
• 2002
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