EP1390986A2 - Condensateur accordable integre - Google Patents

Condensateur accordable integre

Info

Publication number
EP1390986A2
EP1390986A2 EP02748561A EP02748561A EP1390986A2 EP 1390986 A2 EP1390986 A2 EP 1390986A2 EP 02748561 A EP02748561 A EP 02748561A EP 02748561 A EP02748561 A EP 02748561A EP 1390986 A2 EP1390986 A2 EP 1390986A2
Authority
EP
European Patent Office
Prior art keywords
region
insulating
connection
capacitance
trough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02748561A
Other languages
German (de)
English (en)
Inventor
Judith Maget
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1390986A2 publication Critical patent/EP1390986A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0808—Varactor diodes

Definitions

  • N 0 rö X -H ⁇ ⁇ 4J -H rö ⁇ CQ -HU OJ C ⁇ Q) CD ß ß CQ ß 4- ) CD ß 4-> M XI rö s rH xi rH XI -H rH N ⁇ .
  • Integrated, tunable capacities can be manufactured in different technologies and with different structures. For example:
  • Capacitance diodes designed as tunable capacitors, which can be integrated either as single-ended or as differentially configured components, compare, for example, A.-S. Porret, T. Melly, C. C. Enz, E. A. Vittoz "Design of High-Q varactors for Low-Power ireless Applications Using a Standard CMOS Process", IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, March 2000, pp. 337-345.
  • the tunable capacitances can also be designed as NMOS or PMOS field effect transistors with short-circuited source / drain regions, for example in N wells, see for example P. Andreani, S. Mattisson, "On the Use of MOS Varactors in RF VCO's ", IEEE Journal of Solid State Circuits, Vol. 35, No. 6, June 2000, pp. 905-910.
  • the total effective capacity of such a component depends on its particular operating state, such as inversion, depletion or accumulation or enrichment, and is determined by the voltages at the nodes mentioned.
  • the generally constant, parasitic capacitances of such a component are generally always additive.
  • the maximum achievable capacitance results as the sum of gate oxide capacitance, determined by the gate area and thickness of the gate oxide layer, and from the constant, parasitic capacitances between the gate and the source / drain regions.
  • the minimum achievable capacitance results in depletion as a series connection of the gate oxide capacitance and the depletion or depletion Capacitance and in parallel the constant, parasitic capacitances between the gate and the source / drain regions.
  • the object of the present invention is to provide an integrated, tunable capacitance which has a large tuning range and in which the quality is improved.
  • the object is achieved with an integrated, tunable capacity
  • a gate electrode which is arranged on the second insulating region and at least one well connection region for connecting the semiconductor region to a control voltage for tuning the capacitance, which has a higher dopant concentration than the semiconductor region and which has a second layer thickness greater than the first layer thickness Has.
  • the highly doped trough connection areas which extend to a relatively large depth in the semiconductor material, bring about a low series resistance of the integrated, tunable capacitance with a high variation ratio, that is to say with relatively large quotients of the maximum and minimum adjustable capacitance of the tunable capacitance.
  • the highly doped trough connection regions serve to connect the varactor according to the invention to a connection for supplying a tuning voltage for adjusting the capacitance of the varactor, while the gate electrode is preferably designed as a high-frequency connection.
  • the semiconductor body can have a substrate connection which can be connected to a reference potential connection or a means for supplying a bias voltage.
  • the series resistances of the varactor can be reduced further. There- In the case of, however, care must be taken to ensure that the extension of the trough connection region under the first insulating region does not extend below the second insulating region, which is preferably designed as a gate oxide region.
  • the well connection regions described with a high dopant concentration, which extend into the semiconductor body to a great depth, can be implemented, for example, in a BiCMOS production technology as so-called collector deep implantations instead of the source / drain regions usually provided for CMOS varactors.
  • the integrated, tunable capacitance is preferably of symmetrical design, that is to say with two first insulating regions each with two adjacent trough connection regions, each of which extends to a greater depth than the first insulating regions.
  • the first insulating regions border on the second insulating region and surround the trough-shaped semiconductor region of the first conductivity type.
  • the well connection regions according to the present principle are distinguished in that they reach a significantly greater depth of the doping regions in relation to source / drain regions.
  • a buried layer of the first conductivity type with the higher dopant concentration adjoins the at least one well connection region.
  • the quality of the tunable capacitance is further improved, since the series resistances are further reduced.
  • a still further improvement in the quality of the arrangement can be achieved in that the buried layer is arranged immediately below the at least one first insulating region.
  • the tuning range would be reduced by a buried layer directly below the first insulating layer.
  • the buried layer advantageously begins directly (in the vertical direction) adjacent to the maximally extended space charge zone. In any case, however, they preferably border on the tub connection areas, so they are not lower.
  • the trough-shaped semiconductor region below the gate electrode is enclosed by trough connection regions and the buried layer in cross section.
  • the at least one tub connection area is formed using bipolar manufacturing technology.
  • the trough connection areas can be designed, for example, as deep collector implants, produced in bipolar process step steps of a BiCMOS production.
  • the at least one well connection region has a common interface with the second insulating region and the semiconductor region under the gate electrode.
  • the tunable capacitance is preferably formed in a so-called finger structure with a plurality of gate electrode tracks running in parallel.
  • an area for connection to reference potential is provided which is of a second conductivity type and is highly doped and has a common interface with the second insulating area and the semiconductor area under the gate electrode.
  • the described direct connection also takes on reference potential with respect to the whole , of the tunable capacity occupied by the chip area takes up a small area or takes place only in relatively few places in the semiconductor.
  • the second insulating area has a third Layer thickness that is significantly smaller than the first layer thickness of the first insulating region.
  • the second insulating region is preferably formed as a so-called gate oxide layer in a CMOS manufacturing step.
  • the first insulating regions are preferably designed as so-called thick oxide regions, for example as a so-called shallow trench insulation, STI, in order to achieve an improved variation ratio.
  • FIG. 1 shows a cross section through an exemplary embodiment of a basic arrangement of a tunable capacitance according to the invention
  • FIG. 2 shows a cross section through an object developed with respect to FIG. 1 with a direct connection of the trough-shaped semiconductor region along the gate oxide to a trough connection region
  • FIG. 3 shows a schematic plan view of an object with cross sections according to FIGS. 1 and 2,
  • FIG. 4 shows a cross section through an object developed with respect to FIG. 1 with a direct connection to reference potential
  • FIG. 5 shows a schematic top view of a capacitance with a cross section according to FIG. 4,
  • FIG. 6 is a graph showing the quality of an exemplary capacitance according to the invention as a function of 4-> xi J
  • the buried layer 7 runs parallel to the gate oxide layer 4 along the active front side of the semiconductor body 1.
  • both the desired and the parasitic electrical replacement elements are shown in FIG. 1, which on the one hand show the series resistance of the varactor and on the other hand the ratio of the variable capacitance to the parasitic capacitances and thus that Determine the variation ratio of the capacity.
  • the variation ratio is defined as the quotient of the maximum and minimum adjustable capacitance value.
  • CHH denotes the adjustable space charge capacity
  • C ox the gate oxide capacity
  • C r edge capacities the overlap capacity.
  • the resistors Rg and R ⁇ _ to R4 determine the series resistance of the varactor which, together with the capacities, determines the quality of the varactor.
  • the quality is improved in that the resistors R3 and R are significantly reduced compared to a CMOS varactor due to the highly doped collector deep implantation regions 6.
  • the resistances R2 can be reduced in particular.
  • T Ai ⁇ 3 rH XI 4-1 J rö rö Cn 03 4-1 rH rö rö ß 4-1 u 4J CQ ⁇ rö -H ß 4-JH ⁇ TJ rö rH ⁇ CQ 4-> a rö ß ß CN ß TJ XI ⁇ ⁇ ⁇ -H ⁇ -H ⁇ rH Di - ß X rö -H ß rö Dl rö ⁇ ⁇ ⁇ rö ⁇ ß
  • P-doped area is to be used as trough-shaped area 2
  • the deep collector implantation areas and the buried layer are to be P + doped.
  • the described direct connections are then also to be provided with the opposite conductivity type with respect to the exemplary embodiments shown.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un condensateur accordable intégré dont le facteur de qualité est amélioré par le fait que les zones source/grille sont remplacées par des zones de connexion fortement dopées (6) de grande profondeur, conçues par exemple sous forme de zones d'implantation profondes de collecteur. Ainsi, la résistance sérielle du condensateur accordable peut être réduite. Le condensateur accordable intégré selon l'invention peut par exemple être employé dans des circuits oscillateurs intégrés commandés en tension devant présenter un facteur de qualité élevé.
EP02748561A 2001-05-29 2002-05-29 Condensateur accordable integre Withdrawn EP1390986A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10126116A DE10126116A1 (de) 2001-05-29 2001-05-29 Integrierte, abstimmbare Kapazität
DE10126116 2001-05-29
PCT/DE2002/001993 WO2002097899A2 (fr) 2001-05-29 2002-05-29 Condensateur accordable integre

Publications (1)

Publication Number Publication Date
EP1390986A2 true EP1390986A2 (fr) 2004-02-25

Family

ID=7686504

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02748561A Withdrawn EP1390986A2 (fr) 2001-05-29 2002-05-29 Condensateur accordable integre

Country Status (5)

Country Link
US (1) US6906904B2 (fr)
EP (1) EP1390986A2 (fr)
JP (1) JP4191028B2 (fr)
DE (1) DE10126116A1 (fr)
WO (1) WO2002097899A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879003B1 (en) * 2004-06-18 2005-04-12 United Microelectronics Corp. Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof
US7619273B2 (en) * 2004-10-06 2009-11-17 Freescale Semiconductor, Inc. Varactor
KR101146224B1 (ko) * 2005-11-16 2012-05-15 매그나칩 반도체 유한회사 Ｍｏｓ 바랙터 및 그를 포함하는 전압 제어 발진기
US20090102341A1 (en) * 2007-10-23 2009-04-23 Slam Brands, Inc. Cable management apparatus, system, and furniture structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03147376A (ja) * 1989-11-02 1991-06-24 Nissan Motor Co Ltd 可変容量素子
US5894163A (en) * 1996-04-02 1999-04-13 Motorola, Inc. Device and method for multiplying capacitance
US5965912A (en) * 1997-09-03 1999-10-12 Motorola, Inc. Variable capacitor and method for fabricating the same
US6034388A (en) * 1998-05-15 2000-03-07 International Business Machines Corporation Depleted polysilicon circuit element and method for producing the same
US6172378B1 (en) * 1999-05-03 2001-01-09 Silicon Wave, Inc. Integrated circuit varactor having a wide capacitance range

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02097899A2 *

Also Published As

Publication number Publication date
DE10126116A1 (de) 2002-08-22
JP4191028B2 (ja) 2008-12-03
US6906904B2 (en) 2005-06-14
US20040094824A1 (en) 2004-05-20
WO2002097899A3 (fr) 2003-03-13
WO2002097899A2 (fr) 2002-12-05
JP2004530305A (ja) 2004-09-30

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