EP1390986A2

EP1390986A2 - Integrated tunable capacitor

Info

Publication number: EP1390986A2
Application number: EP02748561A
Authority: EP
Inventors: Judith Maget
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-05-29
Filing date: 2002-05-29
Publication date: 2004-02-25
Also published as: WO2002097899A3; WO2002097899A2; JP4191028B2; US6906904B2; JP2004530305A; DE10126116A1; US20040094824A1

Abstract

The invention relates to an integrated tunable capacitor in which the quality is improved by virtue of the fact that, in lieu of source/drain regions, highly doped trough connection regions (6) of a large depth are provided that are configured, for example, as collector deep implantation regions. This results in reducing the series resistance of the tunable capacitor. The integrated tunable capacitor can be used, for example, in integrated voltage-controlled oscillator circuits in which a high quality is demanded.

Description

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to strive for quality, to make the series resistance to capacity as small as possible.

Integrated, tunable capacities can be manufactured in different technologies and with different structures. For example:

Capacitance diodes designed as tunable capacitors, which can be integrated either as single-ended or as differentially configured components, compare, for example, A.-S. Porret, T. Melly, C. C. Enz, E. A. Vittoz "Design of High-Q varactors for Low-Power ireless Applications Using a Standard CMOS Process", IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, March 2000, pp. 337-345.

Furthermore, the tunable capacitances can also be designed as NMOS or PMOS field effect transistors with short-circuited source / drain regions, for example in N wells, see for example P. Andreani, S. Mattisson, "On the Use of MOS Varactors in RF VCO's ", IEEE Journal of Solid State Circuits, Vol. 35, No. 6, June 2000, pp. 905-910.

From the publication by M. Tiebout, "A Fully Integrated 1.3 GHz VCO for GSM in 0.25 μm Standard CMOS with aphaseoise of -142 dBc / Hz at 3 MHz Offset", European Microwave Week 2000, there is also a VCO with NMOS varactors known.

A differentially working PMOS-FET, an NMOS-FET in an n-antenna and an NMOS-FET in an n-antenna without connected diffusion regions are known from the above-mentioned literature reference Porret et al.

An NMOS field effect transistor formed in an n-well with p + extraction areas is described in the publication F. Svelto et al: "A Three Terminal Varactor for RFIC's in Standard CMOS Technology", IEEE Transactions on Electron Devices, Volume 47, No. 4, April 2000, pages 893-895. In the article by JN Burghartz, M. Soyuer and KA Jenkins with the title "Integrated RF and Microwave Components in BiCMOS Technology", IEEE Transactions on Electron Devices, Vol. 43, No. 9, September 1996, PN diodes are produced in bipolar manufacturing technology, which work as basic collector diodes.

Finally, in the essay by Wallace Ming Yip Wong et al. "A Wide Tuning Range Gated Varactor", IEEE Journal of Solid State Circuits, vol. 35, no. 5, May 2000, pp. 773-779 a so-called gated varactor.

Of the above-mentioned solutions for providing a tunable capacitance, those which have been formed as a gated varactor and as an NMOS field-effect transistor in an n-well with p + extraction areas are those with the largest possible tuning range to date. The high-frequency signal is usually applied to the gate connection and a second connection is used to supply the tuning voltage, depending on the version.

The total effective capacity of such a component depends on its particular operating state, such as inversion, depletion or accumulation or enrichment, and is determined by the voltages at the nodes mentioned. The generally constant, parasitic capacitances of such a component are generally always additive.

In inversion, as well as in accumulation, the maximum achievable capacitance results as the sum of gate oxide capacitance, determined by the gate area and thickness of the gate oxide layer, and from the constant, parasitic capacitances between the gate and the source / drain regions. The minimum achievable capacitance, on the other hand, results in depletion as a series connection of the gate oxide capacitance and the depletion or depletion Capacitance and in parallel the constant, parasitic capacitances between the gate and the source / drain regions. With a given gate area and given technology which determines the gate oxide layer thickness, the tuning range can therefore only be increased by reducing the minimum capacitance and / or the constant capacitances.

In order to obtain acceptable phase noise of the VCO when using the tunable capacitance in an LC-VCO, for example, it is desirable to keep series resistances in the LC circuit low, as explained above.

As is customary with high-frequency transistors, so-called finger structures and transistors with a short gate length are used for this. In contrast, the parasitic capacitances are largely independent of the gate length. Only the variable part of the capacities decreases with the gate length. The smaller the gate length, the greater the parasitic capacitances compared to the variable capacitances. To achieve higher grades, it has therefore been necessary to accept a smaller tuning range. The reverse also applies: the larger the gate length, the less the parasitic capacitances are important and therefore a larger tuning range can be achieved. However, a larger gate length leads to increasing series resistances and thus to poorer quality.

The object of the present invention is to provide an integrated, tunable capacitance which has a large tuning range and in which the quality is improved.

According to the invention the object is achieved with an integrated, tunable capacity

a semiconductor body with a trough-shaped semiconductor region of a first conductivity type, the semiconductor body being of a second conductivity type, - At least a first insulating region, which is introduced into the semiconductor body, has a common interface with the trough-shaped semiconductor region and a first layer thickness, - A second insulating region, which has a common interface with the semiconductor region and a common interface with the first insulating region Has,

a gate electrode which is arranged on the second insulating region and at least one well connection region for connecting the semiconductor region to a control voltage for tuning the capacitance, which has a higher dopant concentration than the semiconductor region and which has a second layer thickness greater than the first layer thickness Has.

The highly doped trough connection areas, which extend to a relatively large depth in the semiconductor material, bring about a low series resistance of the integrated, tunable capacitance with a high variation ratio, that is to say with relatively large quotients of the maximum and minimum adjustable capacitance of the tunable capacitance.

The highly doped trough connection regions serve to connect the varactor according to the invention to a connection for supplying a tuning voltage for adjusting the capacitance of the varactor, while the gate electrode is preferably designed as a high-frequency connection.

The semiconductor body can have a substrate connection which can be connected to a reference potential connection or a means for supplying a bias voltage.

Due to the lateral expansion of the trough connection regions in a direction parallel to the active front side of the semiconductor body under the first insulating region, the series resistances of the varactor can be reduced further. There- In the case of, however, care must be taken to ensure that the extension of the trough connection region under the first insulating region does not extend below the second insulating region, which is preferably designed as a gate oxide region.

The well connection regions described with a high dopant concentration, which extend into the semiconductor body to a great depth, can be implemented, for example, in a BiCMOS production technology as so-called collector deep implantations instead of the source / drain regions usually provided for CMOS varactors.

The integrated, tunable capacitance is preferably of symmetrical design, that is to say with two first insulating regions each with two adjacent trough connection regions, each of which extends to a greater depth than the first insulating regions. The first insulating regions border on the second insulating region and surround the trough-shaped semiconductor region of the first conductivity type.

The well connection regions according to the present principle are distinguished in that they reach a significantly greater depth of the doping regions in relation to source / drain regions.

In a preferred embodiment of the present invention, a buried layer of the first conductivity type with the higher dopant concentration adjoins the at least one well connection region.

With a buried layer, a so-called buried layer, below the trough-shaped semiconductor region and adjacent to the at least one trough connection region, the quality of the tunable capacitance is further improved, since the series resistances are further reduced. A still further improvement in the quality of the arrangement can be achieved in that the buried layer is arranged immediately below the at least one first insulating region. However, if the doping ratios are such that the maximum space charge zone is deeper than the first insulating layer without the buried layer, the tuning range would be reduced by a buried layer directly below the first insulating layer. If the tuning range is not to be reduced by the buried layer with somewhat less improved quality, the buried layer advantageously begins directly (in the vertical direction) adjacent to the maximally extended space charge zone. In any case, however, they preferably border on the tub connection areas, so they are not lower.

With a symmetrical design of the tunable capacitance, the trough-shaped semiconductor region below the gate electrode is enclosed by trough connection regions and the buried layer in cross section.

In a further preferred embodiment of the present invention, the at least one tub connection area is formed using bipolar manufacturing technology.

The trough connection areas can be designed, for example, as deep collector implants, produced in bipolar process step steps of a BiCMOS production.

In a further preferred embodiment of the present invention, the at least one well connection region has a common interface with the second insulating region and the semiconductor region under the gate electrode.

With such a direct connection of the trough connection regions to the second insulating region and the semiconductor region directly below, a further improvement in the quality is achieved. enough. However, if one looks at the total chip area occupied by the tunable capacity, the described direct connection takes up only a relatively small area in order to avoid an undesired increase in the para-capacitance.

As is customary with field effect transistors for high-frequency applications, the tunable capacitance is preferably formed in a so-called finger structure with a plurality of gate electrode tracks running in parallel.

In a further preferred embodiment of the present invention, an area for connection to reference potential is provided which is of a second conductivity type and is highly doped and has a common interface with the second insulating area and the semiconductor area under the gate electrode.

As with the direct connection of the trough connection regions to the trough-shaped semiconductor region already described, directly along the gate oxide or the second insulating region by omitting the first insulating region at a few points of the tunable capacitance, the described direct connection also takes on reference potential with respect to the whole , of the tunable capacity occupied by the chip area takes up a small area or takes place only in relatively few places in the semiconductor.

With the described direct connection to reference potential by means of a highly doped region of the opposite conductivity type with respect to the trough-shaped semiconductor region, a further improvement in the quality can be achieved.

In a further preferred embodiment of the present invention, the second insulating area has a third Layer thickness that is significantly smaller than the first layer thickness of the first insulating region. The second insulating region is preferably formed as a so-called gate oxide layer in a CMOS manufacturing step. In contrast, the first insulating regions are preferably designed as so-called thick oxide regions, for example as a so-called shallow trench insulation, STI, in order to achieve an improved variation ratio.

Further details of the invention are the subject of the dependent claims. The invention is explained in more detail below using several exemplary embodiments with reference to the drawings.

Show it:

FIG. 1 shows a cross section through an exemplary embodiment of a basic arrangement of a tunable capacitance according to the invention,

FIG. 2 shows a cross section through an object developed with respect to FIG. 1 with a direct connection of the trough-shaped semiconductor region along the gate oxide to a trough connection region,

FIG. 3 shows a schematic plan view of an object with cross sections according to FIGS. 1 and 2,

4 shows a cross section through an object developed with respect to FIG. 1 with a direct connection to reference potential and

FIG. 5 shows a schematic top view of a capacitance with a cross section according to FIG. 4,

FIG. 6 is a graph showing the quality of an exemplary capacitance according to the invention as a function of 4-> xi J

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they should in any case border on the tub connection areas 6, ie not lower.

The buried layer 7 runs parallel to the gate oxide layer 4 along the active front side of the semiconductor body 1.

For a better understanding of the electrical conditions in the integrated tunable capacitance, both the desired and the parasitic electrical replacement elements are shown in FIG. 1, which on the one hand show the series resistance of the varactor and on the other hand the ratio of the variable capacitance to the parasitic capacitances and thus that Determine the variation ratio of the capacity. The variation ratio is defined as the quotient of the maximum and minimum adjustable capacitance value.

In particular, CHH denotes the adjustable space charge capacity, C _ox the gate oxide capacity, C _r edge capacities and C _u the overlap capacity. The resistors Rg and Rι_ to R4 determine the series resistance of the varactor which, together with the capacities, determines the quality of the varactor.

In order to obtain a large variation ratio, it is desirable to obtain a large variation range of the space charge capacity C-jd with simultaneously small, generally fixed capacities C _r and C _u . To increase the quality, the lowest possible series resistance is desirable.

In the present arrangement, the quality is improved in that the resistors R3 and R are significantly reduced compared to a CMOS varactor due to the highly doped collector deep implantation regions 6. With the buried layer 7, which is also highly doped, the resistances R2 can be reduced in particular. PQ l 4- ⁾ 4->

Φ CQ 0 = rö ß φ -H ß Di ß Φ. -H 4-> φ -H Φ O ß CN 03 ß rö ß LSI rö ß 0 Ai 4H CQ φ -H CQ N CQ CQ Di Φ ß Φ rö rH φ Ai> N rö rH o 0 -H -H ü ß ß -HN CQ rö ß Φ -H CQ TJ rö TJ X! TJ ε φ Di Φ a

&> rö 4-> -H rö Φ TJ rö Φ a 0 TJ ß rö -H rö ß ß rH ß ε rö o ε Φ rö TJ ε a X! rö -H Φ T ß ß Eϊ ß 0 4-> 4-) ß rH Φ ß Ai ω -H ß c P 4-1 4-1 Dl -HX! rö «4J XI ^• ϊ Φ Φ ß Φ 4-> Xi 4H TJ 0 4-> TJ

Q 4-H Φ ^^ ß Xi ß TJ υ «Φ rÖ rH 4-> xi TJ Φ 4-1 H Ai υ rö ß fc-i

Φ ~ 3 ro CJ ε _* . ß

H ß> ß 4J rö ß CQ J ß -H rH rö -H X! -H rö ß rö

-H U 0 0 φ rH -H ß 0 ~ 3 ß Φ ß Xi rö -H CQ ß φ ß rH ß rH XI Φ CQ Φ c α. 4 4-1 O J & X! Xi CQ T Φ X! rH rö rH -H XI Φ -H Φ rö Φ ß -H Φ ε rH Ai ε u Φ CJ rö rH φ ro 4-> ~~ φ CΛ rH> u -H rö TJ Dl xi TJ

0 rö ß ß -H CΛ TJ TJ ß rö 1 a 4-> -H N Dl Di ß φ a 4-) ß

4-> φ 0 4H CQ ß 0 Q ß ε ß Φ ε ß ß φ Dl CΛ ß CQ Ai ß ß ß

Ai rö 4-> CΛ Φ 4-> ß -H -H ^ TJ ε -H ß 4-> rö 4J rö Φ 4-> -HO -H -H φ rö ~ 3 ß φ> rH -H 03 <CQ CQ ε rö -H 4-1 Φ P 03 T ß Cn 2 Φ Φ N -H rH rH CΛ 4-1 -H ß -H TJ 4-1 Φ 4J -H -H -HUX! -H LO Φ CQ rH CΛ Φ o M Φ Φ ro 4H 4-> CQ -H Ai X! • Φ ro 4-> 03 -H ß P CQ Di

0 O 4J 2 0 XI rH 4H CQ X! X! 4J Φ Φ 4- ⁾ Xi XI Φ = rö PQ -H Φ Φ -H Φ ß

Ϊ4 2 CQ u 4-> rö φ -H XI CJ rö Di CQ rH Φ ß ε -H ß TJ ß X! ß

U Φ Ai CQ 4-> T rö -H 0 -H TJ -H CQ φ Dl -H Φ TJ Eϊ φ 0 4J J

Φ a

Dl ß Φ rö Φ φ rH 4-> TJ -H rö 4J ß Φ Di 4-> rH ß rH = rö

-H -H φ rH TJ 4-> -H Φ N Φ a

Ai X 4-> TJ 4-1 -H φ -H «. φ 4-> = rö rH rö

TJ Φ φ xi rH rö XI 4-1 Φ 4J TJ φ CN 0 Xi -H 4H ß TJ X! XI Ai xi Cn H

XI i υ O «. rH Φ ß • ß: ⁽ Ö rH Ai ü »ε ß Φ rH υ φ Φ ß -H« Φ Di D 4 -H CQ ß rH Φ CJ -H Lfl ß φ rö 4-> -H -H -H - H rH Φ Φ φ

Φ φ Ai rH 4H φ TJ CQ Φ ß Φ 0 ß -H Φ ß> 4-1 XI Φ rH w> Dl Xi rsi CQ -H ε ß Φ ß -H Φ -HN rH i4 ß P rH Φ 4-> -H φ XI 4-> Xi ß = E- ⁾

4-> -H ß ε Φ -H φ X Di Di rH rö rH TJ rH CQ Xi ß Dl rö Xi J φ Q ε -H ro <"Φ Xi = 0 ß H XI o -H XI ß Φ Φ + E rH φ 0 Φ ü X! CQ P CJ C 4J -H ß

H ^ω SS ü Ai Φ φ Ai TJ υ ß 4J 4J 1-5 φ rH U -H -H CJ ß -H φ rö φ φ ^ rH rH Φ XI Φ -H ü ß -H TJ = ß CΛ g TJ H 4-) ~ 3 P CQ CQ rö • CQ XI Ü U) Di φ φ 4J Φ φ -H = rö rH rH rH Ai Dl 4-1 Dl: ⁽ Ö

Xi CQ Xi -H Φ Xi P 4-1 Dl -H ß φ TJ ß rH Φ -H • • ß Φ ß φ φ Φ Φ 4->

Cn υ Dl 03 υ CQ = 0 X) Φ φ TJ ß φ φ rH Cn U3 rö ß ~ 3 ß -H Φ 4-> ß -H ß -H ß xi = 0 CQ ß rH ε rH -H Di ß CQ a PQ Φ a 4-1 TJ D) T TJ Φ -H CQ • ß rH ß Φ υ rH Φ φ rH φ TJ -H Di CQ rH 03 4-1 4 P Ai ß ß -H Φ rö ß ß X! Di X) CQ Di X) 4J O u> 4-> ß ß <tf rö = 0 Φ = rö Φ -H 4J ß -H ß 03 X! XI φ

TJ = ß -H = ß Φ Φ> -H rH Φ ß rH Ai 4-> ε -H Φ rH -H 4-1 rH rö rH φ X! rö ε

4J ß XI xi CQ TJ φ Φ φ Eä TJ JD ⁾ rH rö XI Φ ε 4J rH TJ rö Dl CJ a X!

0 Φ φ υ 4J rH 4-1 4-1 IS TJ ß -H Φ φ O Dl φ ß CQ W Φ Xi CQ -H Φ ß -H φ Dl Φ -H -H -H CQ Φ ß -HX Es 4 -> Dl CQ -H 4-> rH 4-> .. ß rH Φ ß

TJ Cn Φ -H rH Φ XI rö -H φ -H rö XI 0 -H rH ro 03 Φ = rö φ rH CQ ß Φ 0 Dl -H ß

Ü J 4-1 φ 4H Xi ß Φ ß Φ X! Φ φ ß 0 4J D φ ß 4J -H -H TJ N

«XI CO ß Φ Di φ -H XI 03 rö 4-1 υ rH J ß rH 4-> ß -H ß TJ rö rö ß 4-> TJ φ o ß Φ xi CQ Φ Di Φ rö 4J rö XI Φ X ! Ai -H N -H P Ai ß rö Φ 03 rH

T φ S Φ Φ TJ ß ß 03 -. T Ai ~ 3 rH XI 4-1 J rö rö Cn 03 4-1 rH rö rö ß 4-1 u 4J CQ φ rö -H ß 4-JH Φ TJ rö rH Φ CQ 4-> a = rö ß ß CN ß TJ XI φ Φ Φ -H φ -H Φ rH Di - ß X rö -H ß rö Dl rö ε φ Φ rö Φ ß

Di -H ß - <H Φ ß TJ H XI -H rH ß -H rö ^ r ¹ i XI rö> -H ü-. T Φ ß TJ CQ rH XI »ß

Φ XI ^• H XI ^• ϊ -HH 03 J Φ ß ß P ε U φ ß Φ ß Di φ 4->& J ß Φ

-H φ φ Φ ε CΛ rö CQ N Dl rö o CQ -H Φ Cn Φ CQ N Φ -H Φ Φ ε = rö Ai rH Di -. u ß Φ TJ ß -H Ai Φ TJ 4-> ß Φ rH Φ rH 4-> ^• ä -H -H rH Φ

CQ ß Φ Φ TJ CQ rö CN Cn ß Φ -H ß ß -H ß TJ ro rö ß φ XI 4H 4H TJ Φ

0 ß Φ ß 4-1 4-1 rH •. ß ß -H 4-> X Φ ß X rö η ß 4-) Di 4- ⁾ φ Φ ß

> 0 ß -H Φ Φ N rö 4 Φ rH 03 Φ Φ Φ 0 rH 0 ES J £ -H Ai CQ X! Ü -H 0 -H ß

-H Φ rö -H -H ß ß = rö TJ -H φ rH 4-1 φ ß ß ε ß XI J 4-> 4-1 Xi Φ

-H 4 XI XI XI TJ Φ φ ß Di ε rH 4-1 XI 4-> Φ Φ 4-1 CQ rö Dl -H Φ rH rö -H CQ rH Ai rH 4-1

Φ rö φ P φ φ ß -H -H rö -H Φ φ = rö φ 4-1 -H rö rö 4-1 -H 4 -H 4-> 4J Φ φ o rö Φ = rö

CQ 4-> CQ

^ o Dl ß P ß ES Cr-, Di Eϊ 4-1 Dl ü CΛ X! Ü TJ CQ C- CQ TJ CQ CQ TJ 4J> 4- ⁾

LΠ O Lfl o Lfl O Lfl rH H CN CN ro ro

mo LΠ o

H CN ro ro

that with the subject matter the minimum quality could be improved from 16 to 34 at low tub tension and from 67 to 145 at high tub tension.

The quality of the tunable capacitance is calculated from the series connection of the variable capacitance C and any existing series resistances R with the formula Q = 1 / ωRC with ω = operating angular frequency and Q = quality.

Instead of the exemplary embodiments shown with P substrate and N well and N + collector deep implantation areas, the present principle can of course also be applied to production processes with N substrate. P-doped area is to be used as trough-shaped area 2, while the deep collector implantation areas and the buried layer are to be P + doped. The described direct connections are then also to be provided with the opposite conductivity type with respect to the exemplary embodiments shown.

LIST OF REFERENCE NUMBERS

1 P substrate

2 N-tub 3 thick oxide, STI

4 gate oxide

5 gate electrode

6 N + tub connection area

7 N + Buried Layer 8 reference potential connection area

9 goodness

10 Grade A Thickness B Thickness D Thickness

C _ox gate oxide capacity

C _jd space charge _capacity

C _r marginal capacity

C _ü overlap capacity R _x resistance

R ₂ resistance

R ₃ resistance

R ₄ resistance

R _G resistance

Claims

claims

1. Integrated, tunable capacity, having

a semiconductor body (1) with a trough-shaped semiconductor region (2) of a first conductivity type (N), the semiconductor body (1) being of a second conductivity type (P),

at least one first insulating region (3), which is introduced into the semiconductor body (1), has a common interface with the trough-shaped semiconductor region (2) and a first layer thickness (A),

- a second insulating region (4), which has a common interface with the semiconductor region (2) and a common interface with the first insulating region (3), - a control electrode (5) which is on the second insulating region (4 ) is arranged, and

- at least one trough connection region (6) for connecting the semiconductor region (2) to a control voltage for tuning the capacitance, which has a higher dopant concentration (N +) than the semiconductor region (2) and which has a second layer thickness (B) greater than the first layer thickness ( A) has.

2. Capacitance according to claim 1, so that a buried layer (7) of the first conductivity type (N) with the higher dopant concentration (N +) is provided, which adjoins the at least one well connection region (6).

3. Capacity according to claim 1 or 2, so that the at least one tub connection area (6) is formed in bipolar manufacturing technology.

4. Capacity according to one of claims 1 to 3, characterized in that the at least one trough connection region (6) each has a common interface with the second insulating region (4) and the semiconductor region (2) under the control electrode (5).

5. Capacitance according to one of claims 1 to 4, characterized in that an area for connection to reference potential (8) is provided, which is of the second conductivity type (P) and highly doped (P +) and a common interface with the second insulating area (4) and the semiconductor region (2) under the control electrode (5).

6. Capacitance according to one of claims 1 to 5, so that the second insulating region (4) has a third layer thickness (D) which is smaller than the first layer thickness (A) of the first insulating region (3).

7. Capacitance according to one of claims 1 to 6, so that the first insulating region (3) is a shallow trench insulation region.

8. Capacitance according to one of claims 1 to 7, d a d u r c h g e k e n n z e i c h n e t that the second insulating region (4) is an oxide layer.

9. Capacitance according to one of claims 1 to 8, that the control electrode (5) is formed by means of a polycrystalline layer.