EP1384325B1 - Resonante logiktreiberschaltung - Google Patents

Resonante logiktreiberschaltung Download PDF

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Publication number
EP1384325B1
EP1384325B1 EP02764076A EP02764076A EP1384325B1 EP 1384325 B1 EP1384325 B1 EP 1384325B1 EP 02764076 A EP02764076 A EP 02764076A EP 02764076 A EP02764076 A EP 02764076A EP 1384325 B1 EP1384325 B1 EP 1384325B1
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Prior art keywords
driver circuit
circuit according
load
voltage
driver
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French (fr)
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EP1384325A1 (de
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Geoffrey Philip Harvey
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Midas Green Ltd
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Midas Green Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/009—Resonant driver circuits

Definitions

  • This invention relates to an electronic logic driver circuit. More specifically, this invention relates to reducing power consumption of electronic logic circuits and the conditioning of signals within electronic logic circuits.
  • An electronic circuit consumes power in various ways.
  • power is consumed when input signals to elements of the circuit change state.
  • a contribution to this power consumption occurs because of the charging and discharging of parasitic capacitance associated with the input signals to circuit elements and with wires connecting these input signals to signal drivers.
  • Power dissipation does not occur in the parasitic capacitance itself, but in the output resistance of the signal drivers.
  • a modem digital integrated circuit typically drives a large number of off-chip signals, which, whilst having high capacitance loading, operate at a relatively low frequency and thus consume a significant (but nevertheless small) portion of the total power consumption of the IC.
  • ICs also include many global on-chip signals, such as clock signals or address lines, which traverse the entire chip driving many internal inputs.
  • Fig 1 shows, for the purpose of illustration, a conventional CMOS IC inverter driver 10 that furnishes a driver output signal VD to an interconnect 12, which in turn furnishes interconnect output signal VO to a load 14.
  • the driver 10 is used as an on-chip driver
  • the load 14 is typically constituted by inputs to further logic devices formed as part of the same IC and the interconnect 12 is formed in on-chip metallization layers. Due to their small dimensions, on-chip interconnects typically have low series inductance.
  • the load 14 is typically constituted by input pins to further IC's mounted on the same printed circuit board (PCB) and the interconnect 12 is constituted by a combination of lead-frame conductors within IC packages and conductors etched onto the PCB. Due to relatively large dimensions of PCB conductors, such interconnects have typically have appreciable series inductance.
  • PCB printed circuit board
  • the inverter driver 10 includes an NMOS transistor M1 serially connected to a PMOS transistor M2 between a positive supply rail VDD and a ground supply rail VSS . Since M1 is turned on by applying a positive voltage to its gate input and M 2 is turned on by applying a ground potential to its gate input, normally only one of the two is conductive during steady-state conditions. Therefore, if the input signal V C is at a 'low' potential (i.e. near VSS potential) then the driver output signal V D is driven to a 'high' potential (i.e. near VDD potential), and conversely. During transitions of the input signal VC between high and low potentials, there is generally a brief period when both transistors M1 and M2 are simultaneously conductive.
  • Fig 2 there is shown a simplified electrical model of the circuit of Fig 1.
  • the output of the inverter driver 10 is modelled by a controllable switch SW in series with an output resistance R(ON).
  • the output resistance represents the source-drain resistance of either transistor M1 or M2 in its 'on' condition.
  • a capacitor C(IN) models the input (gate) capacitance of the transistors M1 and M2.
  • the interconnect 12 is modelled by a series resistance RI and a series inductance LI and a distributed capacitance CI .
  • the distributed capacitance CI is typically smaller than the load capacitance CL so that, to a reasonable degree of accuracy, the distributed capacitance CI can be considered as forming part of load capacitance CL.
  • Fig. 3a shows how signals VD and VO in Fig. 1 typically change when an input signal VP is driven from 'high' to 'low' when the driver 10 is used as an on-chip driver.
  • the current flow into load CL is effectively limited by the driver output resistance R(ON), so the driver output signal VD changes approximately exponentially from 'low' to 'high'. Since the interconnect inductance and resistance are comparatively small, the conductor output signal VO is only slightly delayed and overshoot is negligible.
  • Fig 3b shows how signals VD and VO in Fig. 1 typically change when input signal VP is driven from 'high' to 'low' when the driver 10 is used as an off-chip driver.
  • the current flow into load CL is effectively determined both by the driver output resistance R(ON) and the interconnect inductance LI.
  • the driver output signal VD begins a transition from 'low' to 'high' quite quickly
  • the interconnect inductance causes the interconnect output signal VO to change in a damped sinusoidal manner with some degree of overshoot.
  • On-chip signals are generally required to operate at very high speed, therefore a low value of R(ON) is needed. This is achieved by making the channel width of the drive transistors within the driver 10 quite large. This means that the input capacitance C(IN) of driver 10 may be as much as one third the value of load capacitance CL.
  • R(ON) typically is made much larger in relative terms to limit the speed of the transition and to reduce the ringing and overshoot that would otherwise occur due to the appreciable inductance of the interconnect. Nevertheless, there is typically some overshoot as shown in Fig 3b.
  • the channel width of drive transistors within the driver 10 can be made much smaller for a given load capacitance when driver 10 is an off-chip driver. Therefore, in this case the input capacitance C(IN) of the driver 10 is quite small compared to load capacitance CL.
  • the energy drawn from the supply (ignoring that used in charging and discharging C(IN)) is approximately equal to CV 2 , where V is the potential between VDD and VSS and C is the numerical value of CL. Similar waveforms occur when the output goes from 'high' to 'low', but in this case there is no power is drawn from the VDD supply.
  • the power drawn from the VDD supply when the output is driven at a frequency f is on average equal to f CV 2 .
  • Much of this power is dissipated in the driver output resistance R(ON). The power dissipation cannot be reduced merely by making the value of R(ON) smaller since the only effect would be to increase the amount of overshoot and ringing.
  • WO-A-97/09783 the present applicant showed that the power dissipation, especially of off-chip drivers, can be reduced typically by 75% by harnessing, as an energy storage mechanism, the ringing that occurs when load 14 is driven via an appreciable inductance such as PCB interconnect inductance.
  • An input signal VC to the driver 18 feeds a control circuit that generates control signals V5, V6 and V7 , which in turn connect, to the gate electrodes of NMOS transistors M3 and M4 and a PMOS transistor M5 respectively.
  • the drain connections of these transistors M3, M4 and M5 are all connected to the output VS of the driver 18.
  • the transistors M3 and M5 can connect the output signal VS to VSS and VDD respectively whilst the transistor M4 can connect the output to an intermediate voltage VHH.
  • the transistor M4 is designed to have a lower 'on' resistance than either of the transistors M3 or M5 (or M1 or M2 in Fig 1 when the driver 10 is used as an off-chip driver).
  • the output signal VS is also connected to the load 14 via a PCB interconnect 12, which has been modelled as an inductor LR.
  • Fig. 5 shows the waveform that would result if signals V S and V O have been previously charged to a steady state V SS potential by the transistor M3 having been turned on, but with the transistor M3 now being turned off.
  • the transistor M4 is turned on indefinitely.
  • the output VS of the driver moves quickly to VHH potential.
  • the transistor M4 has a low 'on' resistance, the voltage of the interconnect output signal VO overshoots VHH potential and reaches almost the potential of VDD , and thereafter rings sinusoidally with a resonant frequency f(r) given by Equation 1.1 below.
  • f r 1 2 ⁇ ⁇ ⁇ LC
  • the current passing through the transistor M4 alternates in direction and also causes a very small voltage drop across the transistor M4, causing the output voltage VS of the driver to deviate slightly from VHH potential. Since a small amount of power is dissipated in the transistor M4 and in the also in the various loss mechanisms associates with the load, the amplitude of oscillations gradually decreases.
  • Fig. 6 shows how, if the sinusoidal oscillation depicted in Fig. 5 can be arrested at time t2 (i.e. after half of one complete oscillation).
  • the required transition of interconnect output signal VO can be achieved with very low power dissipation.
  • the driver output signal VS is held at or near VHH potential until the interconnect output signal VO reaches a first maximum. Then the potential of the signal VS is raised to that of VDD by switching off the transistor M4 and switching on the transistor M5.
  • Fig. 6 also shows the required sequence of control signals V5, V6 and V7 in response to the input V1 for LOW-to-HIGH and HIGH-to-LOW transitions.
  • the driver 18 then furnishes an output signal VS in the form of a two-step rising or falling staircase.
  • This allows the interconnect output signal VO to largely complete each conductor output transition while the VS signal is held at an intermediate level. This means that greatly reduced current is drawn from the power supply.
  • This general technique will be called “staircase resonant" driving of capacitive loads in this specification.
  • the staircase resonant driver 18 is useful for driving off-chip signals that have a relatively slow rise time and have inherent series inductance sufficient to produce resonance.
  • On-chip signals generally have low inductance but on-chip inductors (for example spiral trace inductors) could be explicitly provided to furnish the required resonance inductance.
  • on-chip signals must generally be driven at a speed typically an order of magnitude faster than off-chip signals.
  • the peak current flowing in the transistor M4 in Fig. 4 is therefore an order of magnitude higher driving an on-chip load capacitance compared with driving the same off-chip load capacitance so that the "ON" resistance of the transistor M4 is made an order of magnitude lower to achieve the same level of resonant overshoot.
  • the "ON" resistance of the transistor M4 can be reduced by increasing its channel width; but after a point it requires an excessive power consumption to operate or switch transistor M4 due to its increased gate capacitance such that the overall power dissipation is increased contrary to the desired effect which is to decrease overall power dissipation.
  • the driver 18 is may be unsuitable for driving high-speed on-chip signals because the transistor M4 has an "ON" resistance that is too high in relation to the power taken to switch it on and off. This is partly because the maximum gate-source voltage applied to the transistor M4 between times t1 and t2 in Fig.6 is only half of the power supply voltage and because the time of rise and fall of the control signal V is now similar to the desired conductor output rise/fall time and the average gate-source voltage is even lower. Furthermore, the control voltage V makes two transitions corresponding to each transition of the output. This further limits the channel width of the transistor M4 that can be used without leading to excessive power consumption.
  • electronic driver circuits are provided for driving a capacitive load between supply potentials as defined in the appendant independent claims, to which reference should now be made.
  • Embodiments of the present invention are defined in the appendant dependent claims, to which reference should also now be made.
  • Coupled inductors as a repository for stored energy reduces the amount of energy that the driver must draw from its power supply.
  • a resonant inductor may be connected to a common point between the coupled inductors.
  • the resonant inductor may supplement or substitute for the inductance of the driven load.
  • Embodiments of the invention may be suitable for driving two loads with complementary signals. Such embodiments may be constructed in accordance with the aspect of the present invention defined in appendant claim 3.
  • One or both of the voltage sources is (or includes) a voltage supply rail.
  • one or both of the voltage sources may include a reservoir capacitor maintained at a potential at or near a main supply rail.
  • one or more of the switching devices may include a MOSFET.
  • approximately the full allowable gate drive voltage can be applied to the switches, so reducing their "on" resistance.
  • a switching device may be a MOSFET inverter.
  • a switching device may include one or more diode through which energy may return to the power supply.
  • the load(s) can be connected to one or both voltage sources via one or more coupled inductors and one or more switching devices
  • some embodiments may also include a clamp circuit comprising further switching devices which can directly connect or clamp the load to one or other main voltage supply rail during intervals between changing the voltage of the load(s).
  • a driver embodying the invention may further comprise an energy recovery inductor connected to couple with the coupled inductors.
  • the energy recovery inductor has a greater number of turns than either of the coupled inductors.
  • the output of the driver may include a clamp circuit. This enables the output to be clamped to a target output voltage.
  • a driver circuit embodying the invention is typically implemented in an integrated circuit for driving a load on or off the integrated circuit.
  • the coupled inductors typically connect to or constitute part of the inductance in an LC resonator formed with the load. Most typically, the coupled inductors form a substantial part of the inductance of the LC resonator.
  • a driver embodying the invention may further comprise an energy recovery inductor connected to couple with the coupled inductors.
  • the energy recovery inductor typically has a greater number of turns than either of the coupled inductors.
  • one or more inductors of a circuit embodying the invention is at least partially constituted by an interconnect, for example, an interconnect that connects a chip to an external device.
  • Typical embodiments of a driver circuit embodying the invention are driven by first and second input signals.
  • Each of the input signals typically controls a respective one of the switching devices, each input signal having an active state and an inactive state.
  • the waveform of the second driver signal may be a time-shifted function of the waveform of the first driver signal.
  • the waveform of the second driver signal is in the inactive state only within a period in which the first driver signal is in the active state.
  • an applied voltage approximately equal to the supply voltage can be shared or split between two inductors in an efficient manner to generate the half supply voltage step needed to produce a staircase waveform.
  • EMF electroactive force
  • This avoids the need to switch current to or from a source of intermediate voltage supply via a switching device and consequently further avoids the high resistive losses that occur in a prior art method of "staircase resonant driving".
  • This is particularly so when such a switching device comprises a MOSFET with a limited gate-source drive voltage due to the source electrode being connected to a source of intermediate voltage supply and the gate drive voltage being limited to a voltage level between the two main supply rails.
  • Embodiments of the invention may further avoid the need to generate a very short enabling pulse otherwise needed to enable the flow of current to or from a source of intermediate supply voltage corresponding approximately to the desired output signal transition time.
  • the output signal transition time corresponds to an overlap period in which at least two switch enabling pulses of relatively long duration are simultaneously active only during output signal transitions.
  • each enabling pulse typically makes only one transition corresponding to each output transition. This may provide major advantages in relation to a prior art "staircase resonant" driver when it is desired to drive signals with fast rise time and low power consumption.
  • the principles of the invention can be embodied in either a single polarity driver with a single output or a complementary polarity driver with dual outputs being logical complements.
  • the latter By magnetically coupling (in appropriate polarity) complementary signals via coupled inductors, the latter has the further advantage of generating a signal and its logical complement with a high degree of passive coupling and with transition of both the signal and its complement initiated by the same control input signal, thus allowing much lower skew than is possible using an active device to generate the logical complement of a signal.
  • a single output driver designed to embody the present invention may comprise a staircase generator which, in response to one or more control inputs, generates a staircase output signal connected serially via a resonance inductor to an output load and optional output clamp circuit which when present is also responsive to one or more input signals.
  • the load is substantially capacitive and is constituted by the combined parasitic input capacitances of one or more logic gate inputs driven by the driver. When the combined load capacitance is physically close to the driver, the load may often be approximated to reasonable degree of accuracy simply by a capacitor.
  • the load capacitance When the load capacitance is remote from the driver (for example, an on-chip driver in combination with either an off chip load capacitance or an on-chip load capacitance connected via an on-chip interconnect of appreciable length) the load may be represented to a reasonable degree of accuracy by a small inductor in series in series with a small resistor, in turn in series with the load capacitance (capacitor); the inductor representing the inductance of the interconnect and the resistor representing the resistance of the interconnect.
  • the staircase generator circuit may have an output inductance that is effectively in series with the resonance inductor.
  • the single output driver functions as follows. Assume that both the load and the staircase generator are at a low voltage level (VSS), but it is desired to change the voltage of the load to a high level VDD, in response to one or more input signals.
  • the staircase generator output voltage first moves quite quickly to an intermediate voltage level with a potential that is approximately mid-way between VSS and VDD.
  • the action of the resonance inductor is initially to limit the flow of current from the staircase generator to the capacitive load. As the current builds, the voltage at the load begins to change in a resonant sinusoidal manner consistent with a resonant frequency determined by the values of the load capacitance and the resonance inductor.
  • the rate of change of load voltage reaches a maximum approximately when load voltage equals the intermediate voltage level, at which point about half of the energy supplied by the staircase generator has been used in charging the load capacitance. Some energy has been dissipated as heat due to various resistances and non-idealities, but a large remaining portion has been stored in the resonance inductor.
  • the staircase output voltage remains approximately at the intermediate voltage for a further period of time, during which the energy stored in the inductor enables the load voltage to considerably overshoot the intermediate voltage level almost reaching the level of VDD, but with much lower expenditure of energy than in a conventional inverter driver.
  • the staircase generator output voltage changes to from the intermediate voltage level to that of VDD causing the load voltage to completely reach the level of VDD with some small amount of overshoot and ringing.
  • the staircase generator effectively supplies extra energy, which replenishes any energy dissipated during the transition.
  • the dissipated energy is largely supplied from the optional clamp circuit, which, in response to one or more input signals, connects the load to VSS via a switch that is released before the transition and then reconnects the load via a second switch to VDD after the transition.
  • An integrated circuit may be provided incorporating a driver circuit according to any of the appendant claims.
  • embodiments of the invention may reduce the power consumption by up to 70% compared the conventional inverter driver.
  • FIG. 7 illustrates how full swing input signals can be used in conjunction with a purely passive circuit comprising coupled inductors to produce the half-swing step of a staircase output waveform.
  • the circuit in Fig. 7 comprises an inductor circuit 24, two independent time varying voltage supply sources V1 and V2, and a load capacitor CL.
  • the inductor circuit 24 has two input terminals IN1 and IN2 and a single output terminal OUT.
  • the outputs terminals of time varying voltage supply sources V1 and V2 are connected to input terminals IN1 and IN2 respectively of an inductor circuit 24 and supply time varying voltage signals VP1 and VP2, respectively.
  • Output terminal OUT of inductor 24 is connected to a first terminal of the load capacitance CL, the voltage across the load capacitor CL being denoted by VO.
  • the reference terminals of time varying voltage supply sources V1 and V2 and the second terminal of load capacitor CL are all connected to a common circuit ground node.
  • inductor circuit 24 To assist in understanding the operation of inductor circuit 24 it is helpful to consider the current flows within it as being the superposition of a first component of current flow ISELF flowing from input terminal IN1 to input terminal IN2 and a second component of current flow IL flowing from the output terminal OUT.
  • the inductor circuit 24 comprises two series-connected staircase generator inductors LS1 and LS2 of equal self-inductance and strongly coupled by mutual inductance with a coefficient of mutual coupling KS.
  • KS mutual coupling
  • inductors LS1 and LS2 either as a single inductor with a centre tap or as an auto-transformer with centre tap.
  • the centre tap or circuit node joining inductors LS1 and LS2 furnishes an input signal V S to a first terminal of a resonance inductor LR , the other terminal of which furnishes an output signal V O to a load capacitance C L .
  • V P1 and V P2 are at ground potential, as are all other circuit nodes, and no current is flowing. Therefore, the load capacitance C L is fully discharged and V O at a low voltage level (0 volts with respect to the ground node).
  • VP2 also goes form 0 volts to 1 volt, and consequently V S goes from 0.5 volts to 1 volt, effectively arresting the oscillation with load capacitance C L charged to 1 volt, as desired.
  • the timing of the transition of signal V P2 at time t2 in relation to the transition V P1 at time t1 is assumed to have been arranged to coincide approximately with the completion of the transition of the signal V O , being when signal V O is reaches a first maximum voltage near to 1 volt.
  • I L the current charging C L
  • I SELF current I SELF as indicated in Fig. 8
  • the circuit of Fig. 9 shows how the same principle can be applied to drive two equal capacitive loads C L1 and C L2 with complementary signals.
  • the circuit comprises time varying voltage sources V1 and V2 connecting via inductor circuit 19 to load capacitors CL1 and CL2 respectively.
  • the inductor circuit 19 has input terminals IN1 and IN2 and output terminals OUT1 and OUT2.
  • the inductor circuit 19 connects the time varying voltage source V1 to the load capacitor CL1 via a first current path from the input terminal IN1 to the output terminal OUT1 , consisting of the series combination of staircase generating first mutually coupled inductor LS1 and first resonance inductor LR1 .
  • the inductor circuit 19 similarly connects the time varying voltage source V2 to the load capacitance CL2 via a similar second current path from the input terminal IN2 to output terminal OUT2 , consisting of the series combination of a staircase generating second mutually coupled inductor LS2 and a second resonance inductor LR2 .
  • the inductors LS1 and LS2 are tightly coupled by mutual inductance with a coefficient of mutual coupling KS. For the purpose of clarity, it is assumed that the value of KS closely approaches unity, corresponding to nearly 100% mutual coupling.
  • the first and second current paths are electrically isolated.
  • the respective output voltages of voltage sources V1 and V2 are denoted by V P1 and V P2 respectively and the respective voltages across load capacitors CL1 and CL2 are denoted by V O1 and V O2 respectively.
  • V P1 and V P2 the respective voltages across load capacitors CL1 and CL2 are denoted by V O1 and V O2 respectively.
  • V P1 and V O1 associated with the first capacitive load are at a low voltage while the input and output voltages V P2 and V O2 associated with the second capacitive load are at a high voltage.
  • VP1 goes from a low voltage to a high voltage an approximately sinusoidal current I L1 builds, flowing from the voltage source V1 to load C L1 .
  • Fig 10 Voltage and current waveforms occurring in relation to the operation of the circuit of Fig 9 are shown in Fig 10.
  • the waveforms for current flows I L1 and I L2 show how they can be considered as approximately sinusoidal signal components of current flow I S1 and I S2 respectively, superimposed on a common mode component of current flow, I CM .
  • Common mode component current I CM causes a residual current flow to persist similar to that described in relation to Fig. 7, which tends to cause a continuing common-mode oscillation of V O1 and V O2 .
  • This problem can be overcome.
  • the magnitude of the common mode current is greatly reduced because the effect of the mutual coupling between LS1 and LS2 is to increase their apparent inductance in relation to any common mode current flowing within them. It is important to note that both complementary signal transitions are initiated by the single event of V P1 going to a high voltage, therefore the timing skew between V O1 and V O2 is quite small, which is desirable for many applications.
  • Fig. 11 shows a driver 26, being a practical single output driver embodiment of the invention, with its output connected to a load 20.
  • the load 20 illustrates the case where the load capacitance is physically remote from driver 26 and connected via an interconnect with series inductance and resistance L L and R L respectively.
  • the operation of the driver 26 is similar to that described in relation to the circuit of Fig. 7, the main difference being that signals V P1 and V P2 are supplied by CMOS inverter circuits 22, 23 comprising MOS transistors M1, M2, M3, M4 as shown.
  • the driver further includes an inductor circuit 24 that comprises two staircase generator inductors LS1, LS2 and a resonance inductor LR.
  • the resonance inductor LR is shown in dotted lines in Fig.
  • the waveforms that occur in relation to the driver 26 are shown in Fig. 12 and are similar to those shown in Fig. 8. Since the signals V P1 and V P2 now derive from CMOS inverters, which have noticeable output resistance and not idealized voltage sources as in Fig. 7, both exhibit a sinusoidal dip during output transitions from t1 to t2 and from t3 to t4 . Also, the residual current flow between the transitions causes V P1 and V P2 to be displaced slightly from the associated supply rail potential immediately following transitions at time t2 and t4 and to approach the rail potentials exponentially as the current decays due to resistive losses in the CMOS inverters 22, 23.
  • V S staircase voltage
  • Fig. 12 it can be seen that direction of current flow that occurs because of the signal V P2 via the CMOS inverters 22, 23 is always such as to return current to the circuit power supply via V DD and V SS . Therefore, the inverter 23 can be replaced with diodes connected to the load 20, as is the case in driver 28 shown in Fig. 13.
  • the load 20 is shown as being constituted by the combined parasitic capacitance of various CMOS gates being driven by the signal VO on the same chip. Similar waveforms occur in this example as have been described within the driver 26 except that the potential of signal V P2 is determined by the forward drop V f of the diodes in relation to the power rail voltages as shown in Fig. 14.
  • a particular advantage of this configuration is that it has only one input signal V P1 and is self-timed; diodes D1 & D2 allowing the internal signal V P2 to transition automatically at the nearly the same time as V O completes it transition, thus simplifying the provision of input signal for driver 28 when compared to driver 26.
  • a non-unity turns ratio normally gives superior output waveforms.
  • a driver 40 comprising CMOS inverters 32, &34, an inductor circuit 24 (with unity turns ratio) and a clamp circuit 30.
  • a driver 26 appears similar to driver 26 of Fig. 11, but in this case, it is supplied with input control signals V C1 and V C2 that drive CMOS inverters 32, 34 with an alternative timing sequence that is highly efficient.
  • the CMOS inverter 32 includes a PMOS transistor M1 and an NMOS transistor M2. Operation of this embodiment is such that the inverter 32 is used primarily in a "pull-up” mode. Therefore, in terms of minimizing the resistive losses in driver 40, it is the "ON" resistance of the transistor M1 that is of primary concern. Thus, by increasing the channel width of the transistor M1 and reducing the channel width of M2 lower resistive losses result without increasing the input capacitance of driver 40. Similarly, the CMOS inverter 34, which includes a PMOS transistor M3 and NMOS transistor M4, is used primarily in a "pull-down” mode and the channel width of the transistor M4 can be increased and the channel width of the transistor M3 decreased.
  • the sequencing of control inputs V C1 and V C2 is such that, during output transitions when current flow through the inverters 32, 34 is at a maximum, the transistors M1, M4 are conducting whereas the transistors M2, M3 are non-conducting. Therefore, resistive losses are kept low.
  • the inverters 32, 34 drive output signals V D1 , V D2 that connect via series DC blocking capacitors C D1 , C D2 respectively to signals V P1 , V P2 being the inputs to the inductor circuit 24 as before.
  • the blocking capacitors C D1 , C D2 are needed to prevent the average DC voltage that exists between signals V D1 and V D2 from causing a large and wasteful DC component of I SELF through the inductors LS1, LS2.
  • the blocking capacitors C D1 , C D2 are made quite large in value compared with the load capacitance C L . Therefore, the input signals V P1 , V P2 are DC shifted versions of V D1 , V D2 shifted such that I SELF has no DC component, as shown in Fig. 16.
  • V P1 and V P2 are symmetrically disposed about the voltage level of VSS and therefore signal V S and V O are also at VSS .
  • a clamp circuit 30, which is constituted by a PMOS transistor M5 connected in series with an NMOS device M6 holds signal V R (and, since the values of LL and RL are small, therefore also VO) at VSS. Since V C1 is "high” and the transistor M6 is conductive, whilst V C2 is also "high” and the transistor M5 is non-conductive.
  • the signal V C1 goes “low” and the clamp circuit 30 releases the signal V R whilst at the same time causing V P1 to move “high” (near to the potential of VDD) and the staircase voltage V S to increase to a voltage approximately midway between VDD and VSS.
  • the signal V C2 goes “low” and signal V P1 goes “high”, such that both V P1 and V P2 are symmetrically disposed about the potential of VDD. Therefore, the staircase voltage V S also moves to the level of VDD.
  • the signals V R and V O move sinusoidally towards the level of VDD as before, but due to resistive losses would not actually reach the level of VDD.
  • the PMOS transistor M5 in the clamp circuit 30 becomes conductive and pulls signals V R and V O to the level of VDD thus replenishing any dissipated energy.
  • the current I SELF increases, but as shown, between transitions it decreases due to the reversal of potential between signals V P1 and V P2 .
  • a similar sequence begins at time t3 , causing the transition of the output signal V O from "high” to "low".
  • a driver 42 that operates in a very similar manner to the driver 40 described above.
  • the DC blocking capacitors CD1, CD2 of Fig. 15 are replaced by DC blocking capacitors CDD1, CSS1, CDD2 and CSS2 such that a CMOS inverter 32 directly switches between DC shifted supply rails V SS1 and V DD1 , and a CMOS inverter 34 switches between DC shifted supply rails V SS2 and V DD2 as shown.
  • the input signals V P1 and V P2 in Fig. 17 are similar to the signals V P1 and V P2 of Fig. 15.
  • the remainder of the circuit operates in the manner described in the previous paragraph.
  • the advantage of the driver 42 of this embodiment is that it does not require floating capacitors, which can be difficult to fabricate on a standard CMOS chip.
  • Fig. 19 shows a driver 44, a variation of the driver 42 of the preceding embodiment, in which the transistors M2 and M3 are replaced by diodes D1, D2 connected directly to the supply rails V DD1, V DD2 .
  • This arrangement has the advantage of further reducing the input capacitance at the expense of some dissipation between transitions as the current I SELF dissipates stored energy by flowing across the forward voltage drop (Vf) of diodes D1 and D2.
  • Vf forward voltage drop
  • the driver 44 function in the same way as the drivers 40 and 42 previously described.
  • Fig. 21 shows a driver 46, being a variation on the driver 44, in which I SELF is reduced to zero after each transition in a more energy efficient manner by coupling inductors LS1 and LS2 to a separate energy recovery inductor LE1 which has more many more turns than LS1 and LS2 combined.
  • a high voltage is induced in LE1 that causes a signal V E to go to a much lower voltage than V SS .
  • the diode D1 is reverse biased, no current flows in the inductor LE1.
  • the diode D1 goes into forward bias and the energy stored in the inductors LS1 and LS2 is largely returned to the power supply by LE1.
  • Fig. 23 shows an embodiment having a driver 48 which an example of a complementary output embodiment of the invention.
  • the driver 48 receives four input signals, namely V C1 , and V C2 and their logical complements / V C1 and / V C2 and drives two similar loads 20 and 21, furnishing complementary output signals V O1 and V O2 respectively.
  • the driver 48 comprises a switching circuit 50, further comprising CMOS inverters 34 and 35, switching between DC shifted supply rails VSS1 and VDD1 derived from input voltage supply sources VSS and VDD via DC blocking capacitors CSS and CDD respectively.
  • the CMOS inverter 34 comprises transistors M1 and M7 while CMOS inverter 35 comprises transistors M2 and M8.
  • the driver 48 further comprises identical clamp circuits 30 and 31 which in response to input signals V C1 , V C2 / V C1 and /V C2 can clamp the inputs to loads 20 and 21 to either of the input voltage source VSS or VDD.
  • Loads 20 and 21 connect to switching circuit 50 via coupled inductor circuit 19.
  • Inductor circuit 19 connects the output of the CMOS inverter 35 to a first load 20 via a first current path consisting of the series combination of staircase generating the first mutually coupled inductor LS1 and the first resonance inductor LR1.
  • the inductor circuit 19 similarly connects the output of the CMOS inverter 34 to a second load 21 via an similar second current path consisting of the series combination of a staircase generating second mutually coupled inductor LS2 and second resonance inductor LR2 .
  • the inductors LR1 and LR2 and shown in dotted lines to indicate that their function may be equivalently provided by a leakage inductance from LS1 and LS2 when their coupling factor K is less than unity. Referring to Figs. 23 and 24, the circuit functions as follows: at time t0 , V O1 is clamped to VSS via LL1 and RL1 by a transistor M3 and V O2 is clamped to VDD via LL2 and RL2 by transistor M6.
  • the input signal VC1 to CMOS inverter 34 is "high” and therefore its output signal VP1 is connected to the offset voltage source VSS1 via a transistor M2.
  • the input signal VC2 to the CMOS inverter 35 VC1 is “low” and therefore its output signal VP2 is connect to the DC shifted supply rail VDD1 via the transistor M1.
  • the DC shifted supply rails VSS1 and VDD1 stabilize such they maintain a slight positive offset from input voltage sources VSS and VDD.
  • both clamp circuits 30 are released and the transistor M2 becomes conducting while the transistor M1 remains conducting.
  • both staircase signals are initiated by the same input signal event; V C1 going “high”.
  • the reverse transitions are initiated at time t3 when V C2 goes “high”.
  • the circuit is quite efficient in that the current for all transitions is substantially switched via a transistor M1 or M2, both of which are NMOS devices, which normally have a lower "ON" resistance than a PMOS device of the same size and input capacitance.
  • current flows through the inductors LS1 and LS2 can be considered as approximately sinusoidal signal components of current flow I S1 and I S2 respectively, superimposed on a common mode component of current flow, I CM .
  • the signal VP1 and VP2 are both at a low level during all transitions of VO1 and VO2 causing the magnitude I CM to rise steadily during those transitions.
  • VP1 and VP2 By switching VP1 and VP2 between the DC shifted supply rails VSS1 and VDD1, a small positive voltage is applied between transition, the effect of which is to cause I CM to decrease slowly between transitions thus limiting the value I CM to quite a low level.
  • any of the embodiments described might comprise either on-chip coupled inductors and resonance inductor formed as spiral trace inductors or simple lengths of track utilizing mutual coupling between adjacent parallel lengths of track to form coupled inductors.
  • the inductors become part of the distribution network of the circuit of which the driver forms a part.
  • the inductor component could equally be formed in off-chip components.
  • Fig 25 shows an inductor layout 52 being a possible on-chip physical layout for coupled inductors corresponding to the inductor circuit 24 in Fig.11 for the case of a 1:1 turns ratio and where the resonance inductance L R is equivalently provided by a leakage inductance between two coupled inductors L S1 and L S2 as described previously in relation to Fig. 11.
  • the layout is essentially formed as sequential first, second, third and fourth concentric octagonal turns, the 1st being the outermost and the fourth being the innermost.
  • the turns could equally be circular but octagonal structures are commonly substituted for circular structures in chip fabrication to simplify requirements on lithography processes.
  • the inductor layout 52 is formed from two layers of metallization, being an upper and lower layer etched or otherwise patterned to form broadly octagonal conductive paths onto an insulating substrate the two metallization layers being insulated from each other except where connected by via.
  • the 1 st and 3 rd turns of inductor layout 52 correspond to inductor LS1 in inductor circuit 24 whilst the second and fourth turns correspond to the inductor LS2 in inductor circuit 24.
  • the current flows in the inductor circuit 24 can be viewed as the superposition of two component current flows I SELF and IL .
  • the rotational direction of current flow is the same in all four turns and the effective inductance seen between the two input terminals is quite high.
  • the magnetic field in this case is reinforced by all four turns and is of a quite large spatial extent, tending to encompass all four turns.
  • IL the component of current flow due current flowing from the output terminal of inductor layout 52
  • the magnetic field is mainly confined to the spaces between the turns leading to a small leakage inductance, which nevertheless can equivalently provide the resonance inductance LR of the inductor circuit 24.
  • Figure 26 shows an inductor layout 54, a possible on-chip physical layout for coupled inductors corresponding to inductor circuit 19 in Figs. 9 and 23 and where the resonance inductances L R1 and LR2 are equivalently provided by a leakage inductance between two coupled inductors L S1 and L S2 as described previously in relation to Fig.23.
  • the inductor layout 54 is constructed as two metallization layer as described in relation to the inductor layout 52.
  • the layout is again composed of a sequential first, second, third and fourth concentric octagonal turns, the first being the outermost and the fourth being the innermost.
  • the first and third turns correspond to the coupled inductor LS1 in inductor circuit 19 while the second and fourth turns correspond to the coupled inductor LS2 in the inductor circuit 19.
  • the current flows in coupled inductors LS 1 and LS2 of inductor circuit 19 can be viewed as the superposition of two signal components of current flows I S1 , I S2 being of opposite polarity superimposed on a common mode component of current flow I CM .
  • I CM component of current flow the rotational direction of current flow is the same in all four turns and the effective inductance seen between input terminal IN1 and output terminal OUT1 is quite high.
  • the effective inductance seen between input terminal IN2 and output terminal OUT2 is also quite high.
  • the magnetic field in this case is reinforced by all four turns and is of a quite large spatial extent, tending to encompass all four turns.
  • I S1 , and I S2 the signal components of current flow cause current to flow in opposite directions in each adjacent turn.
  • the magnetic field is mainly confined to the spaces between the turns leading to a small leakage inductance, which nevertheless can equivalently provide the resonance inductance LR1 and LR2 of the inductor circuit 19.
  • Fig. 27 shows how coupled inductor circuits, and particularly coupled inductor circuit 19 can be laid out to serve the additional function of circuit interconnect.
  • the circuit in Fig. 27 is equivalent to that of Fig. 9 but coupled the inductor circuit 19 in Fig. 9 has been replaced by the layout 56 shown in Fig 27.
  • the layout 56 is similar to the layout 54 but has turns 'un-wrapped' into linear inductive tracks.
  • the first and second tracks in the layout 56 correspond to a first "unwrapped" instance of the layout 54, while the third and fourth tracks un the layout 56 correspond to a second unwrapped instance of layout 54.
  • layout 54 Whilst a single 'unwrapped' instance of layout 54 could be used, placing a second or further multiple instances side-by-side to increase the effective inductance seen by a common mode component of current flow I CM , compared to the inductance seen by signal components of current flow I S1 and I S2 .
  • signals V P1 and V P2 would typically be provided by a switching circuit (or drive circuit).
  • the layout 56 fulfils the dual function of an interconnect (between physical locations) and a coupled inductor circuit. The main advantages are a more efficient use of chip area and a reduction in resistive losses, compared with the separate provision of coupled inductor circuit and interconnect functions.
  • Circuits designed in accordance with this invention typically drive one or more capacitive loads to produce outputs signals, which, in response to one or more input signals, make approximately sinusoidal transitions between a high and a low voltage level.
  • the relative timing of the input signals needs to be correct in relation to the sinusoidal transition time of the output signal(s) for efficient operation.
  • the input signal V C2 is delayed relative to input signal V C1 by time approximately equal to the sinusoidal transition time of the output signal V O .
  • the input signal V C1 makes a first transition at time t1 and the input signal V C2 makes a first transition at time t2.
  • the input signal V C2 could be produced in a number of ways. For example, V C2 could be controlled in response to the level of output signal V O .
  • V C2 could be derived from V C1 via an adjustable delay element which is adjusted in response a characteristic of one or more previous transitions of output signal V O .
  • V C2 could be derived from V C1 via an LC delay element designed to reproduce the required delay.

Claims (27)

  1. Elektronische Treiberschaltung zum Treiben einer kapazitiven Last zwischen Versorgungspotentialen, umfassend
    a. Schaltvorrichtungen zum Schalten von Strom entweder zu oder von zwei Spannungsversorgungsquellen; gekennzeichnet durch:
    b. zwei gekoppelte Induktionsspulen, die wirken, um Energie zu speichern, welche aus den Spannungsversorgungsquellen bezogen wird, wobei die gekoppelten Induktionsspulen elektrisch in Serie miteinander quer zu den Spannungsversorgungsquellen gekoppelt sind, und durch die Schaltvorrichtungen mit denselben verbunden, wobei ein Punkt zwischen den gekoppelten Induktionsspulen für eine Verbindung mit der Last ausgelegt ist; wobei
    c. die gekoppelten Induktionsspulen mit der Last einen LC-Resonator bilden, derart, dass in den Induktionsspulen gespeicherte Energie zu oder von der Last übertragen werden kann, um eine Änderung in der Spannung der Last zu treiben.
  2. Treiberschaltung nach Anspruch 1, welche eine Resonanzinduktionsspule aufweist, welche mit einem gemeinsamen Punkt zwischen den gekoppelten Induktionsspulen verbunden ist.
  3. Elektronische Treiberschaltung zum Treiben zweier kapazitiver Lasten zwischen Versorgungspotentialen, umfassend
    a. Schaltvorrichtungen zum Schalten von Strom entweder zu oder von zwei Spannungsversorgungsquellen; gekennzeichnet durch:
    b. zwei gekoppelte Induktionsspulen, die wirken, um Energie zu speichern, welche aus den Spannungsversorgungsquellen bezogen wird, wobei die gekoppelten Induktionsspulen magnetisch gekoppelt sind, ohne eine direkte elektrische Verbindung, zwischen den Schaltvorrichtungen, und wobei jede der gekoppelten Induktionsspulen mit einer weiteren Induktionsspule verbunden ist, zur Verbindung mit einer jeweiligen kapazitiven Last; wobei
    c. die gekoppelten Induktionsspulen mit der Last einen LC-Resonator bilden, derart, dass in den Induktionsspulen gespeicherte Energie zu oder von der Last übertragen werden kann, um eine Änderung in der Spannung der Last zu treiben.
  4. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei die gekoppelten Induktionsspulen mit der Induktivität verbinden oder einen Teil davon ausmachen, in einem mit der Last gebildeten LC-Resonator.
  5. Treiberschaltung nach Anspruch 4, wobei die gekoppelten Induktionsspulen einen wesentlichen Teil der Induktivität des LC-Resonators bilden.
  6. Treiberschaltung nach einem der vorhergehenden Ansprüche zum Treiben zweier Lasten mit komplementären Signalen.
  7. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei eine, oder beide, der Spannungsquellen eine Spannungsversorgungsschiene ist.
  8. Treiberschaltung nach Anspruch 7, wobei eine, oder beide, der Spannungsquellen einen Speicherkondensator umfasst, welcher auf einem Potential an oder nahe an der Versorgungsschiene gehalten wird.
  9. Treiberschaltung nach Anspruch 8, wobei eine, oder beide, der Spannungsquellen einen Speicherkondensator umfasst, welcher auf einem Potential an oder nahe an der Versorgungsschiene gehalten wird.
  10. Treiberschaltung nach Anspruch 9, wobei eine, oder beide, der Spannungsquellen aus dem/den Speicherkondensator(en) zugeführt wird.
  11. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei eines, oder mehrere, der Schaltvorrichtungen ein MOSFET ist.
  12. Treiberschaltung nach Anspruch 11, wobei eines, oder mehrere, der Schaltvorrichtungen, ein MOSFET-Inverter ist.
  13. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei eines, oder mehrere, der Schaltvorrichtungen Dioden umfasst, durch welche Energie an die Stromversorgung zurückgegeben werden kann.
  14. Treiberschaltung nach einem der vorhergehenden Ansprüche, welche in einer integrierten Schaltung implementiert ist, zum Treiben einer Last innerhalb oder au-ßerhalb der integrierten Schaltung.
  15. Treiberschaltung nach einem der vorhergehenden Ansprüche, ferner umfassend eine Energierückgewinnungsspule, verbunden zum Koppeln mit den gekoppelten Induktionsspulen.
  16. Treiberschaltung nach Anspruch 15, wobei die Energierückgewinnungsspule eine größere Anzahl an Windungen aufweist als jede der gekoppelten Induktionsspulen.
  17. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei die gekoppelten Induktionsspulen wenigstens teilweise aus einer Verdrahtung bestehen.
  18. Treiberschaltung nach einem der vorhergehenden Ansprüche, wobei die gekoppelten Induktionsspulen wenigstens teilweise in einer integrierten Schaltung hergestellt sind.
  19. Treiberschaltung nach einem der vorhergehenden Ansprüche, ferner umfassend eine Klemmschaltung zum Klemmen der Ausgangsspannung der Schaltung an eine Zielspannung.
  20. Treiberschaltung nach einem der vorhergehenden Ansprüche, ferner umfassend einen oder mehrere Gleichstrom-Sperrkondensatoren, zum Verhindern anhaltenden Flie-ßens von Gleichstrom durch die gekoppelten Induktivitäten.
  21. Treiberschaltung nach einem der vorhergehenden Ansprüche, welche von ersten und zweiten Eingangssignalen getrieben wird.
  22. Treiberschaltung nach Anspruch 21, wobei jedes der Eingangssignale ein jeweiliges der Schaltvorrichtungen steuert, wobei jedes Eingangssignal einen aktiven Zustand und einen inaktiven Zustand aufweist.
  23. Treiberschaltung nach Anspruch 21 oder 22, wobei die Wellenform des zweiten Treibersignals eine zeitversetzte Funktion der Wellenform des ersten Treibersignals ist.
  24. Treiberschaltung nach Anspruch 21 oder 22, wobei die Wellenform des zweiten Treibersignals sich nur während eines Zeitraums im inaktiven Zustand befindet, in welchem sich das erste Treibersignal im aktiven Zustand befindet.
  25. Treiberschaltung nach Anspruch 1, wobei der LC-Resonator ferner eine Resonanzinduktionsspule umfasst, wodurch gespeicherte Energie im Wege der Resonanz zwischen den Induktionsspulen und der Spannungsversorgungsquelle und der Last ausgetauscht werden kann, um eine Änderung in der Spannung der Last zu treiben.
  26. Elektronische Treiberschaltung nach Anspruch 25, wobei ein Abschnitt der Resonanzinduktivität durch eine Resonanzinduktionsspule bereitgestellt wird.
  27. Elektronische Treiberschaltung nach Anspruch 25 oder 26, wobei ein Abschnitt der Resonanzinduktivität durch die gekoppelten Induktionsspulen bereitgestellt wird.
EP02764076A 2001-04-24 2002-04-24 Resonante logiktreiberschaltung Expired - Lifetime EP1384325B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0109971 2001-04-24
GBGB0109971.2A GB0109971D0 (en) 2001-04-24 2001-04-24 Electronic logic driver circuit utilizing mutual induction between coupled inductors to drive capacitive loads with low power consumption
PCT/GB2002/001832 WO2002087084A1 (en) 2001-04-24 2002-04-24 Resonant logic driver circuit

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EP1384325B1 true EP1384325B1 (de) 2007-09-26

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US7098703B2 (en) 2006-08-29
DE60222650D1 (de) 2007-11-08
ATE374455T1 (de) 2007-10-15
WO2002087084A1 (en) 2002-10-31
CN1236559C (zh) 2006-01-11
GB0109971D0 (en) 2001-06-13
EP1384325A1 (de) 2004-01-28
CN1516924A (zh) 2004-07-28
US20040145411A1 (en) 2004-07-29

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