Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
  • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/05—Making the transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
  • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
  • H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor

Definitions

• the invention relates to integrated circuits, and more particularly to analog charge storage devices, in particular analog memory points or light sensors.
• Electronic memories usually operate with two logic levels 1 and 0. In the case of a dynamic random access memory (DRAM memory), these levels correspond to the charged state or not of a capacitor. The reading of the memory point is destructive of the state of this memory point because the charges stored in the capacitor are used as read signal. In addition, for reasons of density of the memory point, the capacitive value of the capacitor is low, and it is then impossible to differentiate several charge levels of the capacitor. In addition, the charge of the capacitor, due to the various leakage currents associated with the control devices, decreases and is not stable over time.
• DRAM memory dynamic random access memory
• a DRAM type memory point must, for density reasons, be as small as possible. It consists of an access transistor controlling the charge or discharge of a capacitor. This capacitor must on the one hand have a maximum capacitive value and on the other hand occupy a minimum surface. Currently the capacitor is produced either in the silicon substrate or in the upper interconnection layers of the integrated circuit.
• the capacitor In the first case the capacitor is located next to the access transistor. In the second case, the capacitor occupies a large volume above the transistor, a volume which cannot be used to make interconnections of the integrated circuit. In these two cases, the density of the memory point, that is to say its size, is affected.
• An object of the invention is to propose a device having a minimum surface and capable of storing charges, of offering a very long retention time of the stored charges, of allowing the reading of the stored charges without loss of information as well as the evaluation of the quantity of charges stored in an analog manner.
• One of the aims of the invention is thus to propose the use of such a device as an analog memory point offering a non-destructive reading of the stored information.
• Another object of the invention is to propose the use of such a device, once a matrix, as an image sensor making it possible to transform a light image into analog electrical information. More precisely, the image is transposed into a matrix, each element of which represents, in the form of analog electrical information, an element (pixel) of the original image.
• the writing operations of this matrix are not destructive of the imprint of the previously registered image, which allows the sensor to perform elementary operations such as the superposition of two images.
• the invention therefore provides an integrated circuit, comprising a semiconductor charge storage device comprising at least one elementary storage capacitor and an elementary active component allowing measurement of the stored charges.
• the device comprises a substrate comprising a lower region containing at least one buried capacitive elementary trench forming said elementary storage capacitor, and an elementary box situated above said lower region of substrate and isolated laterally. by a lateral electrical insulation zone.
• the elementary active component is produced in the elementary box or in and on the elementary box, and said capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary box.
• the device according to the invention comprises an elementary active component with a trench-type capacitor buried located not next to the elementary component but under the elementary component.
• the size is therefore reduced.
• the first electrode of the capacitor is the substrate and the second electrode is a conductor filling the trench.
• This capacitor is located below the elementary well of the active elementary component, and is connected to this elementary well by direct contact between the internal electrode of the capacitor and the elementary well.
• the surface of the elementary box-substrate junction is reduced by the presence of the buried capacitor.
• This elementary active component can in particular be a MOSFET transistor, a JFET transistor, or else a resistor.
• the lateral insulation zone is advantageously formed of a trench filled with a dielectric material and has a greater depth than that of the elementary box.
• the zone extending between the capacitive elementary trench and the lateral isolation zone forms an elementary PN junction between the elementary well and said lower substrate region. And the surface of said elementary junction is advantageously less than the contact surface of said capacitive elementary trench with the elementary box.
• the elementary trench comprises an upper zone in contact with the elementary box and having the same type of conductivity as that of the elementary box.
• the substrate is formed of silicon
• the capacitive trench comprises an internal zone of doped silicon, partially enveloped by an insulating wall laterally separating said internal zone from the substrate, and surmounted by the upper zone formed of doped silicon .
• the storage device can be used as an analog memory point.
• the storage device comprises several adjunct elementary active components respectively associated with several capacitive elementary trenches buried in respective electrical contact with several elementary boxes, said lower substrate region forming a box isolation from the rest of the substrate, so as to form an erasable analog memory plane by application of a selected voltage on the isolation box.
• the storage device can also be used as a light sensor.
• the storage device comprises several adjacent elementary active components respectively associated with several capacitive elementary trenches buried in respective electrical contact with several elementary boxes, so as to form a light sensor of which each pixel is formed an elementary active component and the associated elementary trench.
• the methods of manufacturing semiconductor components can destroy the crystal continuity of the surface of part of the initial monocrystalline semiconductor substrate. This is particularly the case when making a trench.
• the semiconductor substrate has, at the location of the trench, a different material without a crystal structure. Consequently, the surface of the part of the substrate occupied by the trench is unusable for producing semiconductor devices.
• the invention also makes it possible to provide a solution to this problem.
• An object of the invention is to allow the production of a monocrystalline substrate allowing the subsequent formation of an epitaxial layer of silicon free from crystalline defects and in which the control transistor (s) of the device will be produced.
• the invention therefore also provides a method of manufacturing an integrated circuit comprising a semiconductor charge storage device comprising an elementary active component, for example a control transistor, and an elementary storage capacitor.
• a) an initial monocrystalline substrate is produced which locally has an elementary capacitive trench emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice
• the initial substrate is hollowed out at the level of the elementary trench
• the crystal lattice is amorphous at the periphery of the recess
• a layer of amorphous material having the same composition is deposited on the structure obtained in the previous step chemical than that of the initial substrate
• e) a thermal annealing of the structure obtained in the previous step is carried out in order to recrystallize the amorphous material in continuity with the monocrystalline network of the initial substrate
• f) an upper layer is grown by epitaxy substrate
• an elementary box located above and in contact with the capacitive elementary trench is defined in said
• the method comprises, before or after step e), a surface planarization step, for example a chemical mechanical polishing.
• a surface planarization step for example a chemical mechanical polishing.
• the definition of the elementary box includes, for example, the production of isolation zones, an implantation and an annealing.
• the amorphization step includes an ion implantation localized around the obvious by a masking operation.
• a first layer of a first material and a second layer of a second material are successively deposited on the initial substrate, then an elementary trench is etched which is fills with a filling material, and in step b), a selective etching is carried out with respect to said second layer, the first layer and an upper part of the filling material of the elementary trench, so as to form lateral cavities and said obviously at the level of the crystal discontinuity, and said second layer is removed.
• the filling of the elementary trench advantageously comprises the following steps:
• FIG. 2 and 3 schematically illustrate two other embodiments of a storage device according to the invention.
• the starting substrate of the process of the invention is illustrated in FIG. La and here comprises an elementary trench.
• the initial substrate 1 is here doped N.
• the elementary trench can be produced, according to an implementation of the method of the invention, by first depositing a layer of silicon oxide 2 on the initial silicon substrate monocrystalline 1.
• the thickness of this layer 2 can vary between 0.01 micron and 1 micron, and is preferably of the order of 2000 ⁇ .
• a layer of silicon nitride 3 is then deposited on the oxide 2.
• the thickness of this layer 3 can also vary between 0.01 micron and 1 micron, and is also preferably of the order of 2000 ⁇ .
• the elementary trench 4 has a depth of approximately 6 ⁇ m and a width, preferably less than 1 ⁇ m, for example equal to 0.3 ⁇ m.
• a controlled thermal oxidation is then carried out so as to deposit on the walls of the elementary trench 4 a layer of silicon oxide 8 with a thickness between 40 and 1000 ⁇ , preferably between 50 and 300 A.
• the device illustrated is obtained in figure la.
• the doping of silicon is carried out in situ.
• a device is obtained as illustrated in FIG. 1b.
• the polycrystalline silicon 9, previously deposited, is then etched at least so as to remove it from the surface of the wafer. Furthermore, this etching is carried out until the level of polycrystalline silicon in the elementary trench 4 is below the surface of the initial substrate 1.
• the following stage consists of a controlled deoxidation, essentially so as to form under the layer of silicon nitride 3 two lateral cavities of given width in the layer of oxide 2 as illustrated in FIG. Part of the silicon oxide 8 is also removed in the trench 4.
• This deoxidation is carried out by isotropic etching with hydrofluoric acid or by isotropic plasma etching with fluorine.
• the device illustrated in FIG. 1a is then obtained on which the trench is lined with a layer of silicon oxide 8 whose height is less than the height of the layer of doped polycrystalline silicon 9 in the elementary trench 4.
• Two cavities lateral of given width appear under the layer of silicon nitride 3 and in the layer of silicon oxide 2.
• the silicon nitride mask 3 is then conventionally removed.
• the discovered silicon is then amorphized.
• the silicon discovered at this stage of the process is the monocrystalline silicon of the substrate 1, as well as the emerging part of polycrystalline silicon doped 9 in the elementary trench 4.
• the simultaneous localized amorphization of regions 6 and 6bis is self-aligned on the elementary trench.
• Amorphization is carried out in a conventional manner by destroying the crystal lattice of the silicon and of the polycrystalline silicon 6bis, for example by implantation of heavy particles such as the ions. In the context of the invention, the implantation of fluoride ions will in particular be preferred.
• a layer of amorphous silicon 7 is deposited over the entire surface of the wafer so as to at least fill the lateral cavities and obviously above the elementary trench 4.
• the amorphous layer 7 therefore has a role of connection between regions 6 and 6bis as well as the filling of the surface.
• the deposition of amorphous silicon is done conventionally at low temperature.
• the device illustrated in FIG. 1d is then obtained, on which in an elementary trench 4 etched in a substrate 1, a block of polycrystalline silicon 9 is partially enveloped in a layer of silicon oxide 8. The height of this block, lower than that of the elementary trench 4, is also less than the height of the envelope of silicon oxide 8.
• This element is surmounted by an amorphous silicon zone comprising the amorphized silicon zones 6 and 6bis and the amorphous silicon 7 deposit.
• Thermal annealing is carried out so as to restore the crystalline structure of the amorphous silicon.
• Thermal annealing makes it possible to recrystallize the amorphous silicon by creating a re-epitaxy of the amorphous silicon 6, 7 from the monocrystalline silicon of the initial substrate 1.
• the restructuring of the monocrystalline silicon network leads to the figure where the previous layer of amorphous silicon now merges with the monocrystalline silicon of the substrate 1.
• the zone 6 is spatially limited, and the border between this zone 6 and the substrate 1 is easily located by ion implantation.
• This border is also a “soft” border, that is to say that the transition from the monocrystalline Si state to the amorphous Si state is very gradual.
• zone 6bis makes it possible to avoid a "rise” of crystalline defects in the monocrystalline layer from polycrystalline silicon.
• a mechanical chemical polishing is then carried out, stopping on the silicon oxide layer 2 in order to remove the layer of recrystallized silicon on the surface of the wafer.
• the silicon oxide layer 2 is then conventionally removed.
• the wafer is subjected to a final chemical mechanical polishing.
• a final substrate 10 is obtained in monocrystalline silicon illustrated in FIG. 1f, the perfectly flat and uniform monocrystalline surface of which allows epitaxial growth without defect in monocrystalline silicon.
• the thickness of the substrate 10 above the elementary trench is of the order of 0.2 microns.
• the substrate also comprises a buried capacitive elementary trench TRC and consisting of highly doped polycrystalline silicon 90 partially surrounded by a wall of silicon oxide 8 separating it laterally from the substrate.
• This zone corresponds to the amorphized polycrystalline silicon zone 6bis as well as to the part silicon
• the localized destruction according to the invention of the crystal lattice before its restructuring is particularly advantageous for capacitive trenches, since it makes it possible to bury the silicon polycrystalline 90 (full capacity) by controlled etching of the flank oxide 8, without the need for an additional oxide.
• the process continues with an epitaxial growth on the surface of the substrate 10, of an upper layer of substrate 12, formed of P-doped silicon (FIG. Lg), and having a thickness of approximately 1 ⁇ m. It is in this layer 12 that the control transistor T of the device DIS will be produced.
• the substrate SB formed of the substrate 10 and of the layer 12, incorporates the capacitive elementary trench TRC More specifically, as illustrated in FIG. 1h, there are produced around the shallow elementary trench TRC, shallow insulating lateral zones STI having approximately l , 5 ⁇ m deep. In the volume of silicon delimited by these STI zones, an elementary CS-doped P-cell is produced by ion implantation followed by diffusion and annealing.
• the implantation is for example a boron implantation at 10 13 at / cm 2 at an energy of 80keV. Annealing takes place, for example, at 950 ° C. for 20 minutes.
• the depth of this elementary caisson CS is such that electrical continuity is ensured between the elementary caisson and the upper zone Ibis of the P-doped elementary trench.
• the depth of the STI zones is sufficient to insulate two adjacent elementary caissons.
• control transistor T here of the NMOS type, is formed in a completely conventional manner. More precisely, after having produced the lateral insulation zones STI, the gate oxide is formed, then the gate polysilicon which is etched so as to form the insulated gate G of the transistor.
• the drain and source regions are produced in a conventional manner by double implantation before and after formation of the ES insulating spacers flanking the grid.
• a conventional siliciding step makes it possible to metallize the drain, source and gate regions so as to allow contact making.
• An NMOS transistor is therefore finally obtained, the elementary well CS of which is isolated from the substrate by an elementary P / N junction and by the dielectric layer 8 of the elementary trench TRC.
• the capacitive elementary trench under the box makes it possible - to produce a MOS transistor close to the minimum dimensions, the CS box of this transistor being directly connected to an electrode of the capacitive elementary trench without using a metallic interconnection level - increasing the capacitive value between the elementary box and the substrate, - the reduction in the surface of the elementary junction “box P / substrate N”, therefore the reduction in the currents of this elementary junction and in particular the leakage currents.
• the device can thus be advantageously used as an analog memory point or as an elementary light sensor.
• the DIS device When the DIS device is used as an analog memory point, it operates with three cycles, namely a write cycle, a cycle for retaining the stored information, and a read cycle.
• the elementary box CS is polarized at a given negative voltage. More precisely, for example, the substrate is polarized at OV, the drain at -IV, and the source and the grid are left floating. Electrons are then injected into the floating CS caisson and polarize it at said negative voltage, for example -IV.
• the charge thus stored is important because the capacitive value of the box vis-à-vis the substrate is high. This charge disappears only very slowly because the leakage currents, in particular those vis-à-vis the substrate, are low.
• control transistor depends directly on the potential of the well.
• the threshold voltage of the transistor increases when the potential of the housing decreases.
• the drain current is a function of the voltage of the well for a given drain voltage. The knowledge of this drain current allows the measurement of the voltage of the box, and consequently the measurement of the quantity of stored charges. This measurement is analog and non-destructive for the charges stored in the floating box.
• FIG. 1a several (for example three) adjacent pairs of transistors T1-T3 and associated buried capacitive trenches TRC 1-TRC3 are shown diagrammatically. Each pair forms a pixel of a light sensor.
• the initial substrate is P-doped. Consequently, a double box structure is provided, comprising a N-doped CD diffusion isolation box.
• the elementary boxes CS 1 -CS3 of the transistors are then formed as indicated above and are mutually separated by STI isolation zones.
• An additional CSN box, type N, is also produced by implantation and enables the CD broadcast box to be polarized.
• the matrix sensor with several pixels works with three cycles, namely a precharge cycle, a cycle of taking into account the light information, and a read cycle.
• a precharge cycle a cycle of taking into account the light information
• a read cycle a cycle of taking into account the light information
• the potential of the well of each pixel can be fixed as explained previously by the polarization of the drain (for example -I V).
• Another advantageous possibility for this type of sensor consists in biasing the source, the gate and the drain of the transistor at 0V, and in biasing the well CSN (therefore the wells CS 1 - CS3) successively at -IV then at 0V.
• each pixel When the light information is taken into account, the source, the gate and the drain of each transistor are left floating, and the CSN well is polarized at 0V. When a bright image is formed on the surface of the sensor, each pixel is lit differently. In particular, the luminous flux increases the leakage current of each Csi / CD box junction. This results in an increase in the potential of each elementary well Csi as a function of the illumination.
• the previously formed image is read by measuring the voltage of the elementary wells Csi through the current of each control transistor. This measurement is analog and non-destructive. The measurement of the light intensity is therefore analog.
• MOS transistor As an elementary active component, it would be possible to provide any active component allowing a measurement of the stored charges, in particular a resistance or an effect transistor. field junction (JFET transistor).
• JFET transistor field junction
• Figure 2 schematically illustrates a charge storage device whose elementary active component is a resistor.
• This resistance R is for example a layer of silicon doped N, whose resistive value depends on the number of carriers (electrons) in this resistance.
• concentration of dopants is less than 5 10 18 at / cm 3 , the difference of potential between the resistance and the CS elementary box will create a depletion (depletion) of the resistance in carriers.
• the value of this resistance is therefore correlated with that of the potential of the elementary box.
• the value of the resistance which can easily be measured in a conventional manner is generally an image of the potential of the elementary well and therefore of the quantity of charges stored.
• This device is therefore very simple to make and economical.
• FIG. 3 schematically illustrates a charge storage device whose elementary active component is a JFET transistor.
• the resistive layer doped N under the gate of the transistor is pinched by the potential of the gate and by the potential of the elementary well CS.
• the measurement of the current flowing in the JFET transistor provides an image of the quantity of charges stored.
• This device offers the advantage of being more efficient, in particular in terms of sensitivity, than that illustrated in FIG. 2.

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