Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
  • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F2213/0016—Inter-integrated circuit (I2C)
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Definitions

• Cooperation and communication in an IC environment includes the ability of an IC to send data/information to other ICs typically in response to a query signal from another IC and/or to receive data/information from other ICs. This is typically achieved by providing a communication link or channel between the ICs such that the ICs are in communication with one another.
• One way to efficiently provide the communication link is via a bus structure.
• a bus structure is essentially a common communication channel for the plurality of ICs in the electronic device.
• I2C bus Inter Integrated Circuit bus
• the l 2 C bus system/structure operates on an l 2 C protocol that allows the plurality of ICs to be connected to and in communication with one another over a bus structure.
• I 2 C was developed by Phillips Semiconductor to provide a way to connect (i.e. provide communication between) a central processing unit (CPU) and associated peripheral ICs within a television environment.
• I 2 C is, in particular, a serial bus system/protocol that allows various ICs within a device to communicate with one another.
• each IC i.e. a device, driver, memory, or complex function IC/chip
• the l 2 C system can then send and/or receive data to/from a particular IC by using its address.
• the designer In maintaining the integrity of l 2 C, when a new IC is developed, the designer must apply for and obtain a unique IC address for and from the l 2 C authorizing/issuing entity (i.e. Phillips Semiconductor). This allow for the l 2 C system to grow as more types of addressable devices/ICs are uniquely registered.
• the present invention is an apparatus, system and method which provides for the modification or programmability of an address of an l 2 C device.
• the modification or programming may be accomplished via an input signal received by an I/O terminal of the device.
• the present invention also provides for substantially simultaneous modification of first and second addresses of respective first and second l 2 C devices.
• the modification or programming may be accomplished via an input signal received by an I/O terminal coupled to both the first and second l 2 C devices.
• the present invention obviates bus contention problems in an l 2 C bus/protocol system due to IC address conflict through the ability to modify (change) or program the l 2 C address. Modification or programming can be accomplished during the design phase or thereafter via software. By permitting programming an ICs address, an address may be chosen that obviates an address conflict. The address of the IC or components thereof is determined by a signal applied to an I/O pin of the IC.
• the present invention is an integrated circuit system.
• the integrated circuit system comprises a first device with a first l 2 C interface, the first l 2 C interface having a first defined address, a second device with a second l 2 C interface, the second l 2 C interface having a second defined address, and means for substantially simultaneously changing the first and second defined addresses.
• the present invention is a method of modifying first and second defined addresses in an integrated circuit system wherein the integrated circuit system has a first device with a first l 2 C interface having a first defined address, and a second device with a second l 2 C interface having a second defined address.
• the method includes a) providing a control signal to a first address input of the first l 2 C interface, b) providing the control signal to a second address input of the second l 2 C interface; and c) substantially simultaneously changing the first defined address and the second defined address in response to the control signal.
• FIG. 1 is a diagram of an exemplary integrated circuit system in communication with one another via the l 2 C bus/protocol system in which the present invention may be utilized;
• Fig. 2 is an upper level block diagram of one of the integrated circuits of the exemplary integrated circuit system of Fig. 1 , the chosen integrated circuit having two internal blocks of circuitry/logic each of which has been assigned and configured for a particular address in the l 2 C bus/protocol system and which has been modified in accordance with the principles of the present invention as disclosed herein;
• Fig. 3 is a simplified block diagram of an alternate embodiment of an addressable IC such as the IC of Fig. 2, in accordance with the principles of the present invention; and
• Fig. 4 is a table illustrating a manner of making l 2 C addresses modifiable or programmable.
• a system that represents any system, but particularly an electrical system, in which a plurality of devices are in communication with each other via a common network, particularly a bus structure.
• a common network particularly a bus structure.
• Fig. 1 is an electrical system and, more particularly, an integrated circuit system having a controller IC and a plurality of slave ICs all in communication with each other via a system bus and a bus management system, the principles of the present invention are applicable to other similar systems of an electrical and/or non-electrical nature.
• the system 10 depicted in Fig. 1 is particularly an l 2 C bus/protocol system (l 2 C system).
• the l 2 C system 10 includes a command issuing IC 12 in communication with an l 2 C bus, generally designated 18.
• the command issuing IC 12 may be known as a main IC which is operable to initiate data transfers on the bus 18, such as a CPU.
• the l 2 C system 10 further includes a plurality of slave ICs, generally designated 20, that are in communication with the l 2 C bus 18.
• the l 2 C bus consists of a Serial CLock line (SCL) 14 and a Serial DAta line (SDA) 16.
• the SCL 14 is coupled to an I/O pin of the command issuing IC 12 and to an I/O pin of each slave IC 20 for supplying a serial clock signal to each slave IC 20.
• the SDA 16 is coupled to another I/O pin of the main unit and to another I/O pin of each slave IC 20 for data transfer and general communication.
• the command issuing IC 12 controls/generates the system clock and thus the SCL 14 has a single-headed arrow to designate the nature of the clock signal line.
• the SDA is also bi-directional and thus has a double-headed arrow to designate the nature of the serial data line.
• Each of the slave ICs 20 is operable to receive protocol commands from the command issuing IC 12 and respond appropriately.
• each slave IC 20 is assigned a unique address.
• the unique address is hardwired into the respective slave IC 20 typically within an l 2 C bus interface section/circuitry/block.
• the internal address of each slave IC 20 is thus fixed.
• Some of the slave ICs 20 have only one fixed address.
• Some of the slave ICs have more than one fixed address, typically due, at least in part, to having more than one internal l 2 C bus interface or integrated circuitry section each of which has a previously assigned l 2 C address.
• the system 10 of Fig. 1 is only exemplary of an environment/application in which the present invention may be utilized.
• the present invention is applicable to and used in any system of ICs that utilize the l 2 C protocol/bus structure/system.
• the present invention may be used in other similar protocol/bus structures/systems.
• the type of IC and IC system in which the present invention is utilized may take many forms and/or perform many functions.
• the exemplary system 10 of Fig. 1 may be considered as the operation circuitry of a television signal processing device.
• a multiple address IC, operable to process television signals, is designated 20UL in Fig. 1.
• the exemplary IC 20U L provides television signal processing for a variety of formats of television signals from a variety of sources, and is known as a Universal Link IC (UL IC).
• the UL IC 20U L is adapted/operable (i.e. includes appropriate circuitry/logic) to provide satellite television (digital) signal processing, terrestrial (including cable distribution) digital television signal processing, and terrestrial (including cable distribution) analog television signal processing in addition to other associated television signal processing.
• These analog and digital signals may be provided in various formats and modulation schemes.
• ICs utilizing the l 2 C protocol/bus that are adapted to perform other functions may utilize the principles presented herein.
• Examples of other ICs/slave devices are designated 20a, 20b, 20c ... 20N-I, 20 N in Fig. 1. They represent all ICs or other addressable devices and/or components in communication with the bus 18. It is assumable that each of the ICs/slave devices 20a, 20b, 20c ... 20 N . ⁇ , 20 N have at least one address (an l 2 C address). In any IC system such as that shown in Fig. 1 , however, there may be address problems wherein two (or more) ICs share the same fixed/assigned address. This may arise during design of an IC that utilizes at least two blocks of integrated circuitry/logic having previously assigned addresses.
• same assigned addresses are obviated with the present invention during the design phase by hardwire programming or modification of at least one of the addresses.
• Same assigned addresses may also arise in the context of devices or software components being added to the IC system during operation thereof. In this case, same assigned addresses may be obviated by having software modification or programmability of the addresses.
• the present invention provides a programmable l 2 C address in an IC.
• the programmable nature of the address even though a fixed address has been previously assigned to the block of integrated circuitry, allows a designer of IC systems to change the "fixed" address of the IC to another address not otherwise used in the system.
• a top level block diagram of the Universal Link (UL) IC 20U L is shown that is modified according to the principles of the present invention.
• the UL IC 20UL is an integrated circuit chip of mixed signal design, i.e.
• the UL IC 20UL also incorporates or integrates various analog and digital signal processing functions that were previously accomplished by separate ICs into a single IC.
• the integrated circuitry or blocks comprising the separate ICs or an interface section thereof were thus assigned addresses under the l 2 C protocol/system.
• the blocks or sections retain their previously-assigned fixed address after consolidation because the design of these blocks is adopted without change from the design of the prior separate ICs, including without changing the design of the l 2 C interface section of each block.
• the UL IC 20UL inherently has two addresses. However, in accordance with the present invention, the addresses of the sections of the UL IC 20UL are able to be changed. In particular, one bit of the chip address is controlled by a control signal in order to designate or change the address to which the device will respond.
• Universal Link IC 20UL is only representative of an integrated circuit/circuit chip that utilizes the l 2 C protocol/bus and that the principles presented herein are applicable to all types of integrate circuits and/or integrated circuit systems that utilize the l 2 C protocol/bus.
• the Universal Link IC 20UL includes three main sections, namely a "Satlink” section for demodulating satellite transmitted television signals, generally designated 30, a "VSB (Vestigal SideBand) link” section for demodulating terrestrially transmitted general digital and/or digital high definition (HDTV) signals (of which the HDTV signal can be modulated via any type of digital modulation scheme), generally designated 32, and a "DCD” section that provides switching, chroma demodulation, and other signal processing of NTSC (analog) signals, generally designated 34.
• a "Satlink” section for demodulating satellite transmitted television signals
• VSB (Vestigal SideBand) link” section for demodulating terrestrially transmitted general digital and/or digital high definition (HDTV) signals (of which the HDTV signal can be modulated via any type of digital modulation scheme) signals (of which the HDTV signal can be modulated via any type of digital modulation scheme)
• DCD digital high definition
• the Universal Link IC 20 UL also includes a plurality of I/O (Input/Output) pins, some of which are labeled by text in Fig. 2.
• the I/O pins extend to the exterior of the IC package or chip.
• the UL IC 20U L includes a first l 2 C bus/micro interface section 40 that is in communication with the l 2 C bus 18 and an internal bus 44.
• the first l 2 C bus/micro interface 40 is essentially a slave device (IC block or section) and includes appropriate circuitry/logic to provide communication between the other slave ICs 20 and the command issuing IC 12 that are in communication with the l 2 C bus 18, and the various portions of the Satlink section/circuitry/logic 30.
• the first l 2 C bus/micro interface 40 also has a previously assigned l 2 C address that is fixed internal thereto.
• the various blocks or portions of the Satlink section 30 communicate with the l 2 C bus/micro interface 40 via the internal bus 44.
• An address bit input of the l 2 C bus/micro interface 40 (or other address receiving section/block) is coupled via a line 52 to an I/O pin 60 of the UL IC 20 U .
• the UL IC 20I J L further includes a second l 2 C bus/micro interface section 42 that is in communication with the l 2 C bus 18 and an internal bus 46.
• the second l 2 C bus/micro interface 42 is essentially a slave device (IC block or section) and includes appropriate circuitry/logic to provide communication between the other slave ICs 20 and the command issuing IC 12 that are in communication with the l 2 C bus 18, and the various portions of the VSB/DCD sections/circuits/logic 32 and 34.
• the second l 2 C bus/micro interface 42 also has a previously assigned l 2 C address that is fixed internal thereto.
• the various blocks or portions of the VSB and DCD sections 32 and 34 communicate with the l 2 C bus/micro interface 42 via the internal bus 46.
• An address bit input of the l 2 C bus/micro interface 42 (or other address receiving section/block) is coupled via a line 54 to an I/O pin 60 of the UL IC 20U L
• the l 2 C bus/micro interfaces 40 and 42 are in communication with the l 2 C bus
• the address of the l 2 C bus/micro interface 40 is modifiable or programmable.
• the address of the l 2 C bus/micro interface 42 is modifiable or programmable.
• the l 2 C bus/micro interface 40 includes a control line 52 that is in communication with the address input of the l 2 C bus/micro interface 40 and an I/O pin or terminal 60.
• the I/O pin 60 is in communication with the l 2 C bus 18.
• the l 2 C bus/micro interface 42 includes a control line 54 that is in communication with the address input of the l 2 C bus/micro interface 42 and the I/O pin 60.
• modification or programming of the respective addresses for the l 2 C bus/micro interfaces 40 and 42 is accomplished by supplying a control signal via the I/O pin 60.
• the I 2 C bus/micro interfaces 40 and 42 are responsive to the control signal such that their respective addresses are substantially simultaneously modified or programmed.
• this is accomplished by coupling the control line 52 from the I/O pin 60 to an address input of the l 2 C bus/micro interface 40 and coupling the control line 54 from the I/O pin 60 to an address input of the l 2 C bus/micro interface 42.
• the control signal provided to the I/O pin 60 thus modifies or programs the addresses of the l 2 C bus/micro interfaces 40 and 42 via the control lines 52 and 54. More particularly, the control line 52 is coupled to the l C bus/micro interface 40 such that one bit of the address of the l 2 C bus/micro interface 40 is modified or programmed by the control signal.
• control line 54 is coupled to the l 2 C bus/micro interface 42 such that one bit of the address of the l 2 C bus/micro interface 42 is modified or programmed by the control signal. Since the control lines 52 and 54 are coupled to the same I/O pin 60, the addresses of the l 2 C bus/micro interfaces 40 and 42 are modified or programmed together.
• the table 90 of Fig. 4 sets forth an illustration of the above principles and reference is now made thereto. It should be appreciated that while the table 90 refers to the Universal Link IC 20UL discussed above with respect to Figs. 2 and 3, the principles are applicable to all types of devices or integrated circuits that utilize the l 2 C system.
• the column 92 labeled "Section" refers to the UL IC 20UL Satlink block 30 and, more particularly, to the l 2 C bus/micro interface 40 thereof.
• the Satlink block 30 is representative of any device addressable in the l 2 C system.
• the column 92 labeled "Section” refers to the UL IC 20UL VSB/DCD block 32/34 and, more particularly, to the l 2 C bus/micro interface 42 thereof.
• the VSB/DCD block 32/34 is representative of any device addressable in the l 2 C system. Therefore, the below discussion is applicable to all types of l 2 C devices and not applicable only to the Universal Link IC 20UL.
• the table 90 shows the four (4) possible addresses for two l 2 C devices or slaves, denoted by the rows 93, 95, 97, and 99. Specifically, one address is for a Satlink write (i.e.
• one address is for a Satlink read (i.e. reading data from the Satlink block 30 via the bus), one address is for a VSB/DCD write (i.e. writing data to the VSB/DCD block 32/34 via the l 2 C bus), and another address is for a VSB/DCD read (i.e. reading data from the VSB/DCD block 32/34 via the l 2 C bus).
• Column 98 indicates the full address for the particular sections when the "P" bit (programmable bit) is "0" or low (the first full address) and when the "P" bit is "1" or high (the full address in parentheses).
• the addresses for the Satlink section 30 and the VSB/DCD section 32/34 consist of seven bits (which can be denoted B 7 , Be, B5, B 4 , B3, B , and B-i, beginning with the most significant bit to the second least significant bit) plus an eighth bit (denoted Bo) reserved for indicating a read (R) or write (W) condition.
• the eight bits, B 7 , Be, B 5 , B 4 , B 3 , B 2 , Bi and Bo combine to form a full eight bit address, column 98, in hexadecimal.
• the least significant bit (Isb), Bo, column 96, of the address is reserved for R/W indication.
• one of the seven bits (B 7 , Be, B 5 , B 4 , B 3 , B 2 ,and Bi) of the eight bit address may be modified or programmed. This is indicated in the l 2 C Chip address column 94 of the table 90 by the "P" designation.
• the "P” bit may be a zero/low ("0") or a one/high ("1") depending on which full address is to be utilized for the address of the particular device.
• a first address is defined for the particular l 2 C device. If the "P" is tied high, a second address is defined for the particular l 2 C device.
• the choice as to which address is utilized may be hardwired into the system, as by tying the I/O pin 60 either high or low, or may be variable via software, e.g. by coupling the "P" bit pin of the IC to a software- controllable port of a control device such as a microcomputer.
• the two addresses are modified, programmed, or changed substantially simultaneously.
• any l 2 C system of two or more l 2 C devices when the same "programmable" bit or bits is/are chosen, the two l 2 C devices will have their addresses modified at substantially the same time.
• bit B 2 is shown as the "P" bit, it should be appreciated that any of the seven bits B7, Be, B 5 , B 4 , B 3 , B 2 ,and B-i, or any one of the bits not reserved for other purposes, may be the "P" bit.
• two l 2 C devices such as the l 2 C bus/micro interfaces (l 2 C slaves #1 & #2 in Fig. 3) 40 and 42, are interconnected so as to receive a common control signal and change their address substantially simultaneously.
• the programmable or modifiable bit "P" of the l 2 C addresses for the respective is the same for both the Satlink section 30 via the l 2 C bus/micro interface 40 and the VSB/DCD section 32/34 via the l 2 C bus/micro interface 42, the two addresses are modified, programmed, or changed substantially simultaneously.
• the Satlink write chip address shows the address used to indicate a write data/information to the l 2 C bus/micro interface 40 of the Satlink section 30.
• the bits B 7) Be, B 5 , B 4 , B 3 for the Satlink write chip address are "01010", while the bit B ⁇ is "0"
• the R W bit, B 0 is "0" indicating a write (W).
• the Satlink read chip address row 95, shows the address used to indicate a read data/information to the l 2 C bus/micro interface 40 of the Satlink section 30.
• the bits B 7 , B 6 , B 5 , B 4 , B 3 for the Satlink read chip address are "01010", while the bit Bi, is "0"
• the R/W bit, B 0 is "1” indicating a read (R).
• the VSB/DCD write chip address shows the address used to indicate a write data/information to the l 2 C bus/micro interface 42 of the VSB/DCD section 32/34.
• the bits B 7 , B 6 , B 5 , B 4 , B 3 for the VSB/DCD write chip address are "01010", while the bit Bi, is "1"
• the R/W bit, B 0 is "0" indicating a write (W).
• the VSB/DCD read chip address row 99, shows the address used to indicate a read data/information to the l 2 C bus/micro interface 42 of the VSB/DCD section 32/34.
• the bits B 7 , B 6 , B 5 , B 4> B 3 for the VSB/DCD read chip address are "01010", while the bit B 1( is "1”
• the R/W bit, B 0 is "1” indicating a read (R).
• the integrated circuitry of the various sections may also be thought of in terms of blocks of integrated circuits. As such, these blocks may be merged onto the same IC substrate or chip to produce a single IC.
• the UL IC 20IJL integrates first and second slave devices 40 and 42 (i.e. the l 2 C bus/micro interfaces) which is representative of any type of l 2 C integrated IC.
• the first and second devices may comprise respective first and second sections of a single IC.
• the l 2 C devices may be separate.
• the I/O pin 60 is shown connected to other circuitry/logic via line 72.
• the other circuitry/logic 72 is representative of the generation of a control signal by software or other logic such that the addresses of the l 2 C slaves #1 and #2, change in accordance with the principles presented above.
• the generation of the control signal may take many forms. While this invention has been described as having a preferred design and/or configuration, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Bus Control (AREA)
• Communication Control (AREA)
• Small-Scale Networks (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=24667065

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (8)

Family Cites Families (1)

• 2001
  • 2001-09-13 EP EP01968840A patent/EP1323048A2/en not_active Withdrawn
  • 2001-09-13 JP JP2002529383A patent/JP2004510228A/ja not_active Withdrawn
  • 2001-09-13 WO PCT/US2001/028585 patent/WO2002025449A2/en not_active Application Discontinuation
  • 2001-09-13 MX MXPA03002282A patent/MXPA03002282A/es unknown
  • 2001-09-13 KR KR10-2003-7003778A patent/KR20030033063A/ko not_active Application Discontinuation
  • 2001-09-13 AU AU2001289054A patent/AU2001289054A1/en not_active Abandoned
  • 2001-09-13 CN CN01815924A patent/CN1461440A/zh active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events