MXPA03002282A - Circuito integrado con direccion programable en un ambiente izc. - Google Patents

Circuito integrado con direccion programable en un ambiente izc.

Info

Publication number
MXPA03002282A
MXPA03002282A MXPA03002282A MXPA03002282A MXPA03002282A MX PA03002282 A MXPA03002282 A MX PA03002282A MX PA03002282 A MXPA03002282 A MX PA03002282A MX PA03002282 A MXPA03002282 A MX PA03002282A MX PA03002282 A MXPA03002282 A MX PA03002282A
Authority
MX
Mexico
Prior art keywords
integrated circuit
programmable address
programmable
address
integrated
Prior art date
Application number
MXPA03002282A
Other languages
English (en)
Inventor
David Lawrence Albean
Original Assignee
Thomson Licensing Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa filed Critical Thomson Licensing Sa
Publication of MXPA03002282A publication Critical patent/MXPA03002282A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
MXPA03002282A 2000-09-19 2001-09-13 Circuito integrado con direccion programable en un ambiente izc. MXPA03002282A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66469700A 2000-09-19 2000-09-19
PCT/US2001/028585 WO2002025449A2 (en) 2000-09-19 2001-09-13 Integrated circuit having a programmable address in an i2c environment

Publications (1)

Publication Number Publication Date
MXPA03002282A true MXPA03002282A (es) 2003-06-24

Family

ID=24667065

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA03002282A MXPA03002282A (es) 2000-09-19 2001-09-13 Circuito integrado con direccion programable en un ambiente izc.

Country Status (7)

Country Link
EP (1) EP1323048A2 (es)
JP (1) JP2004510228A (es)
KR (1) KR20030033063A (es)
CN (1) CN1461440A (es)
AU (1) AU2001289054A1 (es)
MX (1) MXPA03002282A (es)
WO (1) WO2002025449A2 (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1610896A (zh) * 2001-12-28 2005-04-27 皇家飞利浦电子股份有限公司 通信系统
US20080270654A1 (en) * 2004-04-29 2008-10-30 Koninklijke Philips Electronics N.V. Bus System for Selectively Controlling a Plurality of Identical Slave Circuits Connected to the Bus and Method Therefore
JP4679310B2 (ja) * 2005-09-06 2011-04-27 株式会社リコー 画像形成装置
JP5314563B2 (ja) * 2009-10-22 2013-10-16 旭化成エレクトロニクス株式会社 装置間通信システムおよび通信装置
US9710422B2 (en) 2014-12-15 2017-07-18 Intel Corporation Low cost low overhead serial interface for power management and other ICs
JP6254517B2 (ja) * 2014-12-22 2017-12-27 富士通フロンテック株式会社 媒体取扱装置
US10268614B2 (en) 2016-04-19 2019-04-23 Nokia Of America Corporation Method and apparatus for a segmented on-chip digital interface block
CN108681517B (zh) * 2018-05-09 2020-09-01 广州计量检测技术研究院 变换i2c器件地址的方法及系统
FR3097987A1 (fr) * 2019-06-26 2021-01-01 STMicroelectronics (Alps) SAS Procede d’adressage d’un circuit integre sur un bus et dispositif correspondant

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus

Also Published As

Publication number Publication date
EP1323048A2 (en) 2003-07-02
AU2001289054A1 (en) 2002-04-02
CN1461440A (zh) 2003-12-10
WO2002025449A2 (en) 2002-03-28
JP2004510228A (ja) 2004-04-02
WO2002025449A3 (en) 2003-02-20
KR20030033063A (ko) 2003-04-26

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