EP1321843B1 - Circuit de source de courant - Google Patents

Circuit de source de courant Download PDF

Info

Publication number
EP1321843B1
EP1321843B1 EP02102824A EP02102824A EP1321843B1 EP 1321843 B1 EP1321843 B1 EP 1321843B1 EP 02102824 A EP02102824 A EP 02102824A EP 02102824 A EP02102824 A EP 02102824A EP 1321843 B1 EP1321843 B1 EP 1321843B1
Authority
EP
European Patent Office
Prior art keywords
mos field
effect transistor
current
output
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP02102824A
Other languages
German (de)
English (en)
Other versions
EP1321843A1 (fr
Inventor
Jochen Rudolph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Intellectual Property and Standards GmbH
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property and Standards GmbH, Koninklijke Philips Electronics NV filed Critical Philips Intellectual Property and Standards GmbH
Publication of EP1321843A1 publication Critical patent/EP1321843A1/fr
Application granted granted Critical
Publication of EP1321843B1 publication Critical patent/EP1321843B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26Current mirrors
    • G05F3/262Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a current source circuit, in which a first and a second MOS field effect transistor form a current mirror circuit, wherein the first MOS field effect transistor via a cascode-connected third MOS field-effect transistor a reference current can be supplied and the drain electrode of a with the second MOS field effect transistor in cascode fourth MOS field effect transistor has an output forms.
  • a simple current mirror circuit consists of two transistors, in particular MOS field-effect transistors, whose source and gate electrodes are connected to each other are. Further, the gate electrode and the drain electrode of the one transistor are connected to each other connected and are acted upon by a reference current. The drain elec trode of the other MOS field effect transistor can then be the desired output current be removed. However, this is from the other MOS field effect transistor - im following also called output transistor - voltage depends, since its Parameters are voltage-dependent.
  • the object of the invention is to provide a current source circuit, which in a large Output voltage range has a high output impedance.
  • the extended-drain MOS field-effect transistor is an extended-drain-well-MOS field-effect transistor and that the further MOS field-effect transistor is a p-channel MOS field-effect transistor is.
  • the current source circuit according to the invention has the advantage of a high output impedance over a very large output voltage range, the output voltage can exceed the operating voltage allowed for this technology. To reach These properties do not require additional mask steps for special high-voltage transistors needed. Furthermore, the current source circuit according to the invention can also be operated at an output voltage higher than the operating voltage of the rest Circuit is. In addition, the current source circuit according to the invention has a high accuracy of the current mirror ratio in the operating voltage, output voltage and temperature range.
  • the current source circuit according to the invention serves as a current mirror when the reference current is supplied from the outside.
  • the inventive Current source circuit is also a highly accurate power source.
  • the current source circuit according to the invention has the advantage that, in contrast to other known circuits is not destroyed when the output transistor a Voltage is applied while the circuit itself, so the control amplifier and more Circuit elements are not yet supplied with an operating voltage.
  • the current source circuit according to the invention has the advantage that they are in highly integrated Standard CMOS technologies can be used. By avoiding the hot-carrier effect At high output voltages also increases the life of the power source scarf tung.
  • An advantageous embodiment of the current source circuit according to the invention exists in that at least one diode connected with the further MOS field-effect transistor MOS field effect transistor is connected in series.
  • Another advantageous embodiment is designed such that the output of the control amplifier via a resistor to the gate electrode of the fourth MOS field-effect transistor is connected, wherein it is preferably provided that the variable gain amplifier is formed by an operational transconductance amplifier.
  • the variable gain amplifier is formed by an operational transconductance amplifier.
  • Extended-drain MOS field-effect transistors which also lightly doped drain n-well transistor or lightly doped drift region transistor, for example, are described in: Y.Q. Li, C.A.T. Salama, M. Seufert, M. King “Submicron BiCMOS compatible highvoltage MOS transistor ", ISPSD Proc., 1994, pp. 355-359.
  • the transistors are formed as n-channel MOS field-effect transistors.
  • a first MOS field effect transistor 1 and a second MOS field effect transistor 2 provide the actual current mirror, the supplied via an input 5, a reference current Iin can be.
  • a current mirror circuit is known per se and needs in connection to be explained in detail with the present invention. It is, however briefly mentioned that the output 6 removable current Iout in a by Transistor geometries certain ratio to the reference current Iin stands. To the effect is different high voltages at the input 5 and at the output 6 to reduce a third transistor 3 having a bias voltage applied at 14 and a fourth transistor the first and second transistors in each case in cascode, wherein the MOS field effect transistor 4 in the following also called output transistor.
  • an OTA (Operational transconductance amplifier) 7 the two source voltages the cascode transistors 3, 4 compared with each other, whereby a control signal arises, which is supplied via a resistor 8 of the gate electrode of the output transistor 4 becomes.
  • a MOS field effect transistor 9 is connected as a capacitance between the output of the OTA 7 and ground potential.
  • Embodiment protects the series connection of a p-channel MOS field effect transistor 10 and the two connected as diodes n- or p-channel MOS field effect transistors 11 and 12, the output transistor 4 in the event that a voltage at the output 6 is already present, while the supplied at 13 operating voltage (still) not available is.
  • the transistor 10 receives 0V as the gate potential and switches over the MOS field-effect transistors 11, 12, the gate-drain voltage of the output transistor 4 on a value lower than the gate oxide breakdown voltage. This serves the resistance 8 for decoupling the OTA output. After starting the operating voltage at 13 turns off the MOS field effect transistor 10, so that the function of the cascode control is no longer affected.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Control Of Amplification And Gain Control (AREA)

Claims (5)

  1. Circuit de source de courant, un premier et un deuxième transistors à effet de champ MOS formant un circuit de miroir de courant, dans lequel un courant de référence peut être amené au premier transistor à effet de champ MOS par l'intermédiaire d'un troisième transistor à effet de champ monté en cascade, l'électrode de drain d'un quatrième transistor à effet de champ MOS monté en cascade avec le deuxième transistor à effet de champ MIS forme une sortie et les électrodes de source des troisième (3) et quatrième (4) transistors à effet de champ MOS sont raccordées aux entrées d'un amplificateur de réglage (7) dont la sortie est reliée avec l'électrode de grille du quatrième transistor à effet de champ MOS (4), caractérisé en ce que le quatrième transistor à effet de champ MOS (4) est un transistor à effet de champ MOS à drain étendu et que l'électrode de drain et l'électrode de grille du quatrième transistor à effet de champ MOS (4) sont reliées par l'intermédiaire d'un transistor à effet de champ (10) supplémentaire dont l'électrode de grille est alimentée en une tension de fonctionnement pour le circuit.
  2. Circuit de source de courant selon la revendication 1,
    caractérisé en ce que le transistor à effet de champ MOS à drain étendu est un transistor à effet de champ MOS à caisson n et drain étendu (4) et que le transistor à effet de champ MOS supplémentaire est un transistor à effet de champ MOS à canal p (10).
  3. Circuit de source de courant selon la revendication 2,
    caractérisé en ce qu'au moins un transistor à effet de champ MOS monté en diode (11, 12) est monté en série avec le transistor à effet de champ MOS (10) supplémentaire.
  4. Circuit de source de courant selon l'une des revendications précédentes,
    caractérisé en ce que la sortie de l'amplificateur de réglage (7) est relié par l'intermédiaire d'une résistance (8) avec l'électrode de grille du quatrième transistor à effet de champ MOS (4).
  5. Circuit de source de courant selon l'une des revendications précédentes,
    caractérisé en ce que l'amplificateur de réglage est formé par un amplificateur à transconductance opérationnel (7).
EP02102824A 2001-12-21 2002-12-19 Circuit de source de courant Expired - Lifetime EP1321843B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10163633A DE10163633A1 (de) 2001-12-21 2001-12-21 Stromquellenschaltung
DE10163633 2001-12-21

Publications (2)

Publication Number Publication Date
EP1321843A1 EP1321843A1 (fr) 2003-06-25
EP1321843B1 true EP1321843B1 (fr) 2005-12-14

Family

ID=7710634

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02102824A Expired - Lifetime EP1321843B1 (fr) 2001-12-21 2002-12-19 Circuit de source de courant

Country Status (5)

Country Link
US (1) US6690229B2 (fr)
EP (1) EP1321843B1 (fr)
JP (1) JP4157928B2 (fr)
AT (1) ATE313109T1 (fr)
DE (2) DE10163633A1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2796781A1 (fr) 1999-07-20 2001-01-26 St Microelectronics Sa Dimensionnement d'un systeme a transpondeur electromagnetique pour un fonctionnement en hyperproximite
US7049935B1 (en) 1999-07-20 2006-05-23 Stmicroelectronics S.A. Sizing of an electromagnetic transponder system for a dedicated distant coupling operation
FR2804557B1 (fr) * 2000-01-31 2003-06-27 St Microelectronics Sa Adaptation de la puissance d'emission d'un lecteur de transpondeur electromagnetique
FR2808941B1 (fr) * 2000-05-12 2002-08-16 St Microelectronics Sa Validation de la presence d'un transpondeur electromagnetique dans le champ d'un lecteur a demodulation d'amplitude
FR2808945B1 (fr) * 2000-05-12 2002-08-16 St Microelectronics Sa Evaluation du nombre de transpondeurs electromagnetiques dans le champ d'un lecteur
FR2808946A1 (fr) * 2000-05-12 2001-11-16 St Microelectronics Sa Validation de la presence d'un transpondeur electromagnetique dans le champ d'un lecteur
FR2809235A1 (fr) * 2000-05-17 2001-11-23 St Microelectronics Sa Antenne de generation d'un champ electromagnetique pour transpondeur
FR2809251B1 (fr) * 2000-05-17 2003-08-15 St Microelectronics Sa Dispositif de production d'un champ electromagnetique pour transpondeur
FR2812986B1 (fr) * 2000-08-09 2002-10-31 St Microelectronics Sa Detection d'une signature electrique d'un transpondeur electromagnetique
US20030169169A1 (en) * 2000-08-17 2003-09-11 Luc Wuidart Antenna generating an electromagnetic field for transponder
US7071785B2 (en) * 2003-10-22 2006-07-04 Broadcom Corporation Use of a thick oxide device as a cascode for a thin oxide transcoductance device in MOSFET technology and its application to a power amplifier design
US7071769B1 (en) 2004-02-27 2006-07-04 Marvell International Ltd. Frequency boosting circuit for high swing cascode
US7049894B1 (en) 2004-02-27 2006-05-23 Marvell International Ltd. Ahuja compensation circuit with enhanced bandwidth
US7425862B2 (en) * 2004-08-10 2008-09-16 Avago Technologies Ecbu Ip (Singapore) Pte Ltd Driver circuit that employs feedback to enable operation of output transistor in triode region and saturation region
KR100688803B1 (ko) * 2004-11-23 2007-03-02 삼성에스디아이 주식회사 전류 범위 제어회로, 데이터 구동부 및 발광 표시장치
JP5078502B2 (ja) * 2007-08-16 2012-11-21 セイコーインスツル株式会社 基準電圧回路
JP4408935B2 (ja) * 2008-02-07 2010-02-03 日本テキサス・インスツルメンツ株式会社 ドライバ回路
CN102455727B (zh) * 2010-10-28 2013-10-23 南京航空航天大学 100pA-1μA量程的微弱电流源
CN108683167B (zh) * 2018-07-03 2024-04-09 苏州锴威特半导体股份有限公司 一种pd设备的防浪涌电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2012481B (en) * 1978-01-09 1982-04-07 Rca Corp Egfet mirrors
GB8913439D0 (en) * 1989-06-12 1989-08-02 Inmos Ltd Current mirror circuit
JP3499250B2 (ja) 1992-08-10 2004-02-23 株式会社ルネサステクノロジ 半導体集積回路装置及びa/d変換回路
US5680037A (en) * 1994-10-27 1997-10-21 Sgs-Thomson Microelectronics, Inc. High accuracy current mirror
US5694072A (en) * 1995-08-28 1997-12-02 Pericom Semiconductor Corp. Programmable substrate bias generator with current-mirrored differential comparator and isolated bulk-node sensing transistor for bias voltage control
US5612614A (en) * 1995-10-05 1997-03-18 Motorola Inc. Current mirror and self-starting reference current generator
KR100202635B1 (ko) * 1995-10-13 1999-06-15 구본준 리서프 이디모스 트랜지스터와 이를 이용한 고전압 아날로그의 멀티플렉서회로
US5844434A (en) 1997-04-24 1998-12-01 Philips Electronics North America Corporation Start-up circuit for maximum headroom CMOS devices
US5847556A (en) * 1997-12-18 1998-12-08 Lucent Technologies Inc. Precision current source
US6087820A (en) * 1999-03-09 2000-07-11 Siemens Aktiengesellschaft Current source
US6381491B1 (en) * 2000-08-18 2002-04-30 Cardiac Pacemakers, Inc. Digitally trimmable resistor for bandgap voltage reference
US6466081B1 (en) * 2000-11-08 2002-10-15 Applied Micro Circuits Corporation Temperature stable CMOS device

Also Published As

Publication number Publication date
ATE313109T1 (de) 2005-12-15
DE10163633A1 (de) 2003-07-10
US20030117210A1 (en) 2003-06-26
JP2003223232A (ja) 2003-08-08
US6690229B2 (en) 2004-02-10
EP1321843A1 (fr) 2003-06-25
DE50205270D1 (de) 2006-01-19
JP4157928B2 (ja) 2008-10-01

Similar Documents

Publication Publication Date Title
EP1321843B1 (fr) Circuit de source de courant
DE102005039114B4 (de) Spannungsregler mit einem geringen Spannungsabfall
DE4211644C2 (de) Schaltungsanordnung zur Erzeugung einer konstanten Spannung
DE4034371C1 (fr)
DE10215084A1 (de) Schaltungsanordnung zur Spannungsregelung
DE10000224B4 (de) Leistungsverstärker mit einer Schutzschaltung
EP0557850A2 (fr) Montage servant à limiter le courant de charge d'un MOSFET de puissance
DE3736380C2 (de) Verstärker
DE102010006865B4 (de) Stromquelle, Stromquellenanordnung und deren Verwendung
DE2855303A1 (de) Linearer verstaerker
DE10142707A1 (de) Mehrstufiger Differenzverstärker mit CMFB-Schaltkreis
EP1004165B1 (fr) Reglage actif de points de fonctionnement d'un amplificateur de puissance
DE4444623A1 (de) Schaltungsanordnung zur Laststromregelung eines Leistungs-MOSFET
EP0582125A1 (fr) Circuit de commande pour un MOSFET de puissance ayant une charge connectée à la source
DE19631751C1 (de) Ansteuerschaltung für einen Leistungs-FET mit sourceseitiger Last
EP0523266B1 (fr) Miroir à courant intégrable
EP0556644B1 (fr) Circuit intégré
EP0762635A2 (fr) Circuit de commande de courant avec régulation du courant transversal
EP1099308B1 (fr) Circuit d'attaque
DE102004019345B4 (de) Ausgangsstufenanordnung
DE3017654C2 (fr)
EP0990199B1 (fr) Dispositif de reglage
DE10053374A1 (de) Bipolarer Komparator
DE19940382A1 (de) Stromquelle für niedrige Betriebsspannungen mit hohem Ausgangswiderstand
DE4431466C1 (de) Spannungsregler

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO

17P Request for examination filed

Effective date: 20031229

AKX Designation fees paid

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20051214

Ref country code: IE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051214

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20051219

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051219

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051231

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051231

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

REF Corresponds to:

Ref document number: 50205270

Country of ref document: DE

Date of ref document: 20060119

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060214

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20060213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060314

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060314

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060314

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060314

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060325

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060515

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20060915

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20061231

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20061231

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

BERE Be: lapsed

Owner name: PHILIPS INTELLECTUAL PROPERTY & STANDARDS G.M.B.H.

Effective date: 20051231

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20051231

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20091221

Year of fee payment: 8

Ref country code: GB

Payment date: 20091216

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20091217

Year of fee payment: 8

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20101219

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20110831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110103

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 50205270

Country of ref document: DE

Effective date: 20110701

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20110701

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101219