EP0523266B1 - Miroir à courant intégrable - Google Patents

Miroir à courant intégrable Download PDF

Info

Publication number
EP0523266B1
EP0523266B1 EP19910111958 EP91111958A EP0523266B1 EP 0523266 B1 EP0523266 B1 EP 0523266B1 EP 19910111958 EP19910111958 EP 19910111958 EP 91111958 A EP91111958 A EP 91111958A EP 0523266 B1 EP0523266 B1 EP 0523266B1
Authority
EP
European Patent Office
Prior art keywords
transistor
connection
transistors
load path
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19910111958
Other languages
German (de)
English (en)
Other versions
EP0523266A1 (fr
Inventor
Martin Dipl.-Ing. Feldtkeller
Marc Simon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE59108331T priority Critical patent/DE59108331D1/de
Priority to EP19910111958 priority patent/EP0523266B1/fr
Publication of EP0523266A1 publication Critical patent/EP0523266A1/fr
Application granted granted Critical
Publication of EP0523266B1 publication Critical patent/EP0523266B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology

Definitions

  • the invention relates to an integrated current mirror circuit arrangement according to the preamble of claim 1.
  • a current mirror circuit arrangement is e.g. B. from Tietze, Schenk: semiconductor circuit technology, 8th edition 1986, p. 62 and ff.
  • Fig. 4.36 shows z. B. a current mirror with transistor diode.
  • Fig. 4.37 shows a so-called Wilson current mirror, which has a high accuracy and a high output resistance.
  • the principle of both circuits is that the current I A flowing in the output circuit is regulated as closely as possible to the current I E flowing in the input circuit.
  • Wilson current mirror in particular has a high degree of accuracy with regard to the input and output current.
  • these known current mirror circuits have a strong dependence of the output current on the output voltage or a relatively high minimum voltage, which must drop at the output for precise regulation. As a result, the output characteristics of such current mirror circuits rise relatively slowly before they reach their saturation point.
  • German published patent application DE 39 13 446 A1 a current mirror circuit is shown in which a further transistor is connected in the load path of the current mirror transistor in the output branch.
  • the further transistor is controlled by an operational amplifier, the positive input of which is connected to the drain of the current mirror transistor on the input side and the negative input of which is connected to the drain of the output side Current mirror transistor is connected.
  • the mirrored current is tapped at the drain of the further transistor.
  • German published patent application DE 36 11 548 describes a current mirror circuit which contains a reference current source and two bipolar transistors with coupled base connections and interconnected emitter connections connected to a connection for a supply potential.
  • the coupled base connections are connected to the output connection of an operational amplifier, the input connections of which are connected to the collector connections of the bipolar transistors.
  • the collector connection of one of the bipolar transistors serves as the current output of the circuit, the collector connection of the other is connected to the reference current source.
  • the object of the invention is to provide a further implementation for a current mirror circuit in which the output current is as independent as possible of the output voltage and the minimum voltage is as low as possible.
  • means are provided which compare the voltages at the drain-source paths of the reference transistor and the output transistor with one another and the gate voltage of the two transistors is regulated in such a way that both drain-source voltages become the same.
  • the circuit arrangement shown in FIG. 1 has an input terminal 1 to which the supply voltage can be applied.
  • a reference current source 2 and the load path of a MOSFET 3 are connected in series between this and the ground connection.
  • Another MOSFET 4 is provided, the gate connection of which is connected to the gate connection of the MOSFET 3.
  • the two source connections of MOSFETs 3 and 4 are connected to one another and to ground.
  • two output terminals 6 and 7 are provided, the connection 6 being connected to the drain connection of the MOSFET 4 and the connection 7 being connected to ground.
  • the output circuit can be connected to both terminals 6 and 7.
  • an operational amplifier 5 is provided, the positive input of which is connected to the drain connection of the MOSFET 3 and the negative input of which is connected to the drain connection of the MOSFET 4.
  • the output of the operational amplifier 5 is connected to the two gate connections of the two MOSFETs 3 and 4.
  • the means for comparing the drain-source voltages are shown here as operational amplifiers 5.
  • the operational amplifier 5 adjusts the gate voltage of the two transistors in such a way that for a given drain current, which is equal to the input current I 1 , the same drain voltage is present at the reference transistor as at the output transistor.
  • the current I Q in the output branch is in a fixed ratio to that even at relatively low voltages at the output terminals 6 and 7 Current I 1 in the input branch, which is determined by the geometry of transistors 3 and 4.
  • the output current I Q of the current mirror circuit is therefore independent of the output voltage of the output circuit from a certain output voltage.
  • the exemplary embodiment of the invention shown in FIG. 2 in turn has an input terminal 1 to which the supply voltage can be applied. This is in turn connected to a current source 2, which in turn is connected to ground via the load path of an npn transistor 9 and the load path of an n-channel MOSFET 3.
  • the collector connection of the npn transistor 9 is connected to the base connection of a further npn transistor 8. Its collector is connected to the input terminal 1 and its emitter to the gate terminal of the MOSFET 3.
  • the gate connection of the MOSFET 3 is connected to the gate connection of an n-channel MOSFET 4 via the load path of a p-channel MOSFET 12.
  • Another current source 11 is connected between the gate connection of the MOSFET 3 and ground.
  • a current source 14 and the emitter-collector path of a pnp transistor 10 are also connected in series between the input terminal 1 and ground.
  • the emitter connection of the pnp transistor 10 is connected to the base connection of the npn transistor 9.
  • the base connection of the pnp transistor 10 is connected to the drain connection of the n-channel MOSFET 4 and to the output terminal 6.
  • the source connection of the n-channel MOSFET 4 is connected on the one hand to ground and on the other hand to the output terminal 7.
  • the load path of a further n-channel MOSFET 13 is connected between the gate connection of the n-channel MOSFET 4 and ground.
  • the gate connection of the n-channel MOSFET 13 is connected to the gate connection of the p-channel MOSFET 12 and an input terminal 16.
  • the means for comparing the drain-source voltages from FIG. 1 are formed by the transistors 8, 9, 10 and the two current sources 11 and 14.
  • the transistor 8 provides the desired gate voltage on the two MOSFETs 3 and 4.
  • the exact comparison of the input or. Output voltage at the drain-source paths of the two n-channel MOSFETs 3 and 4 is achieved in that a decisive pn junction is provided for each area. This is on the one hand the emitter base transition of transistor 9 and on the other hand the emitter base transition of transistor 10.
  • the two additional MOS transistors 12 and 13 represent an expansion compared to the circuit shown in FIG. 1. These serve as changeover switches and can be connected via the z. B. digital signal can be controlled. Depending on the signal state at connection 16, either p-channel transistor 12 or n-channel MOSFET 13 is conductive. Thus, either the gate connections of the two n-channel MOSFETs 3 and 4 are connected to one another via the load path of the p-channel MOSFET 12, or the gate connection of the n-channel MOSFET 4 is connected to ground via the load path of the n-channel MOSFET 13 connected. In this way, the output current can be clocked easily.
  • FIG. 3 Another circuit example, which is shown in FIG. 3, again shows an input terminal 1, to which the supply voltage is present.
  • a current source 2 is connected on the one hand to the input terminal 1 and on the other hand to the emitter connection of an npn transistor 19. Its collector is connected to the collector of an npn transistor 20, the emitter of which is in turn connected to ground.
  • a further current source 17 and a diode 18 connected in the direction of flow.
  • This series connection has a center tap which is connected to the base connection of the pnp transistor 19.
  • the connection terminal 1 is connected to the source connection of an enhancement p-channel MOSFET 23. Whose drain connection is connected to the emitter of a pnp transistor 22.
  • the collector terminal of the pnp transistor 22 is on the one hand to the base terminal of the npn transistor 20 and another connected to the collector terminal of an NPN transistor 21.
  • the base terminal of the npn transistor 21 is connected to the base terminal of the npn transistor 20.
  • the emitter connection of the npn transistor 21 is connected to the emitter connection of the npn transistor 20.
  • the collector-emitter path of an NPN transistor 24 is connected between the gate connection of the P-channel MOSFET 23 and ground.
  • the base terminal of the npn transistor 24 is connected to the collector terminal of the first pnp transistor 19.
  • a capacitance 25 is connected between the base connection and collector connection of the npn transistor 24.
  • a current source 26 is also connected between the input terminal 1 and the gate connection of the p-channel MOSFET 23.
  • the gate connection of the p-channel MOSFET 23 is connected to the gate connection of a p-channel enhancement MOSFET 30 via the load path of an n-channel enhancement MOSFET 27.
  • the source connection of the p-channel MOSFET 30 is in turn connected to the input terminal 1 and an output terminal 33.
  • the drain connection of the p-channel MOSFET 30 is connected on the one hand to an output terminal 32 and on the other hand to the emitter of a pnp transistor 31.
  • the base connection and collector connection of the pnp transistor 31 are short-circuited and connected to ground via a further current source 34.
  • the short-circuited base-collector path is still connected to the base connection of the pnp transistor 22.
  • the load path of a p-channel enhancement MOSFET 28 is connected between the input terminal 1 and the gate connection of the p-channel MOSFET 30.
  • the gate connection of the p-channel MOSFET 28 is connected to the gate connection of the n-channel MOSFET 27 and connected to an input terminal 29.
  • the circuit example described last differs from the embodiment according to the invention.
  • the input current that flows over the load path of the reference transistor 23 is quasi mirrored via the current mirror arrangement consisting of the transistors 20, 21 into the branch with the reference current source 2. There it is coupled out via transistor 24.
  • the base current of the transistor 22 is compensated for by the transistor 19 and the current source 17 and diode 18 coupled to it.
  • the capacitor 25 serves to avoid vibrations of the control system.
  • the transistor 31 connected as a diode and the current source 34 protect the circuit against overvoltage. These can occur when the potential at the output terminal 32 becomes lower than the potential at the terminal 33.
  • the circuits shown can be integrated in MOS bipolar mixing technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Claims (3)

  1. Montage de miroir de courant pouvant être intégré, comportant une source de courant de référence (2), deux transistors (3, 4), dont les bornes de commande sont reliées entre elles et dont les voies de charge sont reliées d'une part en commun à la masse, et des moyens (5), qui comparent les tensions aux voies de charge des transistors (3, 4) et qui produisent un signal de sortie qui est envoyé aux bornes de commande des deux transistors (3, 4), la voie de charge du premier transistor (3) recevant le courant (Il) de la source de courant de référence (2) et la voie de charge du second transistor (4) constituant une partie du circuit de sortie par laquelle le courant réfléchi (IQ) circule,
       caractérisé par le fait que
    - les voies de charge des deux transistors (3, 4) sont reliées par leurs bornes de source en commun à la masse,
    - la voie de charge du premier transistor (3) est reliée d'autre part par l'intermédiaire de la voie de charge d'un troisième transistor (9) à la première borne de la source de courant de référence (2),
    - la seconde borne de la source de courant de référence (2) est reliée à une borne d'alimentation (1),
    - le circuit série composé d'une seconde source de courant (14) et de la voie de charge d'un quatrième transistor (10) se trouve entre la borne d'alimentation (1) et la masse,
    - la prise médiane du circuit série est reliée à la borne de commande du troisième transistor (9),
    - une prise située entre la source de courant de référence (2) et la voie de charge du troisième transistor (9) est prévue, cette prise étant reliée à la borne de commande d'un cinquième transistor (8),
    - la voie de charge du cinquième transistor (8) est branchée entre la borne d'alimentation (1) et les bornes de commande du premier et du second transistor (3, 4),
    - une troisième source de courant (11) est branchée entre les bornes de commande du premier et du second transistor (3, 4),
    - la borne de commande du quatrième transistor (10) est reliée à l'autre borne de la voie de charge du second transistor (4).
  2. Montage de miroir de courant pouvant être intégré selon la revendication 1,
       caractérisé par le fait que
       les premier et second transistors (3, 4) sont construits sous forme de transistors MOSFET et les autres transistors (8, 9, 10) sont construits en technique bipolaire.
  3. Montage de miroir de courant pouvant être intégré selon l'une des revendications 1 ou 2,
       caractérisé par le fait que
       un commutateur (12, 13) est prévu entre la borne de commande du second transistor (4) et sa borne de source, le contact central du commutateur (12, 13) étant relié à la borne de commande du second transistor (4), le premier contact de commutation étant relié à la borne de commande du premier transistor (3) et le second contact de commutation étant relié à la borne de source du second transistor (4).
EP19910111958 1991-07-17 1991-07-17 Miroir à courant intégrable Expired - Lifetime EP0523266B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE59108331T DE59108331D1 (de) 1991-07-17 1991-07-17 Integrierbarer Stromspiegel
EP19910111958 EP0523266B1 (fr) 1991-07-17 1991-07-17 Miroir à courant intégrable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19910111958 EP0523266B1 (fr) 1991-07-17 1991-07-17 Miroir à courant intégrable

Publications (2)

Publication Number Publication Date
EP0523266A1 EP0523266A1 (fr) 1993-01-20
EP0523266B1 true EP0523266B1 (fr) 1996-11-06

Family

ID=8206940

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910111958 Expired - Lifetime EP0523266B1 (fr) 1991-07-17 1991-07-17 Miroir à courant intégrable

Country Status (2)

Country Link
EP (1) EP0523266B1 (fr)
DE (1) DE59108331D1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59108303D1 (de) * 1991-08-23 1996-11-28 Itt Ind Gmbh Deutsche Stromregelschaltung
EP0715239B1 (fr) * 1994-11-30 2001-06-13 STMicroelectronics S.r.l. Mirroir de courant de haute précision pour alimentation à basse tension
US5670829A (en) * 1995-03-20 1997-09-23 Motorola, Inc. Precision current limit circuit
DE102017204718B4 (de) 2017-03-21 2021-12-23 Dialog Semiconductor (Uk) Limited Abgleichsystem und Verfahren für regulierte Stromspiegel
FR3104751B1 (fr) 2019-12-12 2021-11-26 St Microelectronics Rousset Procédé de lissage d’un courant consommé par un circuit intégré et dispositif correspondant
FR3113776A1 (fr) * 2020-08-25 2022-03-04 Stmicroelectronics (Rousset) Sas Alimentation de circuit électronique
FR3113777A1 (fr) * 2020-08-25 2022-03-04 Stmicroelectronics (Rousset) Sas Alimentation de circuit électronique
CN114089804B (zh) * 2020-08-25 2023-05-23 意法半导体(鲁塞)公司 用于电子电路供电的设备和方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4647841A (en) * 1985-10-21 1987-03-03 Motorola, Inc. Low voltage, high precision current source
DE3611548A1 (de) * 1986-04-05 1987-10-08 Telefunken Electronic Gmbh Stromspiegelschaltung
EP0356570A1 (fr) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Miroir de courant
GB8913439D0 (en) * 1989-06-12 1989-08-02 Inmos Ltd Current mirror circuit

Also Published As

Publication number Publication date
EP0523266A1 (fr) 1993-01-20
DE59108331D1 (de) 1996-12-12

Similar Documents

Publication Publication Date Title
EP0747713B1 (fr) Circuit capteur de courant de charge d'un composant semi-conducteur de puissance avec charge soit à la borne de source ou soit à la borne de drain
EP0236967B1 (fr) Montage pour la commande d'un MOSFET dont la source est connectée à une charge
WO2000044048A1 (fr) Mosfet de puissance hybride
DE10000224B4 (de) Leistungsverstärker mit einer Schutzschaltung
EP1321843B1 (fr) Circuit de source de courant
DE102013219475A1 (de) Elektronischer schaltkreis mit einem elektronischenschalter und einem überwachungsschaltkreis
DE10196233T5 (de) Nachlauf- und Abschwächungs-Schaltung und Verfahren für DACs mit geschalteten Stromquellen
DE3736380C2 (de) Verstärker
EP0369048A1 (fr) Montage de régulation du courant de charge dans un MOSFET de puissance
EP0523266B1 (fr) Miroir à courant intégrable
DE102015104946A1 (de) Elektronische Treiberschaltung und Verfahren
DE4444623A1 (de) Schaltungsanordnung zur Laststromregelung eines Leistungs-MOSFET
EP0217223B1 (fr) Convertisseur numérique-analogique à compensation de température
EP0570820B1 (fr) Circuit source de courant commutable et l'utilisation d'un tel circuit dans un détecteur de phase
DE19533768C1 (de) Stromtreiberschaltung mit Querstromregelung
DE4429716C1 (de) Schaltungsanordnung zur Strombegrenzung
DE2409929C3 (de) Verzerrungsarmer, niederfrequenter Gegentakt-Leistungsverstärker
DE3100795A1 (de) Schalter mit in serie geschalteten feldeffekttransistoren
EP1099308B1 (fr) Circuit d'attaque
EP0351634B1 (fr) Circuit semi-conducteur pour évènements de commutation rapides
DE3712998C2 (fr)
DE102007036727A1 (de) Aktive Clampingschaltung für einen Leistungshalbleiterschalter
EP0990199A1 (fr) Dispositif de reglage
EP0821472B1 (fr) Dispositif de circuit pour l'ajustement du point de fonctionnement
DE3941840A1 (de) Schaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL SE

17P Request for examination filed

Effective date: 19930701

17Q First examination report despatched

Effective date: 19950208

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT NL SE

REF Corresponds to:

Ref document number: 59108331

Country of ref document: DE

Date of ref document: 19961212

ET Fr: translation filed
ITF It: translation for a ep patent filed

Owner name: STUDIO JAUMANN

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19970123

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010705

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 20010717

Year of fee payment: 11

Ref country code: NL

Payment date: 20010717

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010724

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20010919

Year of fee payment: 11

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020717

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020718

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030201

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030201

EUG Se: european patent has lapsed
GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020717

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030331

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20030201

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050717