EP0523266B1 - Integratable current mirror - Google Patents

Integratable current mirror Download PDF

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Publication number
EP0523266B1
EP0523266B1 EP19910111958 EP91111958A EP0523266B1 EP 0523266 B1 EP0523266 B1 EP 0523266B1 EP 19910111958 EP19910111958 EP 19910111958 EP 91111958 A EP91111958 A EP 91111958A EP 0523266 B1 EP0523266 B1 EP 0523266B1
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Prior art keywords
transistor
connection
transistors
load path
source
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EP19910111958
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German (de)
French (fr)
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EP0523266A1 (en
Inventor
Martin Dipl.-Ing. Feldtkeller
Marc Simon
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Siemens AG
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Siemens AG
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Priority to EP19910111958 priority Critical patent/EP0523266B1/en
Priority to DE59108331T priority patent/DE59108331D1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology

Definitions

  • the invention relates to an integrated current mirror circuit arrangement according to the preamble of claim 1.
  • a current mirror circuit arrangement is e.g. B. from Tietze, Schenk: semiconductor circuit technology, 8th edition 1986, p. 62 and ff.
  • Fig. 4.36 shows z. B. a current mirror with transistor diode.
  • Fig. 4.37 shows a so-called Wilson current mirror, which has a high accuracy and a high output resistance.
  • the principle of both circuits is that the current I A flowing in the output circuit is regulated as closely as possible to the current I E flowing in the input circuit.
  • Wilson current mirror in particular has a high degree of accuracy with regard to the input and output current.
  • these known current mirror circuits have a strong dependence of the output current on the output voltage or a relatively high minimum voltage, which must drop at the output for precise regulation. As a result, the output characteristics of such current mirror circuits rise relatively slowly before they reach their saturation point.
  • German published patent application DE 39 13 446 A1 a current mirror circuit is shown in which a further transistor is connected in the load path of the current mirror transistor in the output branch.
  • the further transistor is controlled by an operational amplifier, the positive input of which is connected to the drain of the current mirror transistor on the input side and the negative input of which is connected to the drain of the output side Current mirror transistor is connected.
  • the mirrored current is tapped at the drain of the further transistor.
  • German published patent application DE 36 11 548 describes a current mirror circuit which contains a reference current source and two bipolar transistors with coupled base connections and interconnected emitter connections connected to a connection for a supply potential.
  • the coupled base connections are connected to the output connection of an operational amplifier, the input connections of which are connected to the collector connections of the bipolar transistors.
  • the collector connection of one of the bipolar transistors serves as the current output of the circuit, the collector connection of the other is connected to the reference current source.
  • the object of the invention is to provide a further implementation for a current mirror circuit in which the output current is as independent as possible of the output voltage and the minimum voltage is as low as possible.
  • means are provided which compare the voltages at the drain-source paths of the reference transistor and the output transistor with one another and the gate voltage of the two transistors is regulated in such a way that both drain-source voltages become the same.
  • the circuit arrangement shown in FIG. 1 has an input terminal 1 to which the supply voltage can be applied.
  • a reference current source 2 and the load path of a MOSFET 3 are connected in series between this and the ground connection.
  • Another MOSFET 4 is provided, the gate connection of which is connected to the gate connection of the MOSFET 3.
  • the two source connections of MOSFETs 3 and 4 are connected to one another and to ground.
  • two output terminals 6 and 7 are provided, the connection 6 being connected to the drain connection of the MOSFET 4 and the connection 7 being connected to ground.
  • the output circuit can be connected to both terminals 6 and 7.
  • an operational amplifier 5 is provided, the positive input of which is connected to the drain connection of the MOSFET 3 and the negative input of which is connected to the drain connection of the MOSFET 4.
  • the output of the operational amplifier 5 is connected to the two gate connections of the two MOSFETs 3 and 4.
  • the means for comparing the drain-source voltages are shown here as operational amplifiers 5.
  • the operational amplifier 5 adjusts the gate voltage of the two transistors in such a way that for a given drain current, which is equal to the input current I 1 , the same drain voltage is present at the reference transistor as at the output transistor.
  • the current I Q in the output branch is in a fixed ratio to that even at relatively low voltages at the output terminals 6 and 7 Current I 1 in the input branch, which is determined by the geometry of transistors 3 and 4.
  • the output current I Q of the current mirror circuit is therefore independent of the output voltage of the output circuit from a certain output voltage.
  • the exemplary embodiment of the invention shown in FIG. 2 in turn has an input terminal 1 to which the supply voltage can be applied. This is in turn connected to a current source 2, which in turn is connected to ground via the load path of an npn transistor 9 and the load path of an n-channel MOSFET 3.
  • the collector connection of the npn transistor 9 is connected to the base connection of a further npn transistor 8. Its collector is connected to the input terminal 1 and its emitter to the gate terminal of the MOSFET 3.
  • the gate connection of the MOSFET 3 is connected to the gate connection of an n-channel MOSFET 4 via the load path of a p-channel MOSFET 12.
  • Another current source 11 is connected between the gate connection of the MOSFET 3 and ground.
  • a current source 14 and the emitter-collector path of a pnp transistor 10 are also connected in series between the input terminal 1 and ground.
  • the emitter connection of the pnp transistor 10 is connected to the base connection of the npn transistor 9.
  • the base connection of the pnp transistor 10 is connected to the drain connection of the n-channel MOSFET 4 and to the output terminal 6.
  • the source connection of the n-channel MOSFET 4 is connected on the one hand to ground and on the other hand to the output terminal 7.
  • the load path of a further n-channel MOSFET 13 is connected between the gate connection of the n-channel MOSFET 4 and ground.
  • the gate connection of the n-channel MOSFET 13 is connected to the gate connection of the p-channel MOSFET 12 and an input terminal 16.
  • the means for comparing the drain-source voltages from FIG. 1 are formed by the transistors 8, 9, 10 and the two current sources 11 and 14.
  • the transistor 8 provides the desired gate voltage on the two MOSFETs 3 and 4.
  • the exact comparison of the input or. Output voltage at the drain-source paths of the two n-channel MOSFETs 3 and 4 is achieved in that a decisive pn junction is provided for each area. This is on the one hand the emitter base transition of transistor 9 and on the other hand the emitter base transition of transistor 10.
  • the two additional MOS transistors 12 and 13 represent an expansion compared to the circuit shown in FIG. 1. These serve as changeover switches and can be connected via the z. B. digital signal can be controlled. Depending on the signal state at connection 16, either p-channel transistor 12 or n-channel MOSFET 13 is conductive. Thus, either the gate connections of the two n-channel MOSFETs 3 and 4 are connected to one another via the load path of the p-channel MOSFET 12, or the gate connection of the n-channel MOSFET 4 is connected to ground via the load path of the n-channel MOSFET 13 connected. In this way, the output current can be clocked easily.
  • FIG. 3 Another circuit example, which is shown in FIG. 3, again shows an input terminal 1, to which the supply voltage is present.
  • a current source 2 is connected on the one hand to the input terminal 1 and on the other hand to the emitter connection of an npn transistor 19. Its collector is connected to the collector of an npn transistor 20, the emitter of which is in turn connected to ground.
  • a further current source 17 and a diode 18 connected in the direction of flow.
  • This series connection has a center tap which is connected to the base connection of the pnp transistor 19.
  • the connection terminal 1 is connected to the source connection of an enhancement p-channel MOSFET 23. Whose drain connection is connected to the emitter of a pnp transistor 22.
  • the collector terminal of the pnp transistor 22 is on the one hand to the base terminal of the npn transistor 20 and another connected to the collector terminal of an NPN transistor 21.
  • the base terminal of the npn transistor 21 is connected to the base terminal of the npn transistor 20.
  • the emitter connection of the npn transistor 21 is connected to the emitter connection of the npn transistor 20.
  • the collector-emitter path of an NPN transistor 24 is connected between the gate connection of the P-channel MOSFET 23 and ground.
  • the base terminal of the npn transistor 24 is connected to the collector terminal of the first pnp transistor 19.
  • a capacitance 25 is connected between the base connection and collector connection of the npn transistor 24.
  • a current source 26 is also connected between the input terminal 1 and the gate connection of the p-channel MOSFET 23.
  • the gate connection of the p-channel MOSFET 23 is connected to the gate connection of a p-channel enhancement MOSFET 30 via the load path of an n-channel enhancement MOSFET 27.
  • the source connection of the p-channel MOSFET 30 is in turn connected to the input terminal 1 and an output terminal 33.
  • the drain connection of the p-channel MOSFET 30 is connected on the one hand to an output terminal 32 and on the other hand to the emitter of a pnp transistor 31.
  • the base connection and collector connection of the pnp transistor 31 are short-circuited and connected to ground via a further current source 34.
  • the short-circuited base-collector path is still connected to the base connection of the pnp transistor 22.
  • the load path of a p-channel enhancement MOSFET 28 is connected between the input terminal 1 and the gate connection of the p-channel MOSFET 30.
  • the gate connection of the p-channel MOSFET 28 is connected to the gate connection of the n-channel MOSFET 27 and connected to an input terminal 29.
  • the circuit example described last differs from the embodiment according to the invention.
  • the input current that flows over the load path of the reference transistor 23 is quasi mirrored via the current mirror arrangement consisting of the transistors 20, 21 into the branch with the reference current source 2. There it is coupled out via transistor 24.
  • the base current of the transistor 22 is compensated for by the transistor 19 and the current source 17 and diode 18 coupled to it.
  • the capacitor 25 serves to avoid vibrations of the control system.
  • the transistor 31 connected as a diode and the current source 34 protect the circuit against overvoltage. These can occur when the potential at the output terminal 32 becomes lower than the potential at the terminal 33.
  • the circuits shown can be integrated in MOS bipolar mixing technology.

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
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Description

Die Erfindung betrifft eine integrierte Stromspiegelschaltungsanordnung gemäß dem Oberbegriff des Anspruches 1.The invention relates to an integrated current mirror circuit arrangement according to the preamble of claim 1.

Eine Stromspiegelschaltungsanordnung ist z. B. aus Tietze, Schenk: Halbleiterschaltungstechnik, 8. Auflage 1986, S. 62 und ff. bekannt. Auf Seite 63 zeigt Abb. 4.36 dort z. B. einen Stromspiegel mit Transistordiode. Abb. 4.37 zeigt einen sogenannten Wilson-Stromspiegel, der eine hohe Genauigkeit und einen hohen Ausgangswiderstand besitzt. Prinzip beider Schaltungen ist, daß der im Ausgangskreis fließende Strom IA möglichst gleich dem im Eingangskreis fließenden Strom IE geregelt wird.A current mirror circuit arrangement is e.g. B. from Tietze, Schenk: semiconductor circuit technology, 8th edition 1986, p. 62 and ff. On page 63, Fig. 4.36 shows z. B. a current mirror with transistor diode. Fig. 4.37 shows a so-called Wilson current mirror, which has a high accuracy and a high output resistance. The principle of both circuits is that the current I A flowing in the output circuit is regulated as closely as possible to the current I E flowing in the input circuit.

Insbesondere der Wilson-Stromspiegel besitzt eine hohe Genauigkeite, was den Eingangs- bzw. Ausgangsstrom betrifft. Diese bekannten Stromspiegelschaltungen haben jedoch eine starke Abhängigkeit des Ausgangsstroms von der Ausgangsspannung oder eine relativ hohe Mindestspannung, die am Ausgang für eine genaue Regelung abfallen muß. Dadurch steigen die Ausgangskennlinien derartiger Stromspiegelschaltungen relativ langsam an, bevor sie ihren Sättigungspunkt erreichen.The Wilson current mirror in particular has a high degree of accuracy with regard to the input and output current. However, these known current mirror circuits have a strong dependence of the output current on the output voltage or a relatively high minimum voltage, which must drop at the output for precise regulation. As a result, the output characteristics of such current mirror circuits rise relatively slowly before they reach their saturation point.

In der deutschen Offenlegungsschrift DE 39 13 446 A1 ist eine Stromspiegelschaltung gezeigt, bei der im Ausgangszweig ein weiterer Transistor in die Laststrecke des Stromspiegeltransistors geschaltet ist. Der weitere Transistor wird von einem Operationsverstärker angesteuert, dessen Plus-Eingang mit dem Drainanschluß des eingangsseitigen Stromspiegeltransistors und dessen Minus-Eingang mit dem Drainanschluß des ausgangsseitigen Stromspiegeltransistors verbunden ist. Der gespiegelte Strom wird am Drainanschluß des weiteren Transistors abgegriffen.In German published patent application DE 39 13 446 A1 a current mirror circuit is shown in which a further transistor is connected in the load path of the current mirror transistor in the output branch. The further transistor is controlled by an operational amplifier, the positive input of which is connected to the drain of the current mirror transistor on the input side and the negative input of which is connected to the drain of the output side Current mirror transistor is connected. The mirrored current is tapped at the drain of the further transistor.

In der Deutschen Offenlegungsschrift DE 36 11 548 ist eine Stromspiegelschaltung beschrieben, die eine Referenzstromquelle enthält sowie zwei Bipolartransistoren mit gekoppelten Basisanschlüssen und miteinander verbundenen, an einen Anschluß für ein Versorgungspotential angelegten Emitteranschlüssen. Die gekoppelten Basisanschlüsse sind mit dem Ausgangsanschluß eines Operationsverstärkers verbunden, dessen Eingangsanschlüsse mit den Kollektoranschlüssen der Bipolartransistoren verbunden sind. Der Kollektoranschluß eines der Bipolartransistoren dient als Stromausgang der Schaltung, der Kollektoranschluß des anderen ist mit der Referenzstromquelle verbunden.German published patent application DE 36 11 548 describes a current mirror circuit which contains a reference current source and two bipolar transistors with coupled base connections and interconnected emitter connections connected to a connection for a supply potential. The coupled base connections are connected to the output connection of an operational amplifier, the input connections of which are connected to the collector connections of the bipolar transistors. The collector connection of one of the bipolar transistors serves as the current output of the circuit, the collector connection of the other is connected to the reference current source.

Aufgabe der Erfindung ist es, eine weitere Realisierung für eine Stromspiegelschaltung anzugeben, bei der der Ausgangsstrom möglichst unabhängig von der Ausgangsspannung ist und die Mindestspannung möglichst geringt ist.The object of the invention is to provide a further implementation for a current mirror circuit in which the output current is as independent as possible of the output voltage and the minimum voltage is as low as possible.

Die Aufgabe wird gelöst durch die kennzeichnenden Merkmale des Anspruchs 1. Weiterbildungen sind Kennzeichen der Unteransprüche. Die Erfindung wird nachfolgend näher erläutert. Es zeigen:

FIG 1
ein Prinzipschaltbild einer Stromspiegelschaltungsanordnung,
FIG 2
ein Ausführungsbeispiel der Erfindung mit n-Kanal-Enhancement-MOS-Feldeffekttransistoren,
FIG 3
ein Schaltungspbeispiel mit p-Kanal-Enhancement-MOS-Feldeffekttransistoren.
The object is achieved by the characterizing features of claim 1. Further developments are characteristic of the subclaims. The invention is explained in more detail below. Show it:
FIG. 1
2 shows a basic circuit diagram of a current mirror circuit arrangement,
FIG 2
An embodiment of the invention with n-channel enhancement MOS field-effect transistors,
FIG 3
a circuit example with p-channel enhancement MOS field effect transistors.

Prinzipiell sind Mittel vorgesehen, die die Spannungen an den Drain-Source-Strecken des Referenztransistors und des Ausgangstransistors miteinander vergleichen und die Gatespannung der beiden Transistoren so ausgeregelt wird, daß beide Drain-Source-Spannungen gleich werden.In principle, means are provided which compare the voltages at the drain-source paths of the reference transistor and the output transistor with one another and the gate voltage of the two transistors is regulated in such a way that both drain-source voltages become the same.

Die in FIG 1 gezeigte Schaltungsanordnung weist eine Eingangsklemme 1 auf, an der die Versorgungsspannung anlegbar ist. Zwischen dieser und dem Masseanschluß ist eine Referenzstromquelle 2 sowie die Laststrecke eines MOSFETs 3 in Reihe geschaltet. Ein weiterer MOSFET 4 ist vorgesehen, dessen Gateanschluß mit dem Gateanschluß des MOSFETs 3 verschaltet ist. Ebenso sind die beiden Sourceanschlüsse der MOSFETs 3 und 4 miteinander und mit Masse verbunden. Weiterhin sind zwei Ausgangsklemmen 6 und 7 vorgesehen, wobei der Anschluß 6 mit dem Drainanschluß des MOSFETs 4 und der Anschluß 7 mit Masse verbunden ist. An den beiden Klemmen 6 und 7 ist der Ausgangskreis anschließbar. Desweiteren ist ein Operationsverstärker 5 vorgesehen, dessen positiver Eingang mit dem Drainanschluß des MOSFETs 3 und dessen negativer Eingang mit dem Drainanschluß des MOSFETs 4 verbunden ist. Der Ausgang des Operationsverstärkers 5 ist mit den beiden Gateanschlüssen der beiden MOSFETs 3 und 4 verschaltet.The circuit arrangement shown in FIG. 1 has an input terminal 1 to which the supply voltage can be applied. A reference current source 2 and the load path of a MOSFET 3 are connected in series between this and the ground connection. Another MOSFET 4 is provided, the gate connection of which is connected to the gate connection of the MOSFET 3. Likewise, the two source connections of MOSFETs 3 and 4 are connected to one another and to ground. Furthermore, two output terminals 6 and 7 are provided, the connection 6 being connected to the drain connection of the MOSFET 4 and the connection 7 being connected to ground. The output circuit can be connected to both terminals 6 and 7. Furthermore, an operational amplifier 5 is provided, the positive input of which is connected to the drain connection of the MOSFET 3 and the negative input of which is connected to the drain connection of the MOSFET 4. The output of the operational amplifier 5 is connected to the two gate connections of the two MOSFETs 3 and 4.

Die Mittel zum Vergleichen der Drain-Source-Spannungen sind hier als Operationsverstärker 5 dargestellt. Der Operationsverstärker 5 stellt die Gatespannung der beiden Transistoren so ein, daß bei einem gegebenen Drainstrom, welcher gleich dem Eingangsstrom I1 ist, am Referenztransistor die gleiche Drainspannung anliegt wie am Ausgangstransistor. Dadurch steht schon bei relativ kleinen Spannungen an den Ausgangsklemmen 6 und 7 der Strom IQ im Ausgangszweig in einem festen Verhältnis zu dem Strom I1 im Eingangszweig, welches durch die Geometrie der Transistoren 3 und 4 bestimmt ist. Der Ausgangsstrom IQ der Stromspiegelschaltung ist also ab einer gewissen Ausgangsspannung unabhängig von der Ausgangsspannung des Ausgangskreises.The means for comparing the drain-source voltages are shown here as operational amplifiers 5. The operational amplifier 5 adjusts the gate voltage of the two transistors in such a way that for a given drain current, which is equal to the input current I 1 , the same drain voltage is present at the reference transistor as at the output transistor. As a result, the current I Q in the output branch is in a fixed ratio to that even at relatively low voltages at the output terminals 6 and 7 Current I 1 in the input branch, which is determined by the geometry of transistors 3 and 4. The output current I Q of the current mirror circuit is therefore independent of the output voltage of the output circuit from a certain output voltage.

Das in FIG 2 gezeigte Ausführungsbeispiel des Erfindung weist wiederum eine Eingangsklemme 1 auf, an welcher die Versorgungsspannung anlegbar ist. Diese ist wiederum mit einer Stromquelle 2 verbunden, welche ihrerseits über die Laststrecke eines npn-Transistors 9 sowie der Laststrecke eines n-Kanal-MOSFETs 3 mit Masse verschaltet ist. Der Kollektoranschluß des npn-Transistors 9 ist mit dem Basisanschluß eines weiteren npn-Transistors 8 verbuncen. Dessen Kollektor ist mit der Eingangsklemme 1 und sein Emitter mit dem Gateanschluß des MOSFETs 3 verschaltet. Weiterhin ist der Gateanschluß des MOSFET 3 über die Laststrecke eines p-Kanal-MOSFETs 12 mit dem Gateanschluß eines n-Kanal-MOSFETs 4 verbunden. Zwischen Gateanschluß des MOSFET 3 und Masse ist eine weitere Stromquelle 11 geschaltet. Zwischen der Eingangsklemme 1 und Masse ist weiterhin eine Stromquelle 14 sowie die Emitter-Kollektorstrecke eines pnp-Transistors 10 in Reihe geschaltet. Der Emitteranschluß des pnp-Transistors 10 ist mit dem Basisanschluß des npn-Transistors 9 verschaltet. Der Basisanschluß des pnp-Transistors 10 ist mit dem Drainanschluß des n-Kanal-MOSFETs 4 und mit der Ausgangsklemme 6 verbunden. Der Sourceanschluß des n-Kanal-MOSFETs 4 ist zum einen mit Masse und zum anderen mit der Ausgangsklemme 7 verschaltet. Schließlich ist zwischen den Gateanschluß des n-Kanal-MOSFETs 4 und Masse die Laststrecke eines weiteren n-Kanal-MOSFETs 13 geschaltet. Der Gateanschluß des n-Kanal-MOSFETs 13 ist mit dem Gateanschluß des p-Kanal-MOSFETs 12 sowie einer Eingangsklemme 16 verbunden.The exemplary embodiment of the invention shown in FIG. 2 in turn has an input terminal 1 to which the supply voltage can be applied. This is in turn connected to a current source 2, which in turn is connected to ground via the load path of an npn transistor 9 and the load path of an n-channel MOSFET 3. The collector connection of the npn transistor 9 is connected to the base connection of a further npn transistor 8. Its collector is connected to the input terminal 1 and its emitter to the gate terminal of the MOSFET 3. Furthermore, the gate connection of the MOSFET 3 is connected to the gate connection of an n-channel MOSFET 4 via the load path of a p-channel MOSFET 12. Another current source 11 is connected between the gate connection of the MOSFET 3 and ground. A current source 14 and the emitter-collector path of a pnp transistor 10 are also connected in series between the input terminal 1 and ground. The emitter connection of the pnp transistor 10 is connected to the base connection of the npn transistor 9. The base connection of the pnp transistor 10 is connected to the drain connection of the n-channel MOSFET 4 and to the output terminal 6. The source connection of the n-channel MOSFET 4 is connected on the one hand to ground and on the other hand to the output terminal 7. Finally, the load path of a further n-channel MOSFET 13 is connected between the gate connection of the n-channel MOSFET 4 and ground. The gate connection of the n-channel MOSFET 13 is connected to the gate connection of the p-channel MOSFET 12 and an input terminal 16.

Die Mittel zum Vergleichen der Drain-Source-Spannungen aus FIG 1 werden in dieser Ausführungsform durch die Transistoren 8, 9, 10 sowie die beiden Stromquellen 11 und 14 gebildet. Der Transistor 8 stellt die gewünschte Gatespannung an den beiden MOSFETs 3 und 4 ein. Der genaue Vergleich der Eingangs-bzw. Ausgangsspannung an den Drain-Source-Strecken der beiden n-Kanal-MOSFETs 3 und 4 wird dadurch erreicht, daß für beide Bereiche jeweils ein entscheidender pn-Übergang vorgesehen ist. Dieser ist zum einen der Emitter-Basisübergang des Transistors 9 sowie zum anderen der Emitter-Basisübergang des Transistors 10.In this embodiment, the means for comparing the drain-source voltages from FIG. 1 are formed by the transistors 8, 9, 10 and the two current sources 11 and 14. The transistor 8 provides the desired gate voltage on the two MOSFETs 3 and 4. The exact comparison of the input or. Output voltage at the drain-source paths of the two n-channel MOSFETs 3 and 4 is achieved in that a decisive pn junction is provided for each area. This is on the one hand the emitter base transition of transistor 9 and on the other hand the emitter base transition of transistor 10.

Eine Erweiterung gegenüber der in FIG 1 gezeigten Schaltung stellen die beiden zusätzlichen MOS-Transistoren 12 und 13 dar. Diese dienen als Umschalter und können über das am Anschluß 16 anliegende z. B. digitale Signal angesteuert werden. Je nach Signalzustand am Anschluß 16 ist entweder der p-Kanal-Transistor 12 oder der n-Kanal-MOSFET 13 leitend. Somit sind entweder die Gateanschlüsse der beiden n-Kanal-MOSFETs 3 und 4 über die Laststrecke des p-Kanal-MOSFETs 12 miteinander verbunden oder der Gateanschluß des n-Kanal-MOSFETs 4 ist über die Laststrecke des n-Kanal-MOSFETs 13 mit Masse verbunden. Auf diese Weise kann der Ausgangsstrom einfach getaktet werden.The two additional MOS transistors 12 and 13 represent an expansion compared to the circuit shown in FIG. 1. These serve as changeover switches and can be connected via the z. B. digital signal can be controlled. Depending on the signal state at connection 16, either p-channel transistor 12 or n-channel MOSFET 13 is conductive. Thus, either the gate connections of the two n-channel MOSFETs 3 and 4 are connected to one another via the load path of the p-channel MOSFET 12, or the gate connection of the n-channel MOSFET 4 is connected to ground via the load path of the n-channel MOSFET 13 connected. In this way, the output current can be clocked easily.

Ein anderen Schaltungsbeispiel, welches in FIG 3 dargestellt ist, zeigt wiederum eine Eingangsklemme 1, an welcher die Versorgungsspannung anliegt. Eine Stromquelle 2 ist zum einen mit der Eingangsklemme 1 und zum anderen mit dem Emitteranschluß eines npn-Transistors 19 verschaltet. Dessen Kollektor ist mit dem Kollektor eines npn-Transistors 20 verschaltet, dessen Emitter wiederum mit Masse verbunden ist. Zwischen den Eingangsklemmen 1 und Masse liegt die Serienschaltung einer weiteren Stromquelle 17 sowie einer in Flußrichtung geschalteten Diode 18. Diese Reihenschaltung weist einen Mittelabgriff auf, der mit dem Basisanschluß des pnp-Transistors 19 verbunden ist. Weiterhin ist die Anschlußklemme 1 mit dem Sourceanschluß eines Enhancement-p-Kanal-MOSFET 23 verbunden. Dessen Drainanschluß ist mit dem Emitter eines pnp-Transistors 22 verschaltet. Der Kollektoranschluß des pnp-Transistors 22 ist zum einen mit dem Basisanschluß des npn-Transistors 20 und zum anderen mit dem Kollektoranschluß eines npn-Transistors 21 verschaltet. Der Basisanschluß des npn-Transistors 21 ist mit dem Basisanschluß des npn-Transistors 20 verbunden. Ebenso ist der Emitteranschluß des npn-Transistors 21 mit dem Emitteranschluß des npn-Transistors 20 verbunden. Zwischen den Gateanschluß des P-Kanal-MOSFETs 23 und Masse ist die Kollektor-Emitterstrecke eines npn-Transistors 24 geschaltet. Der Basisanschluß des npn-Transistors 24 ist mit dem Kollektoranschluß des ersten pnp-Transistors 19 verbunden. Zwischen Basisanschluß und Kollektoranschluß des npn-Transistors 24 ist eine Kapazität 25 geschaltet. Zwischen der Eingangsklemme 1 und dem Gateanschluß des p-Kanal-MOSFETs 23 ist weiterhin eine Stromquelle 26 geschaltet. Der Gateanschluß des p-Kanal-MOSFETs 23 ist über die Laststrecke eines n-Kanal-Enhancement-MOSFETs 27 mit dem Gateanschluß eines p-Kanal-Enhancement-MOSFET -MOSFET 30 verbunden. Der Sourceanschluß des p-Kanal-MOSFETs 30 ist wiederum mit der Eingangsklemme 1 und einer Ausgangsklemme 33 verschaltet. Der Drainanschluß des p-Kanal-MOSFETs 30 ist zum einen mit einer Ausgangsklemme 32 und zum anderen mit dem Emitter eines pnp-Transistors 31 verbunden. Basisanschluß und Kollektoranschluß des pnp-Transistors 31 sind kurzgeschlossen und über eine weitere Stromquelle 34 mit Masse verschaltet. Die kurzgeschlossene Basis-Kollektorstrecke ist weiterhin mit dem Basisanschluß des pnp-Transistors 22 verbunden. Letztlich ist zwischen der Eingangsklemme 1 und dem Gateanschluß des p-Kanal-MOSFETs 30 die Laststrecke eines p-Kanal-Enhancement-MOSFET 28 geschaltet. Der Gateanschluß des p-Kanal-MOSFETs 28 ist mit dem Gateanschluß des n-Kanal-MOSFETs 27 verschaltet und mit einer Eingangsklemme 29 verbunden.Another circuit example, which is shown in FIG. 3, again shows an input terminal 1, to which the supply voltage is present. A current source 2 is connected on the one hand to the input terminal 1 and on the other hand to the emitter connection of an npn transistor 19. Its collector is connected to the collector of an npn transistor 20, the emitter of which is in turn connected to ground. Between the input terminals 1 and ground is the series connection of a further current source 17 and a diode 18 connected in the direction of flow. This series connection has a center tap which is connected to the base connection of the pnp transistor 19. Furthermore, the connection terminal 1 is connected to the source connection of an enhancement p-channel MOSFET 23. Whose drain connection is connected to the emitter of a pnp transistor 22. The collector terminal of the pnp transistor 22 is on the one hand to the base terminal of the npn transistor 20 and another connected to the collector terminal of an NPN transistor 21. The base terminal of the npn transistor 21 is connected to the base terminal of the npn transistor 20. Likewise, the emitter connection of the npn transistor 21 is connected to the emitter connection of the npn transistor 20. The collector-emitter path of an NPN transistor 24 is connected between the gate connection of the P-channel MOSFET 23 and ground. The base terminal of the npn transistor 24 is connected to the collector terminal of the first pnp transistor 19. A capacitance 25 is connected between the base connection and collector connection of the npn transistor 24. A current source 26 is also connected between the input terminal 1 and the gate connection of the p-channel MOSFET 23. The gate connection of the p-channel MOSFET 23 is connected to the gate connection of a p-channel enhancement MOSFET 30 via the load path of an n-channel enhancement MOSFET 27. The source connection of the p-channel MOSFET 30 is in turn connected to the input terminal 1 and an output terminal 33. The drain connection of the p-channel MOSFET 30 is connected on the one hand to an output terminal 32 and on the other hand to the emitter of a pnp transistor 31. The base connection and collector connection of the pnp transistor 31 are short-circuited and connected to ground via a further current source 34. The short-circuited base-collector path is still connected to the base connection of the pnp transistor 22. Ultimately, the load path of a p-channel enhancement MOSFET 28 is connected between the input terminal 1 and the gate connection of the p-channel MOSFET 30. The gate connection of the p-channel MOSFET 28 is connected to the gate connection of the n-channel MOSFET 27 and connected to an input terminal 29.

Aus schaltungstechnischen Gründen unterscheidet sich das zuletzt beschriebene Schaltungsbeispiel von der erfindungsgemäßen Ausführungsform. So wird in diesem Fall quasi der Eingangsstrom, welcher über die Laststrecke des Referenztransistors 23 fließt über die Stromspiegelanordnung bestehend aus den Transistoren 20, 21 in den Zweig mit der Referenzstromquelle 2 gespiegelt. Dort wird er über den Transistor 24 ausgekoppelt. Der Basisstrom des Transistors 22 wird durch den Transistor 19 sowie die an ihn angekoppelte Stromquelle 17 und Diode 18 kompensiert. Der Kondensator 25 dient dazu, Schwingungen des Regelsystems zu vermeiden. Der als Diode geschaltete Transistor 31 sowie die Stromquelle 34 schützen die Schaltung vor Überspannung. Diese können auftreten, wenn das Potential an der Ausgangsklemme 32 niedriger als das Potential an der Klemme 33 wird.For circuitry reasons, the circuit example described last differs from the embodiment according to the invention. In this case, the input current that flows over the load path of the reference transistor 23 is quasi mirrored via the current mirror arrangement consisting of the transistors 20, 21 into the branch with the reference current source 2. There it is coupled out via transistor 24. The base current of the transistor 22 is compensated for by the transistor 19 and the current source 17 and diode 18 coupled to it. The capacitor 25 serves to avoid vibrations of the control system. The transistor 31 connected as a diode and the current source 34 protect the circuit against overvoltage. These can occur when the potential at the output terminal 32 becomes lower than the potential at the terminal 33.

Die gezeigten Schaltungen sind in MOS-Bipolar-Mischtechnologie integrierbar.The circuits shown can be integrated in MOS bipolar mixing technology.

Claims (3)

  1. Integrable current mirror circuit arrangement having a reference current source (2), having two transistors (3, 4) whose control connections are connected to one another and whose load paths are on the one hand jointly connected to earth, and having means (5) which compare the voltages across the load paths of the transistors (3, 4) and produce an output signal which is fed to the control connections of the two transistors (3, 4), the load path of the first transistor (3) being supplied with the current (I1) from the reference current source (2), and the load path of the second transistor (4) forming part of the output circuit through which the mirrored current (IQ) flows,
    characterized in that
    - the load paths of the two transistors (3, 4) are jointly connected to earth at the source connections,
    - the load path of the first transistor (3) is connected, on the other hand, to the first connection of the reference current source (2) via the load path of a third transistor (9),
    - the second connection of the reference current source (2) is connected to a supply terminal (1),
    - the series circuit formed by a second current source (14) and the load path of a fourth transistor (10) lies between the supply terminal (1) and earth,
    - the centre tap of the series circuit is connected to the control connection of the third transistor (9),
    - a tap is provided between the reference current source (2) and the load path of the third transistor (9) and is connected to the control connection of a fifth transistor (8),
    - the load path of the fifth transistor (8) is connected between the supply terminal (1) and the control connections of the first and second transistors (3, 4),
    - a third current source (11) is connected between the control connections of the first and second transistors (3, 4),
    - the control connection of the source transistor (10) is connected to the other connection of the load path of the second transistor (4).
  2. Integrable current mirror circuit arrangement according to Claim 1, characterized in that the first and second transistors (3, 4) are designed as MOSFETs and the remaining transistors (8, 9, 10) are designed using bipolar technology.
  3. Integrable current mirror circuit arrangement according to either of Claims 1 and 2, characterized in that a changeover switch (12, 13) is provided between the control connection of the second transistor (4) and its source connection, the centre contact of the changeover switch (12, 13) being connected to the control connection of the second transistor (4), and the first changeover contact being connected to the control connection of the first transistor (3) and the second changeover contact being connected to the source connection of the second transistor (4).
EP19910111958 1991-07-17 1991-07-17 Integratable current mirror Expired - Lifetime EP0523266B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19910111958 EP0523266B1 (en) 1991-07-17 1991-07-17 Integratable current mirror
DE59108331T DE59108331D1 (en) 1991-07-17 1991-07-17 Integrable current mirror

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19910111958 EP0523266B1 (en) 1991-07-17 1991-07-17 Integratable current mirror

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EP0523266A1 EP0523266A1 (en) 1993-01-20
EP0523266B1 true EP0523266B1 (en) 1996-11-06

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0529118B1 (en) * 1991-08-23 1996-10-23 Deutsche ITT Industries GmbH Current regulating circuit
DE69427479T2 (en) * 1994-11-30 2002-01-17 Stmicroelectronics S.R.L., Agrate Brianza Highly accurate current mirror for low supply voltage
US5670829A (en) * 1995-03-20 1997-09-23 Motorola, Inc. Precision current limit circuit
DE102017204718B4 (en) * 2017-03-21 2021-12-23 Dialog Semiconductor (Uk) Limited Adjustment system and procedure for regulated current mirrors
FR3104751B1 (en) 2019-12-12 2021-11-26 St Microelectronics Rousset Method of smoothing a current consumed by an integrated circuit and corresponding device
FR3113777A1 (en) 2020-08-25 2022-03-04 Stmicroelectronics (Rousset) Sas Electronic circuit power supply
FR3113776A1 (en) * 2020-08-25 2022-03-04 Stmicroelectronics (Rousset) Sas Electronic circuit power supply
CN114089804B (en) * 2020-08-25 2023-05-23 意法半导体(鲁塞)公司 Apparatus and method for powering electronic circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4647841A (en) * 1985-10-21 1987-03-03 Motorola, Inc. Low voltage, high precision current source
DE3611548A1 (en) * 1986-04-05 1987-10-08 Telefunken Electronic Gmbh Current mirror circuit
EP0356570A1 (en) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Current mirror
GB8913439D0 (en) * 1989-06-12 1989-08-02 Inmos Ltd Current mirror circuit

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EP0523266A1 (en) 1993-01-20
DE59108331D1 (en) 1996-12-12

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