EP1313088A1 - Verfahren und Vorrichtung zur Spannungssteuerung einer Elektronenquelle mit Matrixstruktur, mit Regulierung von emittierter Ladung - Google Patents

Verfahren und Vorrichtung zur Spannungssteuerung einer Elektronenquelle mit Matrixstruktur, mit Regulierung von emittierter Ladung Download PDF

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Publication number
EP1313088A1
EP1313088A1 EP02292833A EP02292833A EP1313088A1 EP 1313088 A1 EP1313088 A1 EP 1313088A1 EP 02292833 A EP02292833 A EP 02292833A EP 02292833 A EP02292833 A EP 02292833A EP 1313088 A1 EP1313088 A1 EP 1313088A1
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EP
European Patent Office
Prior art keywords
current
column
line
pixel
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02292833A
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English (en)
French (fr)
Inventor
Pierre Nicolas
Denis Sarrasin
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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Publication of EP1313088A1 publication Critical patent/EP1313088A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present invention relates to a method for and a device for controlling the voltage of a source electrons with matrix structure, with regulation of the charge issued.
  • the cathodes hot cathodes, photoemissive cathodes and cathodes Field effect microtips as described in referenced document [1] at the end of the description
  • the nanofield devices with field effect such as described in the document referenced [2]
  • the sources electron planes of the graphite or diamond carbon type as described in the document referenced [3]
  • the electroluminescent devices or LEDs Light-Emitting Diode
  • Such sources of electrons find applications mainly in the field of viewing with flat screens but also in other areas, for example that of physical instrumentation, lasers and sources of X-ray emission, as described in the document referenced [4].
  • Examples of the invention that are given in the following are taken in the vast field of the visualization, which includes flat screens.
  • the present invention is, however, not limited to this domain and applies to any device using one or more sources of electrons (including in particular the case of a matrix 1 row x 1 column). It's the case, for example, a functioning mono-pixel display pulsed.
  • FIG. 1 schematically illustrates the operating principle of a display screen that uses a field emitting electron source 2.
  • This screen includes an anode 4 with a driver anode 6.
  • the cathode, which constitutes the source Electron 2 is usually voltage controlled. Under the influence of this voltage, it emits a of electrons 8.
  • this screen comprises a cathode constituted by a substrate 10, provided of cathode conductors 12 on which are formed microtips 14, and grids 16 formed above cathodic conductors with holes 18 next to the microtips.
  • the screen also includes an anode with a substrate 20 and anode conductor 22 next to the grids 16.
  • the voltage source 24 makes it possible to apply the high voltage V a to the anode conductor 6.
  • the biasing means 26 are intended to apply the voltage V g to the gate of the electron source 2 and the voltage V c to the cathode of this source.
  • V gc is the control voltage which is equal to V g -V c .
  • V th is the threshold voltage. For a control voltage Vo greater than Vth, the curve I corresponds to a cathode current Io while the curve II corresponds to a current Io- ⁇ I.
  • the electrons emitted by the electron source are accelerated and collected by the anode subjected to the high voltage V a . If a layer of phosphor material 28 ("phosphorus") is deposited on the anode conductor 6, the kinetic energy of the electrons is converted into light.
  • a matrix structure screen using a matrix-structured electron source 30 is schematically shown in FIG. 4.
  • Each pixel is defined by the intersection of a line electrode and a column electrode of that source.
  • the screen of FIG. 4 comprises a generator 34 for scanning lines. This generator is provided with a source 36 of voltage V lns and a source 38 of voltage V ls .
  • V li is the control voltage of the line L i .
  • the screen also comprises means 40 for generating the control voltages of the columns.
  • V cj is the control voltage of the column C j .
  • a control circuit is assigned to each line and to each column of the screen and addressing is carried out one line at a time for a time t lig .
  • the lines are carried sequentially to a potential V ls called line selection potential, while the columns are brought to a potential corresponding to the information to be displayed. Meanwhile t lig unselected rows are raised to a potential V lns as the voltages on the columns do not affect the display on these lines.
  • V ls a potential V ls called line selection potential
  • control methods are possible. We know, for example, a method of control using electric charges, plus simply called “load control method”, as described in the referenced document [6]. We know also a control method using a current, more simply called “current control method”, as described in the referenced document [7].
  • a current command may seem solve this problem because it is then necessary to inject a current and therefore a specific quantity of electrons.
  • Such a principle is in fact valid static.
  • a capacitive load problem Indeed, a column electrode is similar to a capacitor compared to the lines that this column crosses and the current required for fast charging this capacitor proves superior, of several orders of magnitude, the emission current.
  • the capacitance of one column with respect to the C col lines is about 400 pF.
  • the capacitive current is thus of the order 1000 times larger than the emission current that we wants to settle.
  • Such a method is not not suitable for fast ordering from a source to Matrix structure.
  • FIG. 5 schematically illustrates a display screen comprising a matrix-structured electron source using load control.
  • This known screen differs from that of FIG. 4 only by the means for applying the control voltages to the columns of the source of the screen.
  • the means 42 for applying a control voltage to a column for example the column C j , comprise a logic block 44, which receives as input a line synchronization signal E1, and a comparator 46, which receives as input a set value A1 and which is connected to the logic block 44.
  • the voltage application means 42 also comprise a tri-state output stage 48 which is also connected to the logic block 44 and receives voltages respectively denoted V c-on and V c-off from unrepresented voltage sources.
  • the three-state output stage and the comparator are connected to the corresponding column of the electron source (C j in the example under consideration).
  • an electrode of column is akin to a capacitor compared to the matric structure source lines but that there are also leakage currents that circulate between the column in question and the lines and that these currents vary with the difference of potential between these electrodes.
  • the voltage drop does not depend on the only emission current but also currents of leakage that vary themselves according to this fall Of voltage.
  • V lns V lns + I f (lns) little different from (V ls / R lc ) - (n-1). (V cj (t) / R lc )
  • this variation ⁇ V cj must be compared to the set value A1.
  • This variation of the voltage ⁇ V cj depends on the value of the capacity of the column, which brings technological variables of the screen (related to the dimensions of this screen) in the design parameters of the control circuit.
  • the comparator 46 is at the level of the output stage of the assembly forming the means for generating the control voltages of the columns. This means that this comparator must either withstand the voltage dynamics required for the control of the columns (approximately 40 V), or be able to isolate this output by an additional stage.
  • the present invention aims to to remedy the various previous disadvantages.
  • the value of the potential of the column or columns capable of allowing the emission is equal to the potential of the unaddressed line (s) of the pixel of this column.
  • the measured amount of charge is converted into a voltage level.
  • the device which is the subject of the invention may further comprise means of compensation of residual leakage currents.
  • the means for measuring the instantaneous current at the beginning of transmission time and means of using another current include a current-to-voltage converter followed by an analog sample-and-hold to memorize, in the form of a voltage, the instantaneous current of the pixel of the column considered.
  • the means for measuring the instantaneous current at the beginning of time line and use of another stream include current follower mounting and mounting current copier.
  • the follower assembly current includes an operational amplifier looped on a first transistor mounted in the feedback of this amplifier, the first transistor being mounted as a current follower.
  • the copier assembly of current comprises a second transistor biased by a voltage, these two transistors constituting a mirror current.
  • Figure 1 schematically illustrates the operating principle of a display screen of known art using a transmission device field.
  • Figure 2 schematically illustrates the structure of a micropoint screen of the known art.
  • Figure 4 schematically illustrates a display screen of the known art using a field emission device with matrix structure.
  • Figure 5 is a schematic view of a known device for controlling an electron source at Matrix structure.
  • Figure 6 schematically illustrates a example of a control device of a column of a electron source with matrix structure.
  • Figure 7 schematically illustrates a variant of the device of FIG.
  • Figure 8 is a chronogram of different voltages existing in the device of the Figure 7 during a line addressing cycle.
  • Figure 9 schematically illustrates a first embodiment, according to the invention, of a control device of a column of a source electrons with matrix structure, with memorization pixel current as a voltage.
  • Figure 10 is a chronogram of different voltages existing in the device of the Figure 9 during a line addressing cycle.
  • Figure 11 schematically illustrates a second embodiment, according to the invention, of a control device of a column of a source electrons with matrix structure, with memorization of the pixel current using a current mirror.
  • Figure 12 is a chronogram of different voltages existing in the device of the Figure 11 during a line addressing cycle.
  • the first of these components is related to the very principle of scanning the screen. The second of these components can be canceled provided that V cj (t) and V lns are both equal to the same constant.
  • This control device 60 comprises a output stage 62 of the push-pull type, an assembly current integrator 64 and a comparator 66.
  • the output stage 62 makes it possible to switch, on the column electrode (C j ), either the supply voltage V c-off corresponding to the extinction level of the pixel or the input of the integrator assembly 64 which imposes its virtual mass level V c-on , putting it at potential V lns unselected lines.
  • the output stage 62 comprises, in a manner known to those skilled in the art, logic level translation means 68 and two MOSFET transistors 70 and 72, respectively P-type and N-type, arranged as illustrated in FIG. .
  • the integrator assembly 64 comprises an amplifier 74 which is looped on a capacitor 76 of capacitance C int which is itself connected in parallel with a controlled switch SW1.
  • the output A2 of this amplifier is connected to the input (-) of the comparator 66.
  • Switch SW1 controlled by a signal S1 corresponding to the beginning of the time that is allocated to a line, allows the A2 potential to be reduced to zero beginning of each line.
  • the input (+) of the comparator 66 is connected to a target voltage A1 corresponding to the quantity of charges to be issued.
  • This voltage setpoint can be provided by various means that depend on the desired application. In the example shown on Figure 6 uses a digital converter analogue CDA which receives as input a given Digital DN setpoint voltage and whose output provides the setpoint potential A1.
  • S2 output of the comparator assembly is the control of the output stage 62 thus allowing the closure of the device.
  • the control logic 52 provides the signal S1 and controls a PL line control circuit no represent.
  • This device converts the quantity of charge already transmitted into a voltage level, which makes it possible to switch the control of the control stage of the column C j to the time t off when the quantity of charge (Q ref ) of setpoint is reached.
  • the order of magnitude of these charges parasites is often greater than or equal to that of payloads to deliver to the pixel.
  • FIG. 7 An exemplary embodiment of a control device of a column C j , insensitive to the inter-column parasitic coupling problem mentioned above, is schematically represented in FIG. 7.
  • This device 60 is based on a fast acquisition of the current of the pixel at the beginning of line time, therefore in the absence of switching of the other columns.
  • the emission current of a pixel I pix can be considered constant for a line time when the control voltages do not vary.
  • This device comprises in particular a floor push-pull output 62, as shown in FIG. the device of FIG. 6, and a type assembly current-voltage converter CCT.
  • This CCT assembly includes an amplifier 74 for maintaining the potential of the column to that of the virtual mass. The feedback of the amplifier by the resistance R makes it possible to obtain at the output A2 a measurement of the current of the pixel.
  • the amplifier 74 has on its input inverter, SW2 controlled switch and / or fast switching diodes DF1 and DF2. The role of these components is to directly drain to the ground the strong capacitive currents outside the instants of measured. Indeed, during commutations lines / columns, strong capacitive currents could disrupt the current voltage converter CTC.
  • FIG. 8 represents the time diagram of the different voltages existing within the device of FIG. 7, during a line addressing cycle (duration t lig ).
  • the cycle starts at time t 0 , by the start pulse of the signal S 1, and the rise of the signal S 2 which, by the output stage, makes the column V cj go to V c-on (virtual ground).
  • the switch SW2 is closed jointly with the aid of the signal S1 to evacuate the capacitive switching currents of the columns.
  • the line i is addressed and the switch SW2 is opened jointly by means of the command S1.
  • the pixel current (I pix ) establishes on each column, after a stabilization time t stab , a potential stage A2 at the output of the amplifier 74.
  • t stab represents the response time of the column or pixel addressed.
  • the potential line V Li switches to the selection potential V ls , after the establishment of the potential of the column (V cj ), which reduces the ability to load only that of the pixel.
  • the capacitive current in the column is therefore minimized.
  • the calculation of t off requires to integrate for each column output a fast computing electronics 52 to evaluate from the beginning of the line time, the time t off .
  • the object of the invention is to propose a simple analog solution for regulating the load, without means of calculation, by avoiding inter-column interference coupling problems.
  • This analog solution is based on a sampling and analog storage of the current of each pixel at the beginning of time line, which allows you to create a load control system genuinely issued free from pests of switching of the other columns during the rest of the time line.
  • the "push-pull" output stage 62 makes it possible to switch on the column C j , either the supply voltage Vc-off corresponding to the extinction level of the pixel, or the input of the current-voltage converter CCT which imposes by its virtual mass the level V c-on .
  • the current-voltage converter CCT allows measuring the pixel current of the column under consideration.
  • the sampler-blocker 90 associated with resistance R2 allows to sample-block this current of the pixel.
  • This integrator 92 (Su3) is a gradient voltage ramp proportional to the current of the pixel and free from any switching disturbances of neighboring columns. This ramp is compared with the charge setpoint (V ref ) supplied to the comparator 95 by the digital analog converter CDA.
  • the output of this comparator 95 (Scomp) is, after processing by the logic 52, looped by the signal S2 on the control of the output circuit 62 allowing the control of the column in question.
  • This device shown in Figure 9 therefore constitutes a looped analog system of regulation of the transmitted charge.
  • Figure 10 shows the diagram time of the different voltages existing within this device 89 during a line addressing cycle.
  • the signals A to E of this figure correspond to the signals A to E of Figure 8.
  • the cycle starts at time t 0 .
  • the rising edge of pulse S1 closes switch SW2.
  • the rising edge of S2 through the output stage 62, passes the column potential V cj to V c-on (virtual ground).
  • the potential line V Li goes from its potential V lns (defined as the mass of the assembly) to the selection potential V ls to trigger the emission.
  • the current I pix is then established, and after a stabilization time t stab the output of the current-voltage converter CCT (S u1 ) is stabilized at a voltage value representative of I pix .
  • This voltage value is then sampled-blocked in the sample-and-hold 90, whose switch SW3 is controlled by the signal S4 from logic 52.
  • the output of the comparator 95 switches at the instant t off when the voltage ramp on its negative input reaches the setpoint value V ref presented on its positive input.
  • the device of the invention makes it possible to deliver to the pixel in question a charge controlled by the setpoint supplied V ref , and without variation of the voltage applied to the column, during the emission time.
  • the device thus produced is insensitive to switching of neighboring columns by storing the current of the pixel.
  • the line potential V Li switches to the selection potential V ls , after the establishment of the potential of the column V cj , so as to reduce the capacity to load to that of the pixel in question.
  • the capacitive current in the column is therefore minimized during the passage of the pixel in emission, on the rising edge of V Li .
  • the time t stab which corresponds to the establishment of the line / column potential and the passing of the pixel in transmission, is imposed by the physical characteristics of the screen. It sets the first level of gray accessible by the system. Column commutations, in fact, during this establishment phase, are prohibited from acquiring and storing the current of the pixel. The charge transmitted by the pixel during the time t stab thus constitutes the first level of gray of the system.
  • the black display is managed directly by the control logic 52 while keeping the signal S2 of the corresponding column low.
  • the proposed device makes it possible to control the ratio I R2 / I pix by choosing the ratio between R1 and R2.
  • the choice of R2 also conditions the geometry of the integration capacity Ci.
  • Figure 11 illustrates a second example of embodiment of the device of the invention 99 based on storing the current of the pixels using a current mirror.
  • the current follower assembly 100 includes the operational amplifier 74 looped on a P-type transistor T1 mounted in the feedback amplifier 74.
  • This transistor T1 is mounted in current follower, that is to say that its electrode grid is connected to its drain electrode and to the output of the amplifier 74, and that its electrode source is connected to the inverting input of the amplifier 74.
  • the current copier assembly 101 comprises the switch SW3, the capacitor C ech and a transistor T2, identical to the transistor T1, whose drain is biased by a voltage V pol .
  • the output of amplifier 74 (S u1 ) drives the gate of transistor T2.
  • the transistor T2 thus copies the current of T1, itself identical to the pixel current.
  • the set T1, T2 constitutes a current mirror.
  • the drain of T1 could also be biased via the voltage V pol .
  • the current copier assembly 101 allows sampling and blocking of the current I pix in the transistor T2.
  • the T2 current is free from any switching disturbances of neighboring columns.
  • the output of this comparator 95 is, after processing by the logic 52, looped by the signal S2 on the control of the output circuit 62 for controlling the column in question.
  • the device thus represented constitutes a looped analog charge control system issued.
  • Figure 12 shows the diagram time of the different voltages within the device 99 shown in Figure 11.
  • the signals A to I of this figure correspond respectively to the signals A to F and H to J in Figure 10.
  • the cycle starts at time t 0 by the transition to the high level of S1 which closes the switch SW2 and the rising edge of S2 which, through the output stage 62, changes the potential V cj to V c-on (virtual mass).
  • V Li goes from its potential V lns (defined as the mass of the assembly) to the selection potential V ls .
  • V lns defined as the mass of the assembly
  • V ls selection potential
  • This voltage value (S u1 ) is then sampled blocked using command S4, in C ech .
  • the switch SW4 is opened via the signal S3, which starts the integration of the output current of the transistor T2 into the capacitor Ci of the integrator 92.
  • the value of I pix sampled-locked at time t on + t stab With two transistors T1 and T2 identical found in the current integrator 92, the value of I pix sampled-locked at time t on + t stab .
  • the output of the integrator 92 delivers (S u3 ) a slope voltage ramp proportional to the output current of the transistor T2 (I T2 ).
  • the output of the comparator 95 (Scomp) switches to t off when the voltage ramp on its input reaches the setpoint value V ref presented on the input (+).
  • comparator 95 (Scomp) is then revalidated by logic 52, to stop the emission of the pixel.
  • the command S2 then drives the return of the column voltage V cj to Vc -off via the output stage 62.
  • the device described above makes it possible to deliver to the pixel in question, a load controlled by the setpoint supplied V ref , and without variation of the voltage applied to the column during the emission time. It is also insensitive to switches of neighboring columns by storing the current of the pixel.
  • the line potential V Li also switches to the selection potential V ls , after the establishment of the potential of the column (V cj ), so as to reduce the capacity to load to that of the pixel in question.
  • the device thus proposed makes it possible to control the ratio I T2 / I pix by the choice of the geometrical ratios between the transistor T1 and the transistor T2.
  • the geometry of the transistor T2 also conditions the geometry of the integration capacitance Ci.
  • This device also offers the freedom of having a choice of several transistors T2 of different geometries installed in parallel in the circuit.
  • the choice of the transistor to be used then depends on the type of screen to be controlled (hence the expected I pix ) by connecting the common drains of the chosen family to the V pol feed. This connection is made outside the circuit when it is implemented on a given type of screen.
EP02292833A 2001-11-16 2002-11-14 Verfahren und Vorrichtung zur Spannungssteuerung einer Elektronenquelle mit Matrixstruktur, mit Regulierung von emittierter Ladung Withdrawn EP1313088A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0114839A FR2832537B1 (fr) 2001-11-16 2001-11-16 Procede et dispositif de commande en tension d'une source d'electrons a structure matricielle, avec regulation de la charge emise
FR0114839 2001-11-16

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EP1313088A1 true EP1313088A1 (de) 2003-05-21

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US (1) US6862010B2 (de)
EP (1) EP1313088A1 (de)
JP (1) JP4494711B2 (de)
FR (1) FR2832537B1 (de)

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FR2832537B1 (fr) 2003-12-19
US6862010B2 (en) 2005-03-01

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