EP1307874A1 - Procede et circuit de commande d'un ecran a plasma - Google Patents
Procede et circuit de commande d'un ecran a plasmaInfo
- Publication number
- EP1307874A1 EP1307874A1 EP01963085A EP01963085A EP1307874A1 EP 1307874 A1 EP1307874 A1 EP 1307874A1 EP 01963085 A EP01963085 A EP 01963085A EP 01963085 A EP01963085 A EP 01963085A EP 1307874 A1 EP1307874 A1 EP 1307874A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- column
- activation
- activated
- input
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/025—Reduction of instantaneous peaks of current
Definitions
- the present invention relates to plasma screens and more particularly to the control of the cells of a plasma screen.
- a plasma screen is a matrix type screen, formed of cells arranged at the intersections of rows and columns.
- a cell comprises a cavity filled with a rare gas, and at least two control electrodes.
- the cell is selected by applying a potential difference between. its control electrodes, then an ionization of the cell gas is triggered, generally by means of a third control electrode. This ionization is accompanied by an emission of ultraviolet rays.
- the creation of the light point is obtained by excitation of a red, green or blue luminescent material by the rays emitted.
- FIG. 1 represents a conventional plasma screen structure formed by cells 4.
- Each cell 4 has two control electrodes respectively connected to a ⁇ line and to a column 8.
- the selection of cells, with a view to creating images, is conventionally carried out by logic circuits producing control signals.
- the logical states of these deter- undermine the cells which are controlled to produce a light point and those which are controlled not to produce one.
- the ionization of the gas in a cell requires that potentials of the order of a hundred volts be applied between the two control electrodes for a predetermined duration, of the order of 2 microseconds.
- Each cell has an equivalent capacity of the order of several tens of picofarads.
- FIG. 2 represents a plasma screen whose cells 4 are represented by an equivalent capacity.
- a line control circuit 10 for each line 6 comprises a line control block '14 having an output connected to the line 6.
- a column control circuit 12 comprises, for each column 8 a column control unit 18 which an output 20 is connected to the column 8.
- the circuits 10 and 12 are generally integrated on the same semiconductor chip.
- the cells of a plasma screen are activated line by line.
- the lines that are not activated are set to a resting potential VDDl (for example 150 V).
- the activated line is brought to an GND activation potential (0 V).
- VDD2 80 V
- the columns corresponding to the other points of the activated line are brought to the GND potential (0 V).
- the lit cells of the activated row see a column-row potential equal to VDD2 - GND (80 V) and the unlit cells of the activated row see a column-row potential equal to GND - GND (0 V).
- Each line control block 14 comprises a pair of complementary power transistors 22 and 24.
- the transistor 24 receives the potential VDDl on its source. Its drain is connected to a line 6 and its gate receives an LSN command signal for line inactivation.
- the source of transistor 22 is linked to potential GND. Its drain is connected to line 6 and its grid receives an LS control signal complementary to the LSN signal.
- the LS and LSN signals are produced, for example, by a microprocessor not shown.
- Each column control block 18 comprises an output stage 5 comprising a pair of power transistors (not shown) making it possible to bring the output 20 to the potentials VDD2 or GND as a function of a logic signal for selecting the LCS column supplied. on stage 26.
- Each control block 18 also includes a memory element 28 connected, for example to 10. a microprocessor not shown, for receiving and memorizing the value of the logic signal LCS intended for output stage 26.
- Each block control 18 further comprises a logic switch 30 controlled by a validation signal VAL, connected between the memory element 28 and the output stage 26.
- the logic switch 30 is provided to supply an inactive signal to the stage of output 26 as long as the validation signal VAL is inactive, for example at a low logic level.
- the switch 30 is also provided for, when the signal VAL is active, supply to the output stage 26 the LCS signal stored in the element
- the signal VAL is conventionally activated for a predetermined duration after each activation of a line of the screen.
- FIG. 3 is a timing diagram illustrating the voltage V6 of a line 6, the validation signal VAL, the voltage V8 of a column 8, and the current 122 in the transistor 22 of the line control circuit 14.
- the line is selected and the voltage V6 goes from the potential VDDl to the potential GND.
- the voltage V8 is then at the potential GND.
- the signal VAL is activated and the column 8 is connected to the potential VDD2, for a point to light up.
- the selected cell is
- the transistor 22 is crossed by a first current peak PI.
- a second current peak P2 more intense than the first.
- the instant tl can be located 10 to 20 ns after the instant to
- the instant t2 can be located 50 to 100 ns after the instant tl
- the instants t3 and t4 can be located 150 to 200 ns after instants tl and t2 respectively.
- the cell load can correspond to current peaks PI and P2 of 0.1 and 0.3 mA respectively.
- a control circuit is conventionally used to control more than 3000 columns. Thus, if all the columns 8 of a selected row must be lit, the second peak of current passing through the transistor 22 can reach 1 A.
- the transistors 22 must have a large size to be able to be crossed by such a current.
- An object of the present invention is to provide a circuit for controlling the cells of a plasma screen, which is of small size and inexpensive. To achieve this object, the present invention provides for delaying the selection of the different columns so that the charge of the equivalent capacities of the cells of the same line of the screen is not simultaneous.
- the present invention provides a method for controlling cells of a matrix type plasma screen, formed of cells arranged at the intersections of rows and columns, comprising the step of sequentially applying to each row a potential of activation- and, during the activation of a row, applying an activation potential to selected columns, in which while a row is activated, the selected columns are activated non-simultaneously.
- the activation of the selected columns is controlled by a single signal activating several control blocks, each of which controls with a delay of its own the application of the activation potential to the column.
- the present invention also relates to a circuit for controlling the cells of a matrix type plasma screen, formed of cells arranged at the intersections of lines and columns, comprising line command blocks for sequentially applying an activation potential to each line, and comprising column command blocks for, while each line being activated, applying an activation potential to selected columns, each column control block comprising a predetermined delay means for delaying the application of the activation potential to the selected columns.
- the predetermined delay means of each column control block is connected for. be activated by the same validation signal.
- each means with predetermined delay delays the application of the activation potential to a selected column with a predetermined delay from its activation.
- each column control block comprises: an output stage coupled to the column activated by the control block, and receiving an input signal, a memory element for receiving and storing a signal column selection means, and a predetermined delay means comprising a NAND gate having a first input connected to the output of the memory element, a second input which receives said validation signal and an output connected to the input of the output stage via an inverter comprising a P-type OS transistor whose dimensions are such that said inverter switches at a predetermined speed.
- the column control blocks form several groups, the column control blocks of the same group each activating a column with the same predetermined delay and each column control block comprising: a output stage coupled to the column activated by the control block, and receiving an input signal, a memory element for receiving and storing a column selection signal, and a predetermined delay means comprising a NAND gate having a first input connected to the output of the memory element, a second input which receives said validation signal and a output connected to the input of the output stage by means of an inverter supplied between a ground and a supply node, the supply nodes of the column control blocks of the same group being connected together and separated from the supply nodes of the other column control blocks by a resistor, the supply nodes of a first group of column control blocks being connected to a supply voltage.
- FIG. 1, previously described schematically represents a conventional plasma screen structure
- FIG. 2, previously described schematically represents a plasma screen connected to a conventional control circuit
- Figure 3, previously described illustrates the load of a cell of a line of the screen of Figure 2
- FIG. 4 schematically represents column control blocks according to the present invention
- FIG. 5 illustrates the cell load of a line of a plasma screen controlled by a control circuit according to the present invention
- FIG. 6 schematically represents an embodiment of a logic switch of a column control block according to the present invention
- FIG. 7 schematically represents another embodiment of the logic switch of a column control block according to the present invention.
- FIG. 4 schematically represents a circuit 12 ′ for controlling the columns of a plasma screen (not shown) according to the present invention.
- the circuit 12 comprises, for each column 8 of the plasma screen, a column control block 18', one output 20 of which is connected to column 8.
- Each control block 18 includes an output stage 26 controlled by an LCS column activation logic signal, and a memory element 28 connected to receive and store the value of the logic signal to be supplied to stage 26.
- Each control block 18 'further comprises a logic switch 30' controlled by a validation signal VAL and connected between the memory element 28 and the output stage 26.
- the logic switch 30 'of each control block 18' is provided for, when the signal VAL is activated, supply the LCS signal stored in memory element 28 at output stage 26 with a predetermined delay.
- the logic switches 30 'of the different ' blocks 18 ' can each introduce a different delay with respect to the signal VAL or else they can be divided into several groups of switches introducing the same delay. The greater the number of blocks 18 ′ introducing a different delay, the lower the number of cells whose equivalent capacities can be charged simultaneously, and the lower the maximum current likely to pass through the transistor 22.
- FIG. 5 represents various voltages and currents appearing during the operation of the circuit of FIG. 4.
- V8a, V ⁇ b, V8c represent the voltages of three columns connected to three blocks 18 ′ according to the present invention whose logic muters introduce respectively delays Da, Db, From.
- a line 6 is selected and its voltage V6 goes from the potential VDDl to the potential GND.
- the voltages V8a, V8b and V8c are then at the potential GND.
- the signal VAL is activated at an instant tl.
- the logic switches 30 'of the three blocks 18' respectively produce activation signals LCSa, LCSb, LCSc at times tla, tlb, tic delayed by Da, Db and De with respect to the instant tl.
- Columns 8a, 8b and 8c are connected to potential VDD2 substantially at times tla, tlb and tic.
- the capacities of the cells connected to columns 8a, 8b and 8c are loaded respectively between times tla and t2a, tlb and t2b, tic and t2c.
- the transistor 22 is crossed by first current peaks Pla, Plb, Peak of the order of 0.1 A each during the charging of each of the three capacitors. As seen above, each charge is followed by a second peak current.
- Transistor 22 is crossed by three second current peaks P2a, P2b, P2c of the order of 0.3 mA each between instants t3a and t4a, t3b and t4b, t3c and t4c.
- the maximum current flowing through the transistor 22 is only equal to the sum of the current peaks produced by the blocks 18 'introducing a same delay. If, for example, the blocks 18 ′ are distributed into three groups a, b, c respectively introducing a delay Da, Db, De, the present invention makes it possible to divide by three the maximum current in the transistor 22.
- the illustrated charging times that is to say the width of the current peaks, and the delays Da, Db, De are such that the current peaks corresponding to the different delays are distinct. In practice, however, the charging times and delays may be such that the different peaks overlap.
- FIG. 6 schematically represents an embodiment of a logic switch 30 '.
- the switch 30 ' includes a conventional NAND gate 34.
- the two input terminals of door 34 are the two input terminals of the switch logic 30 '.
- the output of the gate 34 is connected to the output S of the switch 30 ′ via an inverter 36.
- the inverter 36 comprises an N-type MOS transistor connected between ground and the output S and a MOS transistor of P type connected between the output S and a VDD power line, for example 3 or 5 V.
- the specific width / width (/ L) ratio for the P type MOS transistor of the inverter 36 is used to get a specific delay.
- the W / L ratio of the P-type transistor determines in particular the current which can pass through this transistor, and thereby the speed with which the switch 30 'can bring a load (stage 26) connected to its output S to a voltage. corresponding to a high logic state.
- the W / L ratio of the P-type MOS transistor of the inverter 36 makes it possible to adjust the delay introduced by the logic switch 30 '.
- FIG. 7 shows the logic switches 30 "of a control circuit according to another embodiment of the present invention.
- Each logical switch 30" includes a NAND gate 34 whose inputs are the inputs of the switch logic, and the output of which is connected to the output S of the logic switch 30 "via an inverter 38.
- Each inverter 38 is supplied between a supply node A and ground.
- the logic switches 30" are divided into n groups Gl, G2, ... Gn (where n is an integer), introducing different delays.
- FIG. 7 represents groups of two switches 30 ".
- the nodes A of switches 30" belonging to the same group are linked together.
- the nodes A of the switches of group G1 are connected to a supply voltage VDD.
- the nodes A of the switches of group G2 are connected to the nodes A of the switches of the group
- the nodes A of the switches of a group Gi (where i is between 2 and n) are connected to the nodes A of the switches of the group Gi-1 via resistance 40.
- the inverters 38 of the switches 30 "of the same group have the same supply voltage, and the inverters of two different groups have different supply voltages.
- the speed at which each inverter can bring a load (stage 26) connected to its output S at a voltage corresponding to a high logic state depends on the supply voltage of this inverter.
- the delays introduced by the 30 "switches of groups Gl, G2, .. .Gn depend on the supply voltage of the respective inverters 38 of these switches.
- the supply voltage of the inverters 38 depends on the voltage drops in the resistors 40 and these voltage drops depend on the number of inverters 38 whose state changes.
- the number of activated cells is large, which in the prior art caused large current peaks in the transistor 22, the number of inverters 38 whose state changes is large and the voltage drops in the resistors 40 are important. This implies that the delays introduced by the switches 30 "of Gl groups, G2, ... Gn are important, and it reduces current peaks in the transistor 22.
- the number of activated cells is low, the number of inverters 38 whose state changes is low and the voltage drops in the resistors 40 are low.
- the delays introduced by the switches 30 "of the groups Gl, G2, ... Gn are then insignificant and the line selection time is thus unimportant.
- Such a control circuit thus operates at an optimal speed while having transistors 22 of reduced size.
- the present invention is susceptible to various variants and modifications which will appear to a person skilled in the art.
- embodiments of the present invention have been described in which the column activation signal is delayed from a single VAL validation signal, but those skilled in the art will easily adapt the present invention to a embodiment in which one uses reads several delayed VAL validation signals produced from an initial VAL signal.
- the present invention has been described in relation to logic switches (30 ', 30 ") provided for receiving and supplying active logic signals at a high level, but a person skilled in the art will easily adapt the present invention to logic switches provided to receive and provide active logic signals at a low level.
- the present invention has been described in relation to a logic switch (30 ', 30 ") whose output is provided by an inverter (36, 38) intended to introduce a predetermined delay, but those skilled in the art will easily adapt the present invention to a logic switch also comprising other elements (such as a NAND logic gate) provided for introducing a predetermined delay.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
- Pulse Circuits (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0010609 | 2000-08-11 | ||
FR0010609A FR2812963B1 (fr) | 2000-08-11 | 2000-08-11 | Procede et circuit de commande de cellules d'un ecran a plasma |
PCT/FR2001/002590 WO2002015163A1 (fr) | 2000-08-11 | 2001-08-09 | Procede et circuit de commande d'un ecran a plasma |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1307874A1 true EP1307874A1 (fr) | 2003-05-07 |
EP1307874B1 EP1307874B1 (fr) | 2011-04-20 |
Family
ID=8853523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01963085A Expired - Lifetime EP1307874B1 (fr) | 2000-08-11 | 2001-08-09 | Procede et circuit de commande d'un ecran a plasma |
Country Status (5)
Country | Link |
---|---|
US (1) | US6853146B2 (fr) |
EP (1) | EP1307874B1 (fr) |
DE (1) | DE60144478D1 (fr) |
FR (1) | FR2812963B1 (fr) |
WO (1) | WO2002015163A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2880175A1 (fr) * | 2004-12-23 | 2006-06-30 | St Microelectronics Sa | Procede et dispositif de commande d'un ecran a plasma matriciel |
KR20070087706A (ko) * | 2005-05-10 | 2007-08-29 | 엘지전자 주식회사 | 플라즈마 디스플레이 장치 및 그의 구동 방법 |
FR2896610A1 (fr) * | 2006-01-20 | 2007-07-27 | St Microelectronics Sa | Procede et dispositif de commande d'un ecran a plasma matriciel |
FR2900266A1 (fr) * | 2006-04-19 | 2007-10-26 | St Microelectronics Sa | Procede de commande d'un ecran, en particulier d'un ecran a plasma, et dispositif correspondant |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4316123A (en) * | 1980-01-08 | 1982-02-16 | International Business Machines Corporation | Staggered sustain voltage generator and technique |
FR2662292B1 (fr) * | 1990-05-15 | 1992-07-24 | Thomson Tubes Electroniques | Procede de reglage de la luminosite d'ecrans de visualisation. |
US5732024A (en) * | 1995-04-19 | 1998-03-24 | Cirrus Logic, Inc. | Circuits, systems and methods for modifying data stored in a memory using logic operations |
FR2741468B1 (fr) * | 1995-11-17 | 1997-12-12 | Thomson Tubes Electroniques | Procede de commande d'un ecran de visualisation et dispositif de visualisation mettant en oeuvre ce procede |
FR2750525B1 (fr) * | 1996-06-28 | 1998-09-18 | Thomson Csf | Procede d'activation des cellules d'un ecran de visualisation d'image, et dispositif de visualisation d'image mettant en oeuvre le procede |
JP3447185B2 (ja) * | 1996-10-15 | 2003-09-16 | 富士通株式会社 | フラット表示パネルを利用した表示装置 |
FR2763735B1 (fr) * | 1997-05-22 | 1999-08-13 | Sgs Thomson Microelectronics | Etage de sortie de puissance pour la commande de cellules d'ecran a plasma |
FR2769743B1 (fr) * | 1997-10-09 | 2000-01-07 | Thomson Multimedia Sa | Procede et dispositif de balayage d'un panneau a plasma |
US6275070B1 (en) * | 1999-09-21 | 2001-08-14 | Motorola, Inc. | Integrated circuit having a high speed clock input buffer |
-
2000
- 2000-08-11 FR FR0010609A patent/FR2812963B1/fr not_active Expired - Fee Related
-
2001
- 2001-08-09 WO PCT/FR2001/002590 patent/WO2002015163A1/fr active Application Filing
- 2001-08-09 DE DE60144478T patent/DE60144478D1/de not_active Expired - Lifetime
- 2001-08-09 EP EP01963085A patent/EP1307874B1/fr not_active Expired - Lifetime
- 2001-08-09 US US10/110,449 patent/US6853146B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
See references of WO0215163A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP1307874B1 (fr) | 2011-04-20 |
US6853146B2 (en) | 2005-02-08 |
FR2812963B1 (fr) | 2003-07-25 |
DE60144478D1 (de) | 2011-06-01 |
US20030057852A1 (en) | 2003-03-27 |
FR2812963A1 (fr) | 2002-02-15 |
WO2002015163A1 (fr) | 2002-02-21 |
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Legal Events
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Effective date: 20020510 |
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