EP1299932A4 - Mehrfinger-stromballast-esd-schutzschaltung und verschachteltes ballastverfahren für esd-empfindliche schaltungen - Google Patents

Mehrfinger-stromballast-esd-schutzschaltung und verschachteltes ballastverfahren für esd-empfindliche schaltungen

Info

Publication number
EP1299932A4
EP1299932A4 EP01948390A EP01948390A EP1299932A4 EP 1299932 A4 EP1299932 A4 EP 1299932A4 EP 01948390 A EP01948390 A EP 01948390A EP 01948390 A EP01948390 A EP 01948390A EP 1299932 A4 EP1299932 A4 EP 1299932A4
Authority
EP
European Patent Office
Prior art keywords
source
circuit
fets
transistor
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01948390A
Other languages
English (en)
French (fr)
Other versions
EP1299932A1 (de
Inventor
Koen Gerard Maria Verhaege
Markus Paul Josef Mergens
Cornelius Christian Russ
John Armer
Phillip Czeslaw Joswiak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sofics Bvba
Sarnoff Corp
Original Assignee
Sofics Bvba
Sarnoff Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/881,422 external-priority patent/US6583972B2/en
Application filed by Sofics Bvba, Sarnoff Corp filed Critical Sofics Bvba
Publication of EP1299932A1 publication Critical patent/EP1299932A1/de
Publication of EP1299932A4 publication Critical patent/EP1299932A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0281—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements field effect transistors in a "Darlington-like" configuration
EP01948390A 2000-06-15 2001-06-15 Mehrfinger-stromballast-esd-schutzschaltung und verschachteltes ballastverfahren für esd-empfindliche schaltungen Withdrawn EP1299932A4 (de)

Applications Claiming Priority (17)

Application Number Priority Date Filing Date Title
US881422 1992-05-11
US21173500P 2000-06-15 2000-06-15
US211735P 2000-06-15
US21451300P 2000-06-28 2000-06-28
US214513P 2000-06-28
US26300501P 2001-01-19 2001-01-19
US263005P 2001-01-19
US27215901P 2001-02-28 2001-02-28
US272159P 2001-02-28
US27556301P 2001-03-14 2001-03-14
US275563P 2001-03-14
US28155201P 2001-04-04 2001-04-04
US281552P 2001-04-04
US28435601P 2001-04-17 2001-04-17
US284356P 2001-04-17
US09/881,422 US6583972B2 (en) 2000-06-15 2001-06-14 Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits
PCT/US2001/019213 WO2001097358A1 (en) 2000-06-15 2001-06-15 Multi-finger current ballasting esd protection circuit and interleaved ballasting for esd-sensitive circuits

Publications (2)

Publication Number Publication Date
EP1299932A1 EP1299932A1 (de) 2003-04-09
EP1299932A4 true EP1299932A4 (de) 2006-04-26

Family

ID=27575183

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01948390A Withdrawn EP1299932A4 (de) 2000-06-15 2001-06-15 Mehrfinger-stromballast-esd-schutzschaltung und verschachteltes ballastverfahren für esd-empfindliche schaltungen

Country Status (4)

Country Link
EP (1) EP1299932A4 (de)
JP (1) JP4942278B2 (de)
KR (1) KR20030019432A (de)
WO (1) WO2001097358A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224560B2 (en) * 2003-02-13 2007-05-29 Medtronic, Inc. Destructive electrical transient protection
KR100681205B1 (ko) * 2004-10-29 2007-02-09 주식회사 하이닉스반도체 정전기방전 보호회로를 위한 반도체소자
DE102005057129A1 (de) * 2005-11-30 2007-05-31 Infineon Technologies Ag Schaltungsanordnung, Verfahren zur Steuerung einer Schwellenspannung eines Transistors, Diferenzverstärker mit der Schaltungsanordnung sowie Verwendung der Schaltungsanordnung
CN100446240C (zh) * 2005-12-06 2008-12-24 上海华虹Nec电子有限公司 集成电路中的静电保护电路
CN100446239C (zh) * 2005-12-06 2008-12-24 上海华虹Nec电子有限公司 集成电路中的静电保护电路
US8144441B2 (en) 2006-08-30 2012-03-27 Triquint Semiconductor, Inc. Electrostatic discharge protection circuit for compound semiconductor devices and circuits
CN102025136A (zh) * 2009-09-17 2011-04-20 上海宏力半导体制造有限公司 一种静电放电保护电路
JP5864216B2 (ja) 2011-11-04 2016-02-17 ルネサスエレクトロニクス株式会社 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4825280A (en) * 1986-10-01 1989-04-25 Texas Instruments Incorporated Electrostatic discharge protection for semiconductor devices
US4845536A (en) * 1983-12-22 1989-07-04 Texas Instruments Incorporated Transistor structure
US5468667A (en) * 1993-03-31 1995-11-21 Texas Instruments Incorporated Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
EP0851552A1 (de) * 1996-12-31 1998-07-01 STMicroelectronics S.r.l. Schutzschaltung für eine Versorgungsleitung in einer integrierten Halbleitervorrichtung

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669080B2 (ja) * 1985-01-31 1994-08-31 株式会社東芝 半導体集積回路装置
NL8900593A (nl) * 1989-03-13 1990-10-01 Philips Nv Halfgeleiderinrichting met een beveiligingsschakeling.
US5477413A (en) * 1994-01-26 1995-12-19 Cypress Semiconductor Corp. ESD protection structure for P-well technology
JPH0993101A (ja) * 1995-09-28 1997-04-04 Hitachi Ltd コイル駆動回路
US5701024A (en) * 1995-10-05 1997-12-23 Cypress Semiconductor Corp. Electrostatic discharge (ESD) protection structure for high voltage pins
KR0164496B1 (ko) * 1995-12-02 1998-12-15 김광호 정전기보호소자
KR100188135B1 (en) * 1996-06-27 1999-06-01 Samsung Electronics Co Ltd Protection device of semiconductor device
JP2943738B2 (ja) * 1996-11-29 1999-08-30 日本電気株式会社 半導体装置における静電保護回路
JP3499140B2 (ja) * 1998-09-18 2004-02-23 株式会社東芝 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845536A (en) * 1983-12-22 1989-07-04 Texas Instruments Incorporated Transistor structure
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4825280A (en) * 1986-10-01 1989-04-25 Texas Instruments Incorporated Electrostatic discharge protection for semiconductor devices
US5468667A (en) * 1993-03-31 1995-11-21 Texas Instruments Incorporated Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
EP0851552A1 (de) * 1996-12-31 1998-07-01 STMicroelectronics S.r.l. Schutzschaltung für eine Versorgungsleitung in einer integrierten Halbleitervorrichtung

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
POLGREEN T L ET AL: "IMPROVING THE ESD FAILURE THRESHOLD OF SILICIDED N-MOS OUTPUT TRANSISTORS BY ENSURING UNIFORM CURRENT FLOW", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 39, no. 2, 1 February 1992 (1992-02-01), pages 379 - 388, XP000247214, ISSN: 0018-9383 *
See also references of WO0197358A1 *

Also Published As

Publication number Publication date
KR20030019432A (ko) 2003-03-06
EP1299932A1 (de) 2003-04-09
JP4942278B2 (ja) 2012-05-30
JP2004521477A (ja) 2004-07-15
WO2001097358A1 (en) 2001-12-20

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RIN1 Information on inventor provided before grant (corrected)

Inventor name: RUSS, CORNELIUS, CHRISTIAN

Inventor name: ARMER, JOHN

Inventor name: MERGENS, MARKUS, PAUL, JOSEF

Inventor name: JOSWIAK, PHILLIP, CZESLAW

Inventor name: VERHAEGE, KOEN, GERARD, MARIA

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SARNOFF EUROPE BVBA

Owner name: SARNOFF CORPORATION

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB NL

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Effective date: 20060310

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Ipc: H01L 27/02 20060101ALI20060306BHEP

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Effective date: 20060324