EP1287555A1 - Procede de formation d'un silicium epitaxial dope sur un substrat de silicium - Google Patents

Procede de formation d'un silicium epitaxial dope sur un substrat de silicium

Info

Publication number
EP1287555A1
EP1287555A1 EP01939124A EP01939124A EP1287555A1 EP 1287555 A1 EP1287555 A1 EP 1287555A1 EP 01939124 A EP01939124 A EP 01939124A EP 01939124 A EP01939124 A EP 01939124A EP 1287555 A1 EP1287555 A1 EP 1287555A1
Authority
EP
European Patent Office
Prior art keywords
silicon
amorphous silicon
doped amorphous
doped
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01939124A
Other languages
German (de)
English (en)
Inventor
Young Limb
Bradley P. Jones
Michael Maldei
Samuel C. Ramac
Colleen M. Snavely
Yun Yu Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Publication of EP1287555A1 publication Critical patent/EP1287555A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to process for forming epitaxial silicon on a silicon substrate.
  • the invention relates to the formation of doped epitaxial silicon by depositing doped amorphous silicon on a silicon substrate and annealing the doped amorphous silicon to form doped epitaxial silicon.
  • An “FET” is a field effect transistor.
  • MOSFET also called an insulated-gate FET, or IGFET
  • JFET junction-gate FET
  • An FET has a control gate, and source and drain regions formed in a substrate.
  • the control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
  • the conventional method of making a contact stud to the source-drain region of a MOSFET is to deposit an interlayer dielectric (ILD) after the MOSFET is fabricated on the substrate.
  • ILD interlayer dielectric
  • a contact hole is etched through the interlayer dielectric to the source-drain region.
  • the contact hole is filled with doped polysilicon by a blanket deposition of doped polysilicon using chemical vapor deposition (CVD).
  • CVD is a process for depositing a thin film of material onto a substrate by reacting the constituent elements in gaseous phase. CVD processes are used to produce thin, single-crystal films called epitaxial films.
  • the polysilicon on top of the interlayer dielectric is selectively removed by chemical mechanical polishing (CMP) or reactive ion etching (RTE).
  • CMP chemical mechanical polishing
  • RTE reactive ion etching
  • the polysilicon in the contact holes forms a contact stud.
  • the polysilicon is subsequently annealed to activate the dopant.
  • Contact studs formed by this process have a high stud resistance, however, due to scattering and dopant segregation at grain boundaries of the polysilicon.
  • the contact hole is filled with undoped monocrystalline silicon, which is doped by ion implantation and annealed to form epitaxial silicon.
  • the monocrystalline silicon is deposited by vapor phase deposition at greater than 1,000°C using silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 ), or silicon tetrachloride (SiCl ) as the silicon source.
  • silane SiH 4
  • dichlorosilane SiH 2 Cl 2
  • silicon tetrachloride SiCl
  • U.S. Patent No. 5,824,586 issued to Wollesen et al. incorporated in this document by reference, discloses a method for manufacturing raised silicon source and drain junctions by depositing undoped amorphous silicon on a source-drain region, ion implanting to form the source and drain junctions, and annealing the amorphous silicon at an elevated temperature so that epitaxial growth takes place in the source-drain region. The remaining amorphous silicon is removed.
  • this method requires a high temperature, use of this method with devices having small features is limited by the stringent thermal budget requirement of the device.
  • the need to dope the silicon by ion implantation is undesirable because it introduces additional process steps.
  • the method is difficult to use in a mass production environment.
  • U.S. Patent No. 5,250,454 issued to Maszara discloses a method for the self- aligned thickening of the source and drain contact regions in which an amorphous silicon layer is deposited using sputtering, electron beam evaporation, or any type of vacuum deposition system. Subsequently, the amorphous silicon layer is heated to induce solid state epitaxial regrowth on the silicon substrate.
  • the drawback of this method is the intrinsic problem of vacuum deposition: poor step coverage.
  • the aspect ratio of contact holes to silicon substrate of deep submicron features is typically greater than three. It is extremely difficult, if possible at all, to fill such contact holes with amorphous silicon by vacuum deposition technique.
  • An object of the present invention is to provide a process that is not limited by stringent thermal budget requirements.
  • a related object is to conduct the process at relatively low temperatures.
  • Another object is to avoid the problem of poor step coverage.
  • An additional object is to reduce the contact resistance of the device produced according to the process.
  • the present invention provides a process for forming doped, epitaxial, crystalline silicon on a monocrystalline silicon substrate.
  • the process produces good contact fill but does not introduce additional complexity to the fabrication process.
  • the process comprises the steps of:
  • This process allows the low-temperature formation of doped, crystalline, epitaxial silicon in a device opening having a very high aspect ratio.
  • the doped epitaxial silicon can partially or completely replace polycrystalline silicon with monocrystalline silicon, producing a drastic reduction in contact resistance.
  • the process can also be used to form a raised source- drain MOSFET.
  • Figs. 1, 2, 3, and 4 are schematic cross-sectional views illustrating the sequential fabrication of a source or drain contact stud using the process of the invention
  • Figs. 5, 6, and 7 are schematic cross-sectional views illustrating the sequential fabrication of a raised source- drain MOSFET using the process of the invention. More specifically,
  • Fig. 1 illustrates a semiconductor device having (1) a silicon substrate, in which a gate (including a thin dielectric layer, a conductive layer, and a dielectric layer) and source and drain regions have been fabricated, (2) an interlayer dielectric layer covering the silicon substrate, and (3) a contact hole etched through the interlayer dielectric layer to one of the source-drain regions;
  • Fig. 2 illustrates the structure shown in Fig. 1 after a layer of doped amorphous silicon is deposited on the surface of the device;
  • Fig. 3 illustrates the structure shown in Fig. 2 after the excess doped amorphous silicon on top of the interlayer dielectric layer is selectively removed;
  • Fig. 4 illustrates the structure shown in Fig. 3 after epitaxial growth has converted the doped amorphous silicon into doped crystalline epitaxial silicon;
  • Fig. 5 is a cross-sectional view of a semiconductor device comprising a silicon substrate, field oxide regions, source-drain regions, a gate region, a polysilicon gate formed on the gate region, gate sidewall spacers formed on either side of the gate region, and a doped amorphous silicon layer deposited on the device;
  • Fig. 6 illustrates the structure shown in Fig. 5 after the doped amorphous silicon is annealed
  • Fig. 7 illustrates the structure shown in Fig. 6 after the amorphous silicon has been removed.
  • the invention is not limited to constructions of any particular shape. Those skilled in the art will recognize that the positions and configuration of the doped regions vary with the design of the semiconductor device and that alternate designs are encompassed by the invention.
  • Fig. 1 is a cross-sectional view of a semiconductor device 10, comprising a silicon substrate 12 of which a gate 14, which comprises a thin dielectric layer 16, a conductive layer 18, and a dielectric layer 20 as well as source and drain regions 22 have been fabricated.
  • Thin dielectric layer 16 may be a layer of a dielectric material, such as silicon dioxide, having a thickness of about 100 A or less.
  • Conductive layer 18 may be a layer of a conductive material, such as polycrystalline silicon, having a thickness of about 2000 A.
  • Dielectric layer 20 may be a layer of a dielectric material, such as silicon nitride, having a thickness of about 2000 A. Preparation of semiconductor device 10 is conventional and can be effected by methods well known to those skilled in the art. As will be recognized by those skilled in the art, although the boundaries of silicon substrate 12 are not shown, the substrate typically comprises a number of devices and may comprise multilayer devices.
  • Interlayer dielectric layer 24 may be any low dielectric constant material known in the art to be useful as a dielectric material, such as silicon dioxide, polyimide, an organic siloxane polymer, poly-arylene ether, carbon-doped silicate glass or silsesquioxane glass, spin-on glass, fluorinated or non- fluorinated silicate glass, or diamond-like amorphous carbon.
  • Interlayer dielectric layer 24 can be deposited by chemical vapor deposition (CVD), including plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or spin coating.
  • the thickness of interlayer dielectric layer 24 is typically about 0.2 to about 2.0 microns.
  • a typical dielectric material is borophosphosilicate glass (BPSG).
  • Contact hole 26 has been etched through interlayer dielectric layer 24 to source- drain region 22 by, for example, reactive ion etching (RIE).
  • RIE reactive ion etching
  • contact hole 26 is about 100 to 1,000 nm in diameter.
  • contact hole 26 is about 250 nm in diameter.
  • a layer of doped amorphous silicon 28 is deposited on the surface of the device.
  • Deposition of doped silicon is conveniently conducted by low pressure chemical vapor deposition (LPCVD).
  • LPCVD is a method in which deposition gases are pyrolyzed in a LPCVD reactor to form the doped silicon using procedures well known to those skilled in the art.
  • doped amorphous silicon using one or more of phosphorous trichloride, t-butyl phosphine, i-butyl phosphine, tetramethyl phosphate, and tetramethyl phosphate as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 4,877,753 issued to Freeman.
  • In-situ doping of silicon using phosphine as the dopant and silane as the silicon source is disclosed in U.S. Patent No. 5,256,566 issued to Bailey.
  • the silicon is doped with arsenic or phosphorus ions.
  • p-type conductivity is desired, the silicon is doped with boron ions.
  • Deposition should be completed at a temperature at or below about 625 °C, preferably at or below 600°C. More preferably, deposition is completed at about 550°C, a pressure of about 300 mTorr, and a phosphine-to-silane ratio of about 0.0008 to form a phosphorus-doped amorphous silicon. Because doped amorphous silicon 28 is deposited by low pressure chemical vapor deposition, it fills contact hole 26 with good step coverage. For n-type conductivity, for example, the dopant level is typically about 1.2 x 10 20 phosphorus atoms/cm 3.
  • CMP chemical mechanical polishing
  • RLE reactive ion etching
  • doped amorphous silicon 28 is annealed at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon.
  • Conventional annealing is conducted at a temperature between about 550°C and 1,000°C, generally between 800°C and 570°C, preferably at about 570°C, for about 5 minutes to 10 hours, to induce epitaxial growth of the doped amorphous silicon.
  • Rapid thermal anneal is typically conducted at a temperature of about 1,000°C for 5 to 90 seconds.
  • the crystalline structure of underlying source- drain region 22 provides the seed for the epitaxial crystal growth of doped amorphous silicon 28. Epitaxial growth converts doped amorphous silicon 28 into doped crystalline epitaxial silicon 30.
  • FIG. 5 is a cross-sectional view of a semiconductor device 110 comprising a silicon substrate 112, field oxide regions 132, source-drain regions 122, and a gate region 134 formed on substrate 112.
  • Source-drain regions 122 comprise mono-crystalline silicon.
  • a polysilicon gate 136 is formed on gate region 134 and gate sidewall spacers 138 are formed on either side of gate region 134.
  • This structure is conventional and can be fabricated by methods well known to those skilled in the art.
  • a doped amorphous silicon layer 128 has been deposited as described above. The doped amorphous silicon layer typically is about 30 nm to 100 nm thick.
  • the doped amorphous silicon is annealed as described above at a temperature sufficient to induce epitaxial crystallization of the doped amorphous silicon.
  • the regions 140 of doped amorphous silicon layer 128 that are in contact with single crystal silicon undergo epitaxial growth.
  • the region 142 in contact with polycrystalline silicon is converted to poly-crystalline silicon.
  • the regions 144 not in contact with silicon, i.e., those regions over field oxide regions 132 or over gate spacer sidewalls 138, are not converted to epitaxial silicon, but remain as amorphous silicon.
  • the amorphous silicon has been removed by, for example, a hydrofluoric acid etch.
  • Raised epitaxial silicon regions 140 remain over source-drain regions 122.
  • Raised epitaxial silicon regions 140 serve as a sacrificial thickness for subsequent suicide formation and as a material for the underlying junction.
  • Processing of the device can be continued using well-known fabrication methods such as those disclosed at column 5, lines 33-56, of U.S. Patent No. 5,824,586 issued to Wollesen et al.
  • a layer of refractory metal such as titanium or cobalt, may be deposited on the MOSFET.
  • a rapid thermal anneal is conducted to form suicide in those regions in which the deposited metal overlies epitaxial silicon.
  • the refractory metal not converted to suicide is removed, producing a MOSFET in which the source and drain regions have been raised.
  • the present invention can be used in the manufacture of semiconductor devices, which are incorporated, for example, in digital computers.
  • the invention has been particularly shown and described with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and changes in form and details may be made without departing from the spirit and scope of the invention.
  • specific details are set forth to provide a more thorough understanding of the invention, but it will be apparent to those skilled in the art that the invention may be practiced without using these specific details.
  • the process of the invention can also be used in the fabrication of multi-level devices.
  • the invention is described with respect to formation of a contact stud to a source and drain region of a MOSFET, and with respect to formation of a raised source-drain MOSFET, it is not so limited.
  • the present invention may be used in any situation in which it is desired to form doped epitaxial crystalline silicon on a monocrystalline silicon substrate.

Abstract

L'invention concerne un procédé de formation d'un silicium épitaxial dopé sur un substrat de silicium. Le silicium amorphe dopé est déposé sur un substrat de silicium et recuit pour former un silicium cristallin épitaxial dopé. Un silicium cristallin épitaxial dopé peut être formé dans l'ouverture d'un dispositif présentant un facteur de forme très élevé à très basse température. Le silicium épitaxial dopé peut remplacer partiellement ou entièrement le silicium polycristallin par un silicium monocristallin, ce qui provoque une diminution radicale de la résistance au contact. Le procédé peut également être utilisé pour fabriquer un MOSFET de source-drain en relief.
EP01939124A 2000-05-31 2001-05-18 Procede de formation d'un silicium epitaxial dope sur un substrat de silicium Withdrawn EP1287555A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US58396200A 2000-05-31 2000-05-31
US583962 2000-05-31
PCT/US2001/016139 WO2001093326A1 (fr) 2000-05-31 2001-05-18 Procede de formation d'un silicium epitaxial dope sur un substrat de silicium

Publications (1)

Publication Number Publication Date
EP1287555A1 true EP1287555A1 (fr) 2003-03-05

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EP01939124A Withdrawn EP1287555A1 (fr) 2000-05-31 2001-05-18 Procede de formation d'un silicium epitaxial dope sur un substrat de silicium

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EP (1) EP1287555A1 (fr)
KR (1) KR100770460B1 (fr)
TW (1) TWI230410B (fr)
WO (1) WO2001093326A1 (fr)

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KR100882930B1 (ko) 2004-12-17 2009-02-10 삼성전자주식회사 소오스 및 드레인 영역들을 갖는 씨모스 반도체 소자들 및 그 제조방법들
CN101310378A (zh) * 2005-11-16 2008-11-19 Nxp股份有限公司 制造半导体器件的方法以及利用该方法获得的半导体器件
US8853862B2 (en) 2011-12-20 2014-10-07 International Business Machines Corporation Contact structures for semiconductor transistors
JP2013258188A (ja) * 2012-06-11 2013-12-26 Hitachi Kokusai Electric Inc 基板処理方法と半導体装置の製造方法、および基板処理装置

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GB8504725D0 (en) * 1985-02-23 1985-03-27 Standard Telephones Cables Ltd Integrated circuits
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
JP2695185B2 (ja) * 1988-05-02 1997-12-24 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5591674A (en) * 1991-12-30 1997-01-07 Lucent Technologies Inc. Integrated circuit with silicon contact to silicide
US5250454A (en) * 1992-12-10 1993-10-05 Allied Signal Inc. Method for forming thickened source/drain contact regions for field effect transistors
US5686335A (en) * 1996-07-22 1997-11-11 Taiwan Semiconductor Manufacturing Company, Ltd Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel
US5824586A (en) * 1996-10-23 1998-10-20 Advanced Micro Devices, Inc. Method of manufacturing a raised source/drain MOSFET

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Title
See references of WO0193326A1 *

Also Published As

Publication number Publication date
WO2001093326A1 (fr) 2001-12-06
KR100770460B1 (ko) 2007-10-26
TWI230410B (en) 2005-04-01
KR20030007804A (ko) 2003-01-23

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