EP1271440A1 - Hochspannungsregler mit externer Steuerung - Google Patents

Hochspannungsregler mit externer Steuerung Download PDF

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Publication number
EP1271440A1
EP1271440A1 EP01202429A EP01202429A EP1271440A1 EP 1271440 A1 EP1271440 A1 EP 1271440A1 EP 01202429 A EP01202429 A EP 01202429A EP 01202429 A EP01202429 A EP 01202429A EP 1271440 A1 EP1271440 A1 EP 1271440A1
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EP
European Patent Office
Prior art keywords
voltage
transistor
output
differential amplifier
terminal
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EP01202429A
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English (en)
French (fr)
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EP1271440B1 (de
Inventor
Arthur Descombes
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Priority to EP01202429A priority Critical patent/EP1271440B1/de
Priority to DE60115408T priority patent/DE60115408T2/de
Priority to AT01202429T priority patent/ATE311644T1/de
Publication of EP1271440A1 publication Critical patent/EP1271440A1/de
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Publication of EP1271440B1 publication Critical patent/EP1271440B1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates generally to a regulator circuit high-voltage making it possible to deliver at least a first regulated output voltage from a high input voltage, in particular of the order of a few tens of volts. More particularly, the present invention relates to such a high-voltage regulator in the form of an integrated circuit controlling an external device for regulation.
  • FIG. 1 shows a regulator circuit generally designated by the reference numeral 1 comprising an external regulating device 2, consisting of a JFET transistor, and a control circuit 10 of this external regulating device 2.
  • This regulating circuit 1 is designed to deliver a regulated output voltage V REG allowing the supply of an associated device, not shown.
  • This regulated output voltage V REG is derived from an input voltage V HV of high level of the order of a few tens of volts which can typically vary between 15 and 30 volts.
  • Such a voltage regulator circuit is used in particular in devices smoke detection, as described for example in the document EP-A1-0 759 602, to derive a regulated low level voltage (for example 5 volts) necessary inter alia for the supply of a microprocessor of the device of smoke detection.
  • a regulated low level voltage for example 5 volts
  • the line voltage supplying the smoke detection devices is for example of the order of 15 to 30 volts.
  • the regulator circuit 1 of FIG. 1 typically comprises a differential amplifier 4, one input of which is connected to the output of a voltage divider circuit 5, formed in this example of two resistors 51, 52 connected in series, the other input of the differential amplifier 4 being connected to a reference cell 6 delivering a reference voltage V REF .
  • This reference cell 6 is typically a cell delivering a reference voltage stable in temperature called "bandgap".
  • the output of the differential amplifier 4 is directly connected to the gate of the JFET transistor forming the regulation device 2.
  • the arrangement illustrated in FIG. 1 thus ensures that the voltage present at the output node of the voltage divider circuit 5, namely the connection node between the resistors 51 and 52, is substantially equal to the reference voltage V REF , the values R1, R2 of resistors 51 and 52 being chosen so that the regulated output voltage V REG of regulator circuit 1 has a determined value, for example of the order of 5 volts.
  • This regulated voltage V REG supplies in particular the differential amplifier 4 and the reference cell 6 of the regulator 1 as illustrated in FIG. 1.
  • a drawback of the regulator circuit of FIG. 1 lies in particular in the choice of the external regulating device 2 and the costs of this regulating device.
  • the JFET transistor must be chosen to resist relatively high drain-source voltages (in the example of the order of max. 25 volts), this drain-source voltage being in particular depending on the high input voltage V HV and the regulated voltage V REG which it is desired to deliver at the output of the regulator.
  • the cost of this JFET transistor increases with the maximum drain-source voltage to which this regulating element can be subjected. It is therefore desirable, in particular with a view to reducing costs, to propose an alternative solution to the solution presented in FIG. 1.
  • a serious disadvantage of the solution of Figure 1 therefore lies in the fact that its application is limited by the high input voltage likely to be applied to the regulator input as well as by the regulated output voltage that one wishes to deliver.
  • the limits imposed by technology would make the use of the regulator circuit of Figure 1 too expensive or even impossible, especially when you want to make this regulator in a technology below the micron.
  • the present invention therefore aims to provide a solution for remedy the aforementioned drawbacks, and in particular propose a solution allowing the use of a less expensive external regulating device as well as a solution that can be used with higher high input voltages.
  • Another object of the present invention is to propose a solution which can be produced and manufactured in CMOS technology below one micron, in particularly in 0.5 ⁇ m CMOS technology.
  • the present invention thus relates to a high-voltage regulator whose Features are set out in claim 1.
  • the regulating device external is advantageously controlled via a MOSFET transistor specific high-voltage likely to see at its terminals a drain-source voltage of the order of a few tens of volts.
  • a MOSFET transistor specific high-voltage likely to see at its terminals a drain-source voltage of the order of a few tens of volts.
  • the present invention requires the use of additional elements, the additional costs caused by the addition of these elements are nevertheless less than the savings that can be expected on the costs linked to the external regulation.
  • the high-voltage MOSFET transistors used in the framework of the present invention are perfectly compatible with technology Standard CMOS and require little or no masks and / or layout additional for their manufacture.
  • the circuit regulator is arranged to deliver a first regulated output voltage, called intermediate, as well as a second regulated output voltage allowing supply certain components of the regulator circuit, such as the differential amplifier and the regulator reference cell, as well as any electronics supply an associated device, such as for example the microprocessor responsible for the operations of a smoke detection device.
  • the voltage regulated intermediate is for example used, within the framework of the application to a smoke detection device, to supply the current necessary for the generation of the infrared pulse by the infrared diode with which these typically are equipped detection devices.
  • this preferred embodiment of the present invention allows the displacement of the infrared diode of the input on the output of the regulator circuit where the intermediate regulated voltage is delivered.
  • Voltage necessary for the generation of the infrared pulse in a device for detecting smoke is typically of the order of ten volts, that is to say much higher at the voltage levels used to power the electronics of the device.
  • this intermediate regulated voltage is of a level lower than the input voltage of the regulator circuit, thus reducing the losses during the generation of the infrared pulse, and nevertheless greater than the supply voltage of the electronics to ensure a supply level adequate for the generation of this infrared pulse.
  • the circuit regulator is arranged so that the differential amplifier controlling the device of external regulation presents a hysteresis, this ensuring in particular a stability increased operation of the regulator.
  • FIG. 2 shows a general block diagram of a high-voltage regulator circuit according to the present invention making it possible to deliver a regulated output voltage designated V REG1 .
  • this regulator circuit is generally designated by the reference numeral 1 and notably comprises an external regulating device 2, constituted in this example of a single JFET transistor with n channel, as well as an integrated circuit control generally designated by the reference numeral 10, for example made in the form of an ASIC.
  • the high input voltage V HV can vary in this example from approximately 15 to 50 volts.
  • the regulated output voltage V REG1 is in this example of the order of ten volts.
  • the external regulating device 2 comprises an input terminal 21 (the drain of the JFET transistor) connected to the high input voltage V HV , an output terminal 22 (the source of the JFET transistor) on which the supply voltage is delivered. regulated output V REG1 , and a control terminal 23 (the gate of the JFET transistor) by means of which the conduction state of the external regulation device 2 is controlled.
  • the control 23 and output 22 terminals are respectively connected to terminals 11 and 12 of the integrated circuit 10.
  • a terminal 13 of the integrated circuit 10 is connected to the ground V SS of the circuit.
  • the integrated circuit 10 essentially comprises a differential amplifier 4, a voltage divider circuit 5, a reference cell 6, as well as a high-voltage control element 3.
  • the voltage divider circuit 5 is formed in this example of two resistors 51, 52 connected in series between terminal 12 of the integrated circuit 10, namely the output terminal of the external regulation device 2, and the ground V SS of the circuit. It will obviously be understood that other voltage dividing circuits could be used by a person skilled in the art.
  • the regulator circuit 1 also typically comprises an external capacitive element C EXT1 forming a buffer connected to the output terminal 22.
  • connection node between the two resistors 51, 52 is connected to a first input terminal of the differential amplifier 4. It will be readily understood that the voltage applied to this first input terminal of the differential amplifier 4 as well as the regulated voltage V REG1 are proportional in a ratio determined by the values R1 and R2 of the resistors 51, 52.
  • the second input terminal of the differential amplifier 4 is connected in turn to the reference cell 6 producing a voltage of reference designated V REF , this reference cell 6 typically being a cell of the "bandgap" type delivering a reference voltage for example of the order of about 1.2 volts.
  • the output of the differential amplifier 4 is applied to the grid of a high-voltage MOSFET transistor 3 of a specific type.
  • This MOSFET transistor high-voltage 3 here of the n-channel type, is already known to those skilled in the art.
  • the particularity of this high-voltage transistor lies in particular in the structure specific for the gate oxide which has a greater thickness on the side drain only on the source side as well as in the presence of a buffer zone on the drain side consisting of an n-type box (or p for a high-voltage MOSFET transistor with p-channel).
  • FIGS 3a and 3b respectively show the diagrams of a transistor High-voltage n-channel MOSFET, or HVNMOS, and a p-channel MOSFET transistor high-voltage, or HVPMOS.
  • HVNMOS transistors include the advantage of a high breakdown voltage typically greater than 30 volts.
  • a another advantage of this type of transistor lies in the fact that their manufacture is fully compatible with standard CMOS technology.
  • the high-voltage MOSFET transistor 3 is connected, on the drain side, to the control terminal 23 of the external regulating device 2 via the terminal 11, and, on the source side, to ground V SS via terminal 13.
  • a resistor 30 of value R0 is connected between terminals 11 and 12 of the integrated circuit 10, namely between the control 23 and output 22 terminals of the external regulation device 2. It will be noted that this resistor 30 is only necessary in the case where the external regulation device 2 consists of a JFET transistor as illustrated. In the event that the external regulation device was produced in the form of an arrangement of bipolar transistors as illustrated in FIG. 8, this resistor 30 is no longer necessary.
  • the differential amplifier 4 as well as the reference cell 6 are supplied by a supply voltage V DD , for example of the order of 3 volts.
  • V DD a supply voltage
  • this supply voltage V DD is advantageously also supplied by the regulator circuit 1 itself.
  • the only elements which must support high voltages across their terminals are transistor 3 and resistors 30, 51 and 52, these the latter being advantageously integrated in the form of regions of diffusion of type n or "n-well" resistors.
  • the differential amplifier 4 is a conventional differential amplifier that must only support low voltages at its terminals.
  • FIG. 4 shows an advantageous variant of the regulator circuit according to the invention in which the integrated circuit 10 further comprises means, generally designated by the reference numeral 100, for delivering a second regulated output voltage V REG2 advantageously making it possible to supply various electronic components of the regulator circuit, such as in particular the differential amplifier 4 and the reference cell 6, or other electronic components associated with the regulator.
  • the regulated output voltage V REG2 is used as the supply voltage V DD for the differential amplifier 4 and the reference cell 6.
  • the means 100 preferably comprise, as illustrated, a second n-channel high-voltage MOSFET transistor designated by the reference numeral 101, a regulating element 102 constituted in this example of a p-MOS transistor, a differential amplifier 104 and a voltage divider circuit 105.
  • the high-voltage MOSFET transistor 101 is analogous to transistor 3 and is connected by its drain terminal to the output terminal 22 of the external device regulation 2, and, through its source terminal to the source terminal of the p-MOS transistor 102.
  • the gate of the high-voltage MOSFET transistor 101 is connected to the divider circuit of voltage 5 at the connection node between resistors 53 and 54.
  • These resistors 53 and 54 in series replace the resistor 51 of FIG. 2 and the sum of the values R11 and R12 of these resistors 53 and 54 is equivalent to the value R1 of the resistance 51 of FIG. 2.
  • the division ratio of the voltage divider circuit 5 thus remains unchanged with regard to the voltage applied to the input of the amplifier differential 4.
  • the ratio of resistors R11, R12 and R2 is chosen so that the voltage applied to the gate of the high-voltage transistor 101 causes a determined potential drop between the drain and source of this transistor 101, the voltage present on the source of this transistor 101 then being representative of the output voltage V REG1 minus the determined potential drop present across the transistor 101. It will therefore be understood that the essential role of the high-voltage transistor 101 is to lower the output voltage V REG1 to a level tolerable for downstream circuits.
  • the voltage divider circuit 105 is constituted in this example of the series arrangement, between the drain terminal of the p-MOS transistor 102 and the ground V SS , of two resistors 151 and 152, the division ratio of this divider circuit 105 being determined by the values R3 and R4 of these resistances.
  • the second regulated output voltage V REG2 is supplied to a terminal 14 of the integrated circuit 10 on the drain terminal of the p-MOS transistor 102 at the terminals of the voltage divider circuit 105, a second capacitive element C EXT2 forming a buffer being typically connected to this terminal 14.
  • connection node between the two resistors 151 and 152 is connected to a first input terminal of the differential amplifier 104.
  • the voltage applied to this first input terminal of the differential amplifier 104 as well as the second output voltage regulated V REG2 are proportional in a ratio determined by the values R3 and R4 of the resistors 151, 152.
  • the second input terminal of the differential amplifier 104 is connected, in a similar manner to the differential amplifier 4, to the reference 6 producing the reference voltage V REF .
  • the output of the differential amplifier 104 is applied to the gate of the p-MOS transistor 102.
  • the arrangement of the differential amplifier 104 illustrated in FIG. 4 requires that the voltage present at the output node of the circuit voltage divider 105, namely the connection node between the resistors 151 and 152, is substantially equal to the reference voltage V REF , the values R3 and R4 of the resistors being chosen so that the second regulated output voltage V REG2 of the regulator circuit 1 has a determined value, for example of the order of 3 volts.
  • This regulated voltage V REG2 supplies in particular the differential amplifier 4 and the reference cell 6 of the regulator 1 as already mentioned.
  • the supply of the differential amplifier 104 is ensured, on the one hand, by the ground V SS and, on the other hand, by the voltage present at the source terminal of the transistor p -MOS 102.
  • a capacitive element 106 is disposed on the output of the differential amplifier 104 between the gate and drain terminals of the p-MOS transistor 102. This capacitive element 106 ensures stability of the regulated output voltage V REG2 .
  • the regulator circuit according to the invention allows the displacement of the infrared diode of the detector, necessary for the generation of the infrared pulse, from the input to the output of the circuit.
  • regulator on terminal 12 of the circuit where the regulated output voltage V REG1 is delivered.
  • FIG. 4 schematically shows the arrangement of this infrared diode indicated by the reference numeral 200 and of the control means 210 mounted in series with the diode 200, here a bipolar transistor, allowing the triggering of the infrared pulse.
  • the present invention allows thus a reduction in losses during the generation of the infrared pulse, in particular because the regulated voltage used for this generation is less than the input voltage.
  • the infrared diode and its control means are placed at the high-voltage input 21, the regulated output voltage not being sufficient to supply this diode infrared and allow the generation of the required pulse.
  • the differential amplifier 4 used in the circuit Figure 2 or 4 regulator is a conventional type differential amplifier an exemplary embodiment of which is illustrated in FIG. 6.
  • the differential amplifier 4 illustrated in FIG. 6 comprises a differential pair of transistors M1, M2 (in two identical p-MOS transistors), the gates of which form the inputs of the differential amplifier 4.
  • Each transistor M1, M2 is connected in series in the reference branch of a current mirror 41, 42, each mirror of current 41, 42 conventionally comprising two n-MOS M11 transistors, M12 and M21, M22 connected grid to grid.
  • the transistors M12 and M22 of the branches of output of current mirrors 41 and 42 are themselves connected respectively in the reference and output branches of another designated current mirror globally by reference numeral 43 and comprising two p-MOS transistors M13 and M23.
  • the output of the differential amplifier 4 is formed by the node of connection between p-MOS M23 and n-MOS M22 transistors of the output branch of current mirror 43.
  • a p-MOS transistor M3 connected between the power supply terminal V DD and the connection node of the p-MOS transistors M1, M2 of the input differential pair ensures adequate biasing of the transistors, a determined bias voltage V BIAS being applied to the gate of this p-MOS transistor M3.
  • the differential amplifier 4 further comprises an additional output stage comprising p-MOS M5 and n-MOS M6 transistors forming an inverter arrangement making it possible to deliver the output signal designated OUT and its inverse.
  • OUT_B a p-MOS transistor M4 controlled by the bias voltage V BIAS being connected in series with these transistors M5, M6 in order to ensure an adequate bias of the latter.
  • V BIAS bias voltage
  • the differential amplifier 104 used in the regulator circuit of FIG. 4 must be designed to tolerate higher voltages across its terminals and may be produced on the basis of a diagram analogous to the differential amplifier 4 of FIG. 6 by using cascode assemblies well known to those skilled in the art, that is to say assemblies of two or more transistors in series.
  • Figure 7 shows a exemplary embodiment of such a differential amplifier using techniques of cascode editing.
  • the transistors Q1, Q2, Q11, Q12, Q21, Q22, Q13, Q23 and Q3 essentially fulfill the same roles as the transistors M1, M2, M11, M12, M21, M22, M13, M23 and M3 of the circuit of figure 6
  • Cascode arrangements are used in order to limit the voltages likely to appear at the terminals of the transistors of this differential amplifier 104, in particular the transistors connected between the supply voltages V P and Vss. It will be noted that the voltage V P is taken from the source of the high-voltage MOSFET transistor 101.
  • the transistors Q12 and Q22 are each connected in series respectively with a second n-MOS transistor Q51 disposed between the transistors Q12 and Q13 and a second n-MOS transistor Q52 disposed between transistors Q22 and Q23.
  • the transistors Q3 and Q23 are each connected in series with a second p-MOS transistor Q41 disposed between the transistor Q3 and the connection node of the differential pair and a second p-MOS transistor Q42 disposed between the transistors Q22 and Q23 .
  • the output terminal of the differential amplifier 104 is formed by the connection node between the transistors Q42 and Q52.
  • n-MOS transistor Q50 conventionally forms a current mirror with transistors Q51 and Q52.
  • a p-MOS transistor additional Q40 conventionally forms a current mirror with the transistors Q41 and Q42.
  • Each of these Q40 and Q50 transistors is connected in series with cascode mounting of two transistors p-MOS Q43, Q44 and n-MOS respectively Q53, Q54.
  • the n-MOS transistor Q54 still forms a current mirror with a other n-MOS Q55 transistor connected in series in the branch comprising the p-MOS transistors Q40, Q43 and Q44.
  • the bias of the transistors is fixed by a bias current I BIAS applied in the current path of a p-MOS transistor Q31 connected in current mirror with the transistor Q3, this bias current I BIAS itself being mirrored in the branch comprising the n-MOS transistors Q50, Q53 and Q54 by means of a p-MOS transistor Q32.
  • the assembly illustrated in FIG. 7 ensures that none of the transistors of this differential amplifier 104 sees too high a voltage across its terminals to cause a breakdown of this transistor.
  • the configuration of Figure 7 is given only by way of example only, the skilled person can make many modifications to the diagram presented, or even choose a alternative configuration. It will be noted that the differential amplifier 104 must basically respond to higher constraints than the differential amplifier 4 since this is supplied by a higher voltage, in this example typically in the range of 4 to 7 volts.
  • FIG. 5 shows another advantageous variant of the regulator circuit according to the invention substantially similar to the variant of FIG. 4.
  • the differential amplifier 4 of the regulator circuit 1 is arranged to present a hysteresis.
  • This hysteresis has the advantage of making the stability of the regulator less critical and as a consequence a periodic variation of the first regulated voltage V REG1 .
  • the regulator of FIG. 5 thus forms a “bang-bang” type regulator delivering a regulated voltage varying between two determined voltage levels.
  • the differential amplifier 4 forms in this example a comparator, that is to say that it supplies output signals OUT and OUT_B of logic levels.
  • the hysteresis of the differential amplifier can be generated from various ways. One of them is illustrated schematically in Figure 5 and makes call to two transmission doors 7, 8 connected to the input on which is applied the output voltage of the voltage divider circuit 5, and an inverter 9 connected to the output of the differential amplifier 4.
  • the divider circuit 5 is also slightly modified so that the resistor 54 is subdivided into two resistors 55 and 56, the sum of the values R121 and R122 is equivalent to the value R12 of the resistor 54 of FIG. 4.
  • the hysteresis is determined by the ratio of the values R11, R121, R122 and R2 of the resistors 53, 55, 56 and 52.
  • connection node between resistors 55 and 56 is connected to the input of the first transmission door 7 and the connection node between the resistors 56 and 52 is connected to the input of the second transmission door 8.
  • the state of transmission doors 7 and 8 is controlled according to the output of the amplifier differential 4, the transmission doors 7 and 8 being respectively passing and non-passing when the output signal (not inverted) of the differential amplifier 4 is at the high state, and, on the other hand, respectively non-passing and passing when the signal of the differential amplifier 4 is low.
  • the exit inverted OUT_B of differential amplifier 4 is connected to the inverting terminal of door 7 and the non-inverting terminal of door 8, this inverted output OUT_B being also applied, via the inverter 9, to the non-inverting terminal of the door 7 and the reversing terminal on door 8.
  • the JFET transistor used as an external control device 2 in the embodiments described above could be replaced by another suitable device.
  • the JFET transistor can advantageously be replaced by the device illustrated in the figure 8 consisting of a montage conventionally named "pseudo-Darlington" comprising two complementary bipolar transistors, namely a transistor bipolar type pnp B1 and a bipolar transistor type npn B2.
  • a Darlingtion assembly comprising two bipolar transistors of the same type could alternatively be used instead of the pseudo-Darlingtion assembly of the figure 8.
  • the emitter and the collector of the transistor B1 respectively form the input 21 on which the high input voltage V HV is applied and the output 22 on which the regulated output voltage V is delivered REG1 , the base of this transistor B1 being connected to the collector of the bipolar transistor B2, the emitter of this transistor B2 being connected to the collector of the transistor B1.
  • the base of transistor B2 forms the control terminal 23 of the external regulation device.
  • this external regulation device 2 further comprises a resistor 25 mounted in parallel between the input terminal 21 and the control terminal 23.
  • the device illustrated in Figure 8 includes a higher number of components, the costs of this device are nevertheless lower than the costs linked the use of a JFET transistor, this therefore constituting an advantage in terms of optics a reduction in the manufacturing costs of the regulator circuit.
  • the regulator circuit according to the invention is not in no way limited by the type of external regulating device used in the modes aforementioned embodiments, namely a JFET transistor.
  • other suitable arrangements such as the arrangement in FIG. 8, can be used by the skilled person.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Details Of Television Scanning (AREA)
  • Electrophonic Musical Instruments (AREA)
EP01202429A 2001-06-25 2001-06-25 Hochspannungsregler mit externer Steuerung Expired - Lifetime EP1271440B1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP01202429A EP1271440B1 (de) 2001-06-25 2001-06-25 Hochspannungsregler mit externer Steuerung
DE60115408T DE60115408T2 (de) 2001-06-25 2001-06-25 Hochspannungsregler mit externer Steuerung
AT01202429T ATE311644T1 (de) 2001-06-25 2001-06-25 Hochspannungsregler mit externer steuerung

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EP01202429A EP1271440B1 (de) 2001-06-25 2001-06-25 Hochspannungsregler mit externer Steuerung

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EP1271440B1 EP1271440B1 (de) 2005-11-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9647537B2 (en) 2013-09-23 2017-05-09 Commissariat à l'énergie atomique et aux énergies alternatives Charge pump circuit for generating a negative voltage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611335A (en) * 1968-11-13 1971-10-05 Bbk Electronics Inc Multiple combustion sensing device with false alarm prevention
US3913082A (en) * 1973-02-02 1975-10-14 Jenson Robert S Ionization aerosol detector
JPS63217231A (ja) * 1987-03-06 1988-09-09 Nohmi Bosai Kogyo Co Ltd 輻射式火災検知器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611335A (en) * 1968-11-13 1971-10-05 Bbk Electronics Inc Multiple combustion sensing device with false alarm prevention
US3913082A (en) * 1973-02-02 1975-10-14 Jenson Robert S Ionization aerosol detector
JPS63217231A (ja) * 1987-03-06 1988-09-09 Nohmi Bosai Kogyo Co Ltd 輻射式火災検知器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 009 (P - 811) 11 January 1989 (1989-01-11) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9647537B2 (en) 2013-09-23 2017-05-09 Commissariat à l'énergie atomique et aux énergies alternatives Charge pump circuit for generating a negative voltage

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EP1271440B1 (de) 2005-11-30
DE60115408T2 (de) 2006-08-24
DE60115408D1 (de) 2006-01-05
ATE311644T1 (de) 2005-12-15

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