EP1222531B1 - Mehrfachinstanzimplementierung von sprachkodierer-dekodierern - Google Patents

Mehrfachinstanzimplementierung von sprachkodierer-dekodierern Download PDF

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Publication number
EP1222531B1
EP1222531B1 EP19990948014 EP99948014A EP1222531B1 EP 1222531 B1 EP1222531 B1 EP 1222531B1 EP 19990948014 EP19990948014 EP 19990948014 EP 99948014 A EP99948014 A EP 99948014A EP 1222531 B1 EP1222531 B1 EP 1222531B1
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EP
European Patent Office
Prior art keywords
memory
codec
dsp
instance
segments
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Expired - Lifetime
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EP19990948014
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English (en)
French (fr)
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EP1222531A1 (de
Inventor
Wenshun Tian
Foo Yuen Leong
Antonio Mario Alvarez-Tinoco
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STMicroelectronics Asia Pacific Pte Ltd
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STMicroelectronics Asia Pacific Pte Ltd
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/16—Vocoder architecture
    • G10L19/18—Vocoders using multiple modes

Definitions

  • This invention relates to audio coding, and is particularly applicable in the field of telecommunication and the internet, for example, in which multi-channel speech coders are implemented using a single digital signal processing (DSP) device.
  • DSP digital signal processing
  • WO 99/10807 discloses how multi-instanced software can be utilized to implement a plurality of virtual modems which can be used simultaneously. Entire controllerless software modems operate multi-instanced with a single code set. Two software modules interface with the DSP hardware. The modem control layer manipulates DSP modes, creates an destroys modem connections, and monitors modem activity. The Line I/O Layer is responsible for transferring data to and from the DSP.
  • An alternative is to provide the audio codec functions in software (firmware, micro-code, etc.) for operation on a more general purpose Digital Signal Processor ("DSP").
  • DSP Digital Signal Processor
  • a powerful DSP to process a plurality of different audio signals or channels in real-time, to thereby implement a plurality of voice coders (''vocoders”) using a single processing device.
  • the present invention also provides a data coding and/or decoding system in which a plurality of encoders and/or decoders (codecs) are implemented using a single digital signal processing (DSP) device, comprising:
  • a third memory is also provided which is accessible by each of the codec instances for shared storage of temporary variables and data buffering in encoding/decoding said respective separate data streams.
  • Each codec instance preferably accesses the corresponding memory segment using indirect addressing based on at least one index register, the at least one index register being set for each codec instance to modify addressing of variables for that codec instance to the corresponding memory segment.
  • the plurality of memory segments are contiguous in the second memory, and the at least one index register is set for each codec instance according to an offset based on the difference in address from a first of said memory segments to the memory segment corresponding to that codec instance.
  • each of the memory segments in said second memory is the same size.
  • the first memory is provided with a plurality of instruction code programs for implementing different kinds of codecs, wherein different codec instances may be selected from the different kinds of codec.
  • each of the memory segments in the second memory is the same size, and the size of the memory segments is selected according to the maximum memory required by any of the plurality of different kinds of codec.
  • This methodology can be used to modify the existing DSP assembly code or to implement a new algorithm with a multiple instance feature.
  • the multiple-instance implementation can be used to process multi-channel signals using one software module.
  • the embodiments of the invention described hereinbelow are in the context of audio coders implemented by instruction codes in the form of software, firmware or micro-code operating on a general purpose digital signal processor chip.
  • the described embodiments relate to implementation of speech codecs of the type which is the subject of ITU-T Recommendation G.729.
  • the present invention is not necessarily limited to such an environment, and may further be used to implement coders for other forms of real-time data streams including other forms of voice and/or facsimile transmission or storage coding.
  • a simple audio encoding system 10 based on a general purpose DSP is illustrated in block diagram form in Figure 1.
  • the audio coding system 10 comprises a digital signal processor (DSP) 12 which is coupled to receive input data and produce coded output signals.
  • the DSP 10 is coupled to a storage memory 14.
  • the memory 14 provides data to the DSP 12 to enable coding of the received input data to take place.
  • the memory 14 may contain various different forms of data, including read-only data which is permanently stored in the memory, and temporary data which is transiently stored during coding operations.
  • the memory 14 may also contain stored instruction codes used by the DSP to perform the coding, which would ordinarily be permanently stored in read-only form.
  • One of the considerations which must be dealt with in implementing multiple codecs on a single DSP by operating multiple instances of the DSP instruction codes which control the codec operation is the arrangement of storage memory so that each instance of the codec can have efficient memory usage and not interfere with other codec instances in use at the same time.
  • this is achieved by arranging the data memory as illustrated in the block diagram of Figure 2.
  • This exemplary embodiment relates to implementation of a 4-channel multiple instance vocoder on a single DSP.
  • the data memory is partitioned into different parts, in this case comprising read-only memory (ROM), local RAM, and static RAM.
  • the ROM is used to store all the read only data, which may include the program instruction codes and the like.
  • the static RAM is used for storage of temporary variables and for data buffering.
  • the static RAM is used for storage of all the global and historical variables required for the coding operations, for example data which will be used for processing the next frame of output As shown in the block diagram, in this case the static RAM is partitioned into separate areas for each DSP codec instance.
  • the preferred form of the present invention involves partitioning the data memory based on their properties and using an index register or index modifier to modify the address of the static RAM segment data used for each codec instance.
  • the program code memory can be arranged as usual. If, however, program memory is used for data accessing, this part of memory also needs to be partitioned in the same way as data memory such as X or Y. This methodology allows the easy management of the operating system or real-time kernel due to the facility of opening and closing the various instances.
  • the partition of the data memory according to its accessing property is obtained, for example in the embodiment shown in Figure 2 involving ROM data, temporary local RAM, and static or global RAM segments.
  • the data ROM and temporary local RAM are shared for every instance. Only the static RAM segments are used exclusively by corresponding codec instances.
  • This static RAM segment is accessed using an index register by adding an offset value to address the static RAM segment for a particular instance.
  • index registers In order to pass the addressing information to every channel vocoder, two index registers should be reserved for this reentrant purpose, say IX2 and IY2 if using a D950 DSP. By doing so, the address of all the static variables stored in the respective static RAM segments will be modified by these two index registers from the beginning.
  • the multiple-instance 4-channel system can operate as follows,
  • This is applicable for a new implementation or for converting existing DSP instruction coding to a re-entrant multiple instance implementation. Since this method does not require a change of the variable names in the DSP coding, it is efficient in both MIPS and porting effort if compared to using pointers.
  • the memory may be arranged as illustrated in Figure 3, for which the multiple-instance accessing procedures are described below.
  • the memory map for a 4-channel system is shown, in which the 4 active channels could be any possible combination of codecs operating according to ITU-T G729, G723.1 and FAX.
  • the size of ROM segment comprises ROM data for all of the codec types.
  • the size of the temporary local RAM segment is the maximum local RAM size used by any of the codecs. All of the different codecs share the local RAM segment.
  • each of the static RAM segments are of a size to accommodate the frame processing storage requirements of any one of the possible codecs implementations. This enables different codecs to make use of different static RAM segments.
  • One example is a 4-channel System with two different speech codecs, say G723.1 and G729.
  • the program instruction codes are, in this example, stored separately in a program memory (not shown).
  • the data memory is arranged as shown in Figure 3.
  • Such a 4-channel system multiple instance system can operate as follows,

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  • Engineering & Computer Science (AREA)
  • Computational Linguistics (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Claims (14)

  1. Verfahren zum Implementieren einer Vielzahl an Encodern und/oder Decodierern (Codecs), welches eine einzige digitale Signalprozessor- (DSP) Vorrichtung anwendet, wobei die Funktion jedes Codecs durch den DSP nach einem Operationscodeprogramm ausgeführt wird, wobei das Verfahren folgende Schritte umfasst:
    Schaffen eines Operationscodeprogramms, welches in einem ersten Speicher zur Steuerung des DSP als Codec zu funktionieren gespeichert ist;
    Schaffen eines zweiten Speichers, welcher eine Vielzahl an Speichersegmenten umfasst;
    Implementieren einer Vielzahl an Codecs mittels des DSP durch Ausführen des Operationscodeprogramms im ersten Speicher mehrere Male und in ablaufinvarianten Vorgängen,
    wobei jeder Codecvorgang mit Zugang zu einem entsprechendem separaten Speichersegment im zweiten Speicher zum Speichern von Daten versehen ist, welche beim Encodieren/Decodieren eines entsprechenden separaten Datenstroms verwendet werden.
  2. Verfahren nach Anspruch 1, wobei ein dritter Speicher vorgesehen ist, welcher durch jeden Codecvorgang für geteiltes Speichern temporärer Variablen und Datenpufferung beim Encodieren/Decodieren der entsprechenden separaten Datenströme zugänglich ist.
  3. Verfahren nach Anspruch 1 oder 2, wobei jeder Codecvorgang auf das entsprechende Speichersegment mittels indirekter Adressierung zugreift, welche auf mindestens einem Indexregister basiert, wobei mindestens ein Indexregister für jeden Codecvorgang eingestellt ist, um die Adressierung von Variablen für diesen Codecvorgang an das entsprechende Speichersegment zu ändern.
  4. Verfahren nach Anspruch 3, wobei die Vielzahl an Speichersegmenten im zweiten Speicher benachbart sind und das zumindest eine Indexregister für jeden Codecvorgang nach einer Distanzadresse eingestellt ist, welche auf dem Unterschied von Adressen aus einem ersten der Speichersegmente zu einem Speichersegment, welches diesem Codecvorgang entspricht, basiert.
  5. Verfahren nach einem der Ansprüche 1 bis 4, wobei alle Speichersegmente im zweiten Speicher die gleiche Größe aufweisen.
  6. Verfahren nach Anspruch 1, 2, 3 oder 4, wobei der erste Speicher mit einer Vielzahl an Operationscodeprogrammen zum Implementieren verschiedener Codecarten versehen ist, und wobei unterschiedliche Codecvorgänge aus den verschiedenen Codecarten ausgewählt werden können.
  7. Verfahren nach Anspruch 6, wobei alle Speichersegmente im zweiten Speicher gleichgroß sind und die Speichersegmentgröße nach dem durch irgendeinen der Vielzahl an unterschiedlichen Codecarten benötigten Maximalspeicher ausgewählt wird.
  8. Datencodier- und/oder Decodieranlage, in welchem eine Vielzahl an Encodern und/oder Decodieren (Codecs) mittels einer einzigen digitalen Signalprozessor- (DSP) Vorrichtung implementiert sind, welche folgendes umfasst:
    einen digitalen Signalprozessor (DSP);
    einen ersten an den DSP gekoppelten Speicher, welcher ein Operationscodeprogramm enthält, wobei die Funktion jedes Codecs durch den DSP bei Betrieb nach dem Operationscodeprogramm ausgeführt wird;
    einen zweiten an den DSP gekoppelten Speicher, welcher unterteilt ist, um eine Vielzahl an separaten Speichersegmenten zu umfassen;
    wobei eine Vielzahl an Codecs mittels des DSP durch Ausführen des Operationscodeprogramms im ersten Speicher mehrere Male und in ablaufinvarianten Vorgängen implementiert ist, wobei jeder Codecvorgang mit Zugang zu einem entsprechendem separaten Speichersegment im zweiten Speicher zum Speichern von Daten versehen ist, welche beim Encodieren/Decodieren entsprechender separater Datenströme verwendet werden.
  9. Anlage nach Anspruch 8, welche einen dritten an den DSP gekoppelten Speicher umfasst, welcher durch jeden Codecvorgang für geteiltes Speichern temporärer Variablen und Datenpufferung beim Encodieren/Decodieren der entsprechenden separaten Datenströme zugänglich ist.
  10. Anlage nach Anspruch 8 oder 9, wobei jeder Codecvorgang auf das entsprechende Speichersegment mittels indirekter Adressierung zugreift, welche auf mindestens einem Indexregister basiert, wobei mindestens ein Indexregister für jeden Codecvorgang eingestellt ist, um die Adressierung von Variablen für diesen Codecvorgang an das entsprechende Speichersegment zu ändern.
  11. Anlage nach Anspruch 10, wobei die Vielzahl an Speichersegmenten im zweiten Speicher benachbart sind und das zumindest eine Indexregister für jeden Codecvorgang nach einer Distanzadresse eingestellt ist, welche auf dem Unterschied von Adressen aus einem ersten der Speichersegmente zu einem Speichersegment basiert, welches diesem Codecvorgang entspricht.
  12. Anlage nach einem der Ansprüche 8 bis 11, wobei alle Speichersegmente im zweiten Speicher die gleiche Größe aufweisen.
  13. Anlage nach einem der Ansprüche 8 bis 11, wobei der erste Speicher mit einer Vielzahl an Operationscodeprogrammen zum Implementieren verschiedener Codecarten versehen ist, und wobei unterschiedliche Codecvorgänge aus den verschiedenen Codecarten ausgewählt werden können.
  14. Anlage nach Anspruch 13, wobei alle Speichersegmente im zweiten Speicher gleichgroß sind und die Speichersegmentgröße nach dem durch irgendeinen der Vielzahl an unterschiedlichen Codecarten benötigten Maximalspeicher ausgewählt wird.
EP19990948014 1999-09-29 1999-09-29 Mehrfachinstanzimplementierung von sprachkodierer-dekodierern Expired - Lifetime EP1222531B1 (de)

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PCT/SG1999/000095 WO2001023993A1 (en) 1999-09-29 1999-09-29 Multiple instance implementation of speech codecs

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EP1222531A1 EP1222531A1 (de) 2002-07-17
EP1222531B1 true EP1222531B1 (de) 2003-11-12

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WO2003081423A1 (en) * 2002-03-22 2003-10-02 Telefonaktiebolaget Lm Ericsson Method for processing data streams divided into a plurality of process steps
WO2020220935A1 (zh) * 2019-04-27 2020-11-05 中科寒武纪科技股份有限公司 运算装置
US11841822B2 (en) 2019-04-27 2023-12-12 Cambricon Technologies Corporation Limited Fractal calculating device and method, integrated circuit and board card

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US5285264A (en) * 1990-03-30 1994-02-08 Kabushiki Kaisha Toshiba Image reproduction apparatus with plural program processing
JP2773601B2 (ja) * 1993-06-11 1998-07-09 ヤマハ株式会社 信号処理装置
US6341368B1 (en) * 1997-08-22 2002-01-22 Cirrus Logic, Inc. Method and systems for creating multi-instanced software with a preprocessor

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DE69912860D1 (de) 2003-12-18
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