Classifications

• • G—PHYSICS
  • G10—MUSICAL INSTRUMENTS; ACOUSTICS
  • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
  • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
  • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
  • G10L19/16—Vocoder architecture
  • G10L19/18—Vocoders using multiple modes

Definitions

• This invention relates to audio coding, and is particularly applicable in the field of telecommunication and the internet, for example, in which multi-channel speech coders are implemented using a single digital signal processing (DSP) device.
• DSP digital signal processing
• codecs audio coders/decoders
• DSP Digital Signal Processor
• a method for implementing a plurality of encoders and/or decoders (codecs) using a single digital signal processing (DSP) device wherein the function of each codec is performed by the DSP according to an instruction code program, the method comprising the steps of: providing an instruction code program stored in a first memory for controlling the DSP to function as a codec; providing a second memory including a plurality of memory segments; implementing a plurality of codecs using the DSP by running said instruction code program in the first memory a plurality of times in re-entrant instances, wherein each codec mstance is provided access to a respective separate memory segment in the second memory for storing data used in encoding/decoding a respective separate data stream.
• codecs encoders and/or decoders
• the present invention also provides a data coding and/or decoding system in which a plurality of encoders and/or decoders (codecs) are implemented using a single digital signal processing (DSP) device, comprising: a digital signal processor (DSP); a first memory coupled to the DSP and containing an instruction code program, the function of each codec being performed by the DSP, in use, according to the instruction code program; a second memory coupled to the DSP and partitioned to include a plurality of separate memory segments; wherein a plurality of codecs are implemented using the DSP by running the instruction code program in the first memory a plurality of times in re-entrant instances, and wherein each codec instance is provided access to a respective separate memory segment in the second memory for storing data used in encoding/decoding a respective separate data stream.
• DSP digital signal processing
• a tt ⁇ irti memory is also provided which is accessible by each of the codec instances for shared stbrage of temporary variables and data buffering in encoding/decoding said respective separate ⁇ data streams.
• Each codec instance preferably accesses the corresponding memory segment using indirect addressing based on at least one index register, the at least one index register being set for each codec instance to modify addressing of variables for that codec mstance to the corresponding memory segment.
• the plurality of memory segments are contiguous in the second memory, and the at least one index register is set for each codec instance according to an offset based on the difference in address from a first of said memory segments to the memory segment corresponding to that codec instance.
• each of the memory segments in said second memory is the same size.
• the first memory is provided with a plurality of instruction code programs for implementing different kinds of codecs, wherein different codec instances may be selected from the different kinds of codec.
• each of the memory segments m the second memory is the same size, and the size of the memory segments is selected according to the maximum memory required by any of the plurality of different kinds of codec.
• This methodology can be used to modify the existing DSP assembly code or to implement a new algorithm with a multiple instance feature.
• the multiple-instance implementation can be used to process multi-channel signals using one software module.
• Figure 1 is a block diagram of a simple audio encoding system employing a DSP
• Figure 2 is a block diagram of a data memory structure for a first embodiment of the present invention.
• Figure 3 is a block diagram of a data memory structure for a second embodiment of the invention employing a plurality of different codec types.
• the embodiments of the invention described hereinbelow are in the context of audio coders implemented by instruction codes in the form of software, firmware or micro-code operating on a general purpose digital signal processor chip.
• the described embodiments relate to implementation of speech codecs of the type which is the subject of ITU-T Recommendation G.729.
• the present invention is not necessarily limited to such an environment, and may further be used to implement coders for other forms of real-time data streams including other forms of voice and/or facsimile transmission or storage coding.
• a simple audio encoding system 10 based on a general purpose DSP is illustrated in block diagram form in Figure 1.
• the audio coding system 10 comprises a digital signal processor (DSP) 12 which is coupled to receive input data and produce coded output signals.
• the DSP 10 is coupled to a storage memory 14.
• the memory 14 provides data to the DSP 12 to enable coding of the received input data to take place.
• the memory 14 may contain various different forms of data, including read-only data which is permanently stored in the memory, and temporary data which is transiently stored during coding operations.
• the memory 14 may also contain stored instruction codes used by the DSP to perform the coding, which would ordinarily be permanently stored in read-only form.
• One of the considerations which must be dealt with in implementing multiple codecs on a single DSP by operating multiple instances of the DSP instruction codes which control the codec operation is the arrangement of storage memory so that each instance of the codec can have efficient memory usage and not interfere with other codec instances in use at the same time.
• this is achieved by arranging the data memory as illustrated in the block diagram of Figure 2.
• This exemplary embodiment relates to implementation of a 4-channel multiple instance vocoder on a single DSP.
• the data memory is partitioned into different parts, in this case comprising read-only memory (ROM), local RAM, and static RAM.
• the ROM is used to store all the read only data, which may include the program instruction codes and the like.
• the static RAM is used for storage of temporary variables and for data buffering.
• the static RAM is used for storage of all the global and historical variables required for the coding operations, for example data which will be used for processing the next frame of output As shown in the block diagram, in this case the static RAM is partitioned into separate areas for each DSP codec instance.
• the preferred form of the present invention involves partitioning the data memory based on their properties and using an index register or index modifier to modify the address of the static RAM segment data used for each codec instance.
• the program code memory can be arranged as usual. If, however, program memory is used for data accessing, this part of memory also needs to be partitioned in the same way as data memory such as X or Y. This methodology allows the easy management of the operating system or real-time kernel due to the facility of opening and closing the various instances.
• the partition of the data memory according to its accessing property is obtained, for example in the embodiment shown in Figure 2 involving ROM data, temporary local RAM, and static or global RAM segments.
• the data ROM and temporary local RAM are shared for every instance. Only the static RAM segments are used exclusively by corresponding codec instances.
• This static RAM segment is accessed using an index register by adding an offset value to address the static RAM segment for a particular instance.
• index registers In order to pass the addressing information to every channel vocoder, two index registers should be reserved for this reentrant purpose, say D 2 and IY2 if using a D950 DSP. By doing so, the address of all the static variables stored in the respective static RAM segments will be modified by these two index registers from the beginning.
• the multiple-instance 4-channel system can operate as follows, Repeat following codes
• offseti addressx 1 -addressx 1
• One example of the static RAM size is about 1560 words in X memory and 256 words in Y memory for a codec operating according to ITU-T G.729.
• the static RAM size would typically be the same for each instance of the G.729 vocoder.
• This is applicable for a new implementation or for converting existing DSP instruction coding to a re-entrant multiple instance implementation. Since this method does not require a change of the variable names in the DSP coding, it is efficient in both MIPS and porting effort if compared to using pointers.
• the memory may be arranged as illustrated in Figure 3, for which the multiple-instance accessing procedures are described below.
• the memory map for a 4-channel system is shown, in which the 4 active channels could be any possible combination of codecs operating according to ITU-T G729, G723.1 and FAX.
• the size of ROM segment comprises ROM data for all of the codec types.
• the size of the temporary local RAM segment is the maximum local RAM size used by any of the codecs. All of the different codecs share the local RAM segment.
• each of the static RAM segments are of a size to accommodate the frame processing storage requirements of any one of the possible codecs implementations. This enables different codecs to make use of different static RAM segments.
• One example is a 4-channel system with two different speech codecs, say G723.1 and G729.
• the program instruction codes are, in this example, stored separately in a program memory (not shown).
• the data memory is arranged as shown in Figure 3.
• Such a 4-channel system multiple instance system can operate as follows,
• the flag variable codec Jlag i is writeable by an operating system or system controller, so as to dictate which type of codec is used for each instance.

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• Engineering & Computer Science (AREA)
• Computational Linguistics (AREA)
• Signal Processing (AREA)
• Health & Medical Sciences (AREA)
• Audiology, Speech & Language Pathology (AREA)
• Human Computer Interaction (AREA)
• Physics & Mathematics (AREA)
• Acoustics & Sound (AREA)
• Multimedia (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)

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• 1999
  • 1999-09-29 DE DE69912860T patent/DE69912860T2/de not_active Expired - Fee Related
  • 1999-09-29 WO PCT/SG1999/000095 patent/WO2001023993A1/en active IP Right Grant
  • 1999-09-29 EP EP19990948014 patent/EP1222531B1/de not_active Expired - Lifetime

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