Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0041—Arrangements at the transmitter end
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0045—Arrangements at the receiver end
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
  • H04L1/0056—Systems characterized by the type of code used
  • H04L1/0071—Use of interleaving
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04H—BROADCAST COMMUNICATION
  • H04H2201/00—Aspects of broadcast communication
  • H04H2201/10—Aspects of broadcast communication characterised by the type of broadcast system
  • H04H2201/20—Aspects of broadcast communication characterised by the type of broadcast system digital audio broadcasting [DAB]

Definitions

• the invention is based on a device for receiving digital signals or a device for sending digital signals according to the preamble of the independent claims.
• the device according to the invention for receiving digital signals and the device according to the invention for sending digital signals with the features of the independent claims has the advantage that the memory of the receiver or the transmitter is optimally used by pre-sorting by means of a buffer. This makes it possible to use the available Reduce storage, which leads to cost advantages. It is also advantageous that the lower load that the data bus of the receiver or transmitter carries for memory access means that other components of the receiver or transmitter can access the data bus, so that the processing speed of the receiver or Transmitter is significantly increased. In addition, a lower number of accesses to the storage means a lower power consumption.
• a register in the receiver temporarily stores the symbols in the original order, so that the symbols then arrive in the original order at the channel decoder, so that the channel decoder can carry out the channel decoding.
• a sorting unit determines the time for how long the memory words containing the symbols with the same delay remain in the memory, since this achieves the same total delay for all symbols, so that the delays caused by the re-sorting are compensated become.
• a re-sorting unit determines how long the individual memory words are delayed, because this ensures that a cyclical delay of the individual symbols contained in the memory words is achieved, so that then in the receiver Referring to these delays these delays are offset again by further delays in the end all symbols have the same total delay, so that the original chronological order of the symbols is restored.
• a register stores the symbols in the changed order due to the delay, so that a processor then transmits the symbols to a modulator in the order intended for the transmission and the symbols are then sent. This ensures that, due to the re-sorting, so-called burst errors will have no fatal effect on the transmitted data stream.
• FIG. 1 shows a transmitting device for DAB signals, which is connected to a data bus
• FIG. 2 shows a receiver for DAB signals, which is connected to a data bus.
• a speech coder When speech, such as broadcasting, is transmitted, a speech coder is used which converts the speech signals into a uniform and efficient digital format.
• the encoded data, the symbols then contain a high amount of information and must be protected from errors.
• the speech coder generates important symbols one after the other. If an error occurs during the transmission of the speech signals that destroys several symbols in succession, error-correcting measures can no longer reconstruct the original symbols.
• the symbols in the transmitter rearranged so that the symbols that were consecutive in the data stream are now separated from each other in time. In English this sorting is called interleaving.
• this delay is assigned to the individual symbol positions ensures that successive symbols are separated from one another in time.
• the rule of how these delays are assigned is also known in the receiver, so that the receiver can restore the original order by assigning a further delay to each symbol, so that all symbols have experienced the same total delay, which means that the original temporal delay Order of symbols is restored.
• So-called channel coding is used to correct errors in the receiver.
• the channel coding adds redundancy to the symbols in the original order, which allows errors to be recognized and also corrected.
• the channel decoding in the receiver is carried out on the sorted order, that is to say after the original chronological order of the symbols has been restored.
• the exemplary embodiments should be based on the DAB (digital
• DAB is a multi-frequency carrier transmission method with high
• Frequency division multiplex used. That is a
• DAB frequency interleaving
• DAB also has time interleaving for the reasons mentioned above, that is to say symbols which were originally generated in succession are now separated from one another in time in order to minimize the effects of burst errors.
• the devices according to the invention are also suitable for other transmission methods which carry out a time re-sorting. Examples of such
• DVB Digital Video Broadcasting
• DRM Digital Radio Mondial
• FIG. 1 shows a transmission device 34 for transmitting DAB signals, which is connected to a data bus 33.
• a data source 25 e.g. a speech coder, a channel coder 22, a buffer 23, a register 31, a processor 32, a register 26, a modulator 24, a transmitter 21 and an antenna 20.
• the data generated by the data source 25 go to the channel encoder 22.
• the channel encoder 22 carries out the channel coding of the data.
• the channel-coded data go from the channel encoder 22 to a first data input of the buffer memory 23.
• Via a first address output of the processor 32 information arrives at an address input of the buffer memory 23, at which memory addresses the buffer memory 23 is to store the data coming from the channel encoder 22.
• the symbols are stored in such a way that the symbols that have the same delay are stored next to one another.
• the processor 32 via its first address output, which leads to the buffer 23, and its second address output, which leads to the register 31, causes the symbols, which are to experience the same delay, from a data output of the register 31 Buffer 23 are transferred to register 31 and are combined there into memory words.
• Register 31 is connected to data bus 33 via its data output. On the data bus 33 is still a
• the reordering unit 30 is a programmable component, for example a processor, which contains the rule according to which the symbols are delayed.
• the sorting unit 30 can alternatively be integrated into the processor 32, the processor 32 then having an address line to the memory 28 so that the individual memory words are delayed in accordance with the regulation which the unsorting unit has.
• the symbols combined into memory words are transmitted from register 31 via data bus 33 to memory 28, where the symbols are stored in a memory element of memory 28.
• the rearrangement unit 30 causes the symbols which are stored in memory words in the memory 28 to be delayed as long as is provided.
• the information as to how long the memory words are stored is known both to the reordering unit 30 and to the processor 32, so that the symbols which are to experience this delay are first combined into memory words and then this delay is experienced.
• the symbols in the memory words When the symbols in the memory words have experienced the intended delay in the memory 28, they are transferred from the memory 28 via the data bus 33 to the register 26, which is connected to the data bus 33 via a data input. Via an address input, the register 26 is controlled by the processor 32 via its third address output. In the register 26, the symbols that are present in a memory word are again divided into symbols, temporarily stored and transmitted to the modulator 24 via a data output of the register 26 to a data input of the modulator 24.
• the modulator 24 combines the symbols into DAB symbols and modulates the DAB symbols in accordance with the DAB standard and transfers the modulated DAB symbols to the
• Transmitter 21 which converts the modulated DAB symbols to the transmission frequency, amplifies them and radiates them via the antenna 20.
• FIG. 2 shows a receiving device which is connected to a data bus 8.
• the receiving device 15 has an antenna 1, a receiving device 2, a demodulator 3, an intermediate memory 4, a register 7, a register 9, a processor 10, a channel decoder 13, a signal processing 14 and a loudspeaker 16.
• the DAB signals received by means of the antenna 1 are amplified, filtered and converted in the receiving device 2 and then reach the demodulator 3, where the received DAB signals are demodulated.
• the demodulated DAB signals arrive from the demodulator 3 as symbols in the buffer memory 4, specifically via its data input.
• the processor 10 is connected via its first address output to an address input of the buffer memory 4.
• the processor 10 determines the memory addresses at which the buffer 4 stores the demodulated symbols.
• the processor 10 is connected to an address input of the register 7 via a second address output.
• the Processor 10 causes the symbols which have experienced the same delay in the DAB transmitter to be transferred together into register 7 and are combined there into memory words.
• the symbols combined into memory words reach the memory 11 with the same delay. There, the symbols combined into memory words are delayed until they have reached a total delay which is the same for all symbols. This time is determined by a sorting unit 6, which is located in the memory 11.
• the sorting unit 6 can alternatively be integrated with the processor 10, the processor 10 having an address line to the memory 11 so that the symbols in the memory 11 are delayed in accordance with the sorting unit 6.
• Register 9 the symbols summarized in memory words are again divided into individual symbols and temporarily stored, so that they arrive from the register 9 in the correct order to the channel decoder 13, the processor 10 via its third address output, which is connected to an address input of the register 9, controls this division into symbols.
• the channel decoder 13 carries out the channel decoding and transfers the channel decoded signals to the
• Signal processing 14 which prepares the signals for the loudspeaker 16.
• register 9 has an additional memory which is addressed by processor 10 so that the symbols are saved in their original chronological order.
• processor 10 is aware that the first, seventeenth, thirty-fourth and fiftieth symbols are contained in a memory word, since all of these symbols are the same
• Delay in the transmitter were resorted.
• the processor 10 knows which position these symbols occupy in the memory word. Using this knowledge, the processor 10 places the symbols in the memory of the register 9 at the first, seventeenth, thirty-fourth and fiftieth positions, respectively, so that when the register 9 memory is filled, the DAB symbols are in their original chronological order Sequence to the channel decoder 13 are sent.
• the buffer 4 can be used for this sorting instead of the additional memory of the register 9.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Physics & Mathematics (AREA)
• Probability & Statistics with Applications (AREA)
• Theoretical Computer Science (AREA)
• Circuits Of Receivers In General (AREA)
• Radio Relay Systems (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

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• 1999
  • 1999-07-31 DE DE19936272A patent/DE19936272C2/de not_active Expired - Lifetime
• 2000
  • 2000-07-20 JP JP2001513843A patent/JP2003521141A/ja active Pending
  • 2000-07-20 EP EP00954346A patent/EP1219055A2/de not_active Withdrawn
  • 2000-07-20 WO PCT/DE2000/002367 patent/WO2001010066A2/de active Application Filing
  • 2000-07-20 CA CA002380745A patent/CA2380745C/en not_active Expired - Lifetime

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