CA2380745C

CA2380745C - Device for receiving digital signals and device for transmitting digital signals

Info

Publication number: CA2380745C
Application number: CA002380745A
Authority: CA
Inventors: Gerald Spreitz
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1999-07-31
Filing date: 2000-07-20
Publication date: 2007-12-04
Anticipated expiration: 2020-07-20
Also published as: CA2380745A1; DE19936272C2; DE19936272A1; EP1219055A2; WO2001010066A2; JP2003521141A; WO2001010066A3

Abstract

The invention relates to a device for receiving digital signals and to a device for transmitting digital signals, which are used for interleaving the transmission of symbols contained in the digital signals and for compiling t he symbols into memory words which are subjected to a cyclic delay. During reception, the received symbols having the same delay are compiled into memo ry words and subjected to an additional delay so that all symbols have the same overall delay. The devices include a buffer memory which is used for presorting and a register to compile the symbols into memory words and to separate the memory words back into symbols. The devices for receiving and transmitting digital signals are connected to a data bus, the memory also being connected to said data bus. The invention provides the advantage that the load exerted on the data bus is low so that said data bus can be made available to other components.

Description

Device for Receiving Digital Signals and Device for Transmitting Digital Signals Prior art The present invention proceeds from a device for receiving digital signals and a device for transmitting digital signals of the class described in the independent patent claims.

It is already known from WO 96/20536 that for digital audio broadcasting (DAB), an interleaving process is used at the transmitting end, and a sorting process is used at the receiving end in order to permit correction of so-called burst errors in the receiver. During interleaving or sorting, amemory of a transmitter or receiver, which has memory elements, is used; generally speaking, a number of symbols will not fit in a memory element, i.e., the number of these DAB symbols is either too great or too small for a memory element because of their length.

Advantages of the present invention In contrast to this, the device according to the present invention, used for receiving digital signals, or the device according to the present invention, used for transmitting digital signals , with the features set out in the independent claims, entails the advantage that the memory of the receiver or of the transmitter is used optimally by presorting, using an intermediate memory. This makes it possible to reduce the size of the available memory, which results in cost advantages. Furthermore, it is an advantage that, because of the smaller load that has to be borne by the data bus of the receiver or the transmitter for memory access, other receiver or transmitter components can access the data bus, so that the processing speed of the receiver or transmitter is greatly increased. In addition, reducing the number of times the memory is accessed means lower power consumption.

The measures set out in the dependent claims permit advantageous developments and improvements to the device described in the independent claims.

It is particularly advantageous that a register in the receiver holds the symbols in intermediate memory In their original sequence, so that the symbols then move to the channel decoder in the original sequence and the channel decoder can perform channel decoding.

It is also an advantage that a sorting unit determines the time for which the memory words that contain the symbols with the same delay remain in memory; because of this, an equal overall delay is arrived at for all the symbols, so that the delays caused by Interleaving can be evened out.

It is an advantage for the transmitter that an interleaving unit determines how long the individual memory words are delayed, for this ensures that a cyclical delay Is arrived at for the individuai symbols that are contained in the memory words, so that in the receiver these delays can then be evened out again by additional delays, with reference to these delays, so that at the end, all the symbols have the same overall delay, and so that the original chronological sequence of the symbols Is reestablished.

Within the transmitter, it is also an advantage that a register holds the symbols in intermediate memory in the modified sequence brought about by the delay, so that a processor passes the symbols to a modulator in the sequence intended for transmission, and the symbols are then transmitted. This ensures that because of the interleaving, so-called burst errors can have no fatal effect on the data flow that is transmitted.

In accordance with an aspect of the present invention, there is provided a device for receiving digital signals, the digital signals having symbols, the signals that are received being in a modified sequence because of a cyclical delay in a transmitter, the device comprising: a demodulator for demodulating the digital signals that are received, a channel decoder for channel decoding the symbols, an intermediate memory for storing the symbols coming from the demodulator, a first register for receiving the symbols from the intermediate memory, and for combining symbols having the same delay to form memory words, wherein a main receiver memory is connected to a data bus and the device is connected to the data bus, wherein the main receiver memory is adapted to receive and store the memory words coming from the first register via the data bus, the device further comprising: a second register for receiving the memory words from the main receiver memory, the symbols of memory words being received having the same overall delay that is identical for all of the symbols; the second register also being adapted for breaking down the memory words into symbols, and a processor for transferring the symbols to the channel decoder in a sequence the same as the sequence originally received by the transmitter.

In accordance with another aspect of the present invention, there is provided a device for transmitting digital signals, the digital signals having symbols, the device comprising: a channel coder for channel coding the symbols, an intermediate memory for holding symbols coming from the channel coder; a first register for receiving the symbols from the intermediate memory, the symbols having been subjected to an equal delay, and for combining the symbols to form memory words, wherein a main transmitter memory is connected to a data bus and the device is 2a connected to the data bus, wherein the main transmitter memory is adapted to receive and store the memory words coming from the first register via the data bus, the device further comprising: a second register for receiving the memory words from the data bus, wherein for the memory words being received, the symbols in different memory words having a different delay, a modulator for modulating the symbols, and a processor for transferring the symbols to the modulator in a modified sequence.

Drawings 2b Embodiments of the present invention are shown in the drawings and described in greater detail below. These drawings show the following:

Figure 1: A transmitting device for DAB signals, which is connected to a data bus;
Figure 2: A receiver for DAB signals, which is connected to a data bus.
Description of the embodiments When speech is transmitted, e.g., during a broadcast, a speech coder is used to convert the speech signals into a standardized and efficient digital format. The coded data, the symbols, then have a large information content and have to be protected against errors.
Typically, the speech coder generates important signals one after the other.
If an error, which destroys several symbols one after the other, occurs when speech signals are being transmitted, error correcting measures cannot reconstruct the original symbols. For this reason, the symbols are interleaved in the transmitter so that the symbols that were one behind the other in the data stream are now separated from each other by time.
In English, this process is referred to as interleaving.

An error that destroys several signals one after the other during transmission is referred to in English as a burst. The interleaving of the symbols in the transmitter takes place by means of a cyclical delay. The effect of this cyclical delay is such that the symbols in the original sequence are first divided up into groups of, for example, sixteen symbols, a specific delay being associated to a specific position in each of these sixteen symbols.

The rule that governs how these delays are assigned to the individual symbol positions ensures that symbols that are positioned one behind the other are separated from each other by time. The rule that governs how these delays are assigned is known in the receiver, so that the receiver can reestablish the original sequence, because an additional delay is assigned to each symbol, so that all the symbols have experienced the identical overall delay, whereby the original chronological sequence of the symbols is reestablished.
A so-called channel coding is used in order to permit correction of an error in the receiver.
The channel coding adds redundancy to the symbols in the original sequence and this makes it possible to identify and correct errors. In general, a distinction is made between two methods for channel coding for error-correcting codes; these are, first, the so-called block codes, additional bits being added to a block of symbols; these are the so-called parity bits that make it possible to identify and correct errors. There are also the so-called convolutional codes, the original symbol sequence being mapped into a new symbol sequence by a mapping instruction that adds additional bits.

Since the channel coding is performed on the original chronological sequence of the symbols, the channel decoding in the receiver is performed on the sorted sequence, which is to say, after the original chronological sequence of the symbols has been reestablished.

The exemplary embodiments will be shown as based on DAB. DAB is a broadband multi-frequency carrier transmission method. The modulation method of orthogonal frequency multiplex is used in this digital terrestrial sound radio system. This is a modulation method in which the signal that is to be transmitted is divided amongst a number of sub-carriers, when the signals that are divided amongst these sub-carriers do not interfere with each other. This method is referred to as orthogonal.

So-called frequency interleaving is achieved by this division amongst several frequencies.
This avoids a powerful attenuation at one frequency from weakening the signal very strongly. If it is divided amongst several frequencies, this attenuation causes no fatal disturbance of the signal.
In addition to this frequency interleaving, for the reasons set out above, DAB also has time interleaving, in that symbols that were originally generated one after the other over time are now separated from each other by time in order to minimize the effects of burst errors.

The devices according to the present invention are also suitable for other transmission methods that involve chronological interleaving. Examples of such transmission methods are DVB (digital video broadcasting) and DRM
(digital radio mondial). Like DAB, these two methods use frequency interleaving; essential differences are in the transmission frequencies and band widths, and in the frame structure.

Figure 1 shows a transmitter device 34 that is used to transmit DAB signals; this device is connected to a data bus 33. The transmitter device 33 has a data source 25, e.g., a speech coder, a channel coder 22, an intermediate memory 23, a register 31 (which may be referred to as a first register for the transmitter), a processor 32, a register 26, a modulator 24, a transmitting device 21, and an antenna 20.

The data generated by the data source 25 pass to the channel coder 22. The channel coder 22 carries out channel coding of the data. The channel coded data pass from the channel coder 22 to a first data input of the intermediate memory 23. From a first address output of the processor 32, information passes to an address input of the intermediate memory 23 at which memory addresses the intermediate memory 23 is to store the data coming from the channel coder 22.

The symbols are so stored that the symbols that have the same delay are stored next to each other. The processor 32 ensures, by way of its first address output, which leads to the intermediate memory 23, and its second address output, which leads to the register 31, that the symbols, which are meant to experience the same delay, are transmitted by way of a data output of the register 31 from the intermediate memory 23 to the register 31, where they are then combined to form memory words.

The register 31 is connected to the data bus 33 through its data output. A memory 28 (which may also be referred to as a main transmitter memory) with an interleaving unit 30 is also connected to the data bus. The interleaving unit 30 is a programmable component, for example, a processor, which contains the rule according to which the symbols are delayed. Alternatively, the interleaving unit 30 can be integrated into the processor 32, the processor 32 then having an address line to the memory 28, in order that the individual memory words are delayed in accordance with the instruction held in the interleaving unit.

The symbols that have been combined to form memory words are passed from the register 31 on the data bus 33 to the memory 28, where the symbols are stored in a memory element of the memory 28.

The interleaving unit 30 ensures that the symbols that have been stored in memory words in the memory 28 are delayed for as long as has been prescribed. The information as to how long the memory words are to be stored is known to both the interleaving unit 30 and the processor 32, so that the symbols that are to be so delayed are first combined to form memory words and then experience this delay.

When the symbols in the memory words have undergone their intended delay in the memory 28, they are moved on the data bus 33 from the memory 28 to the register 26 (which may also be referred to as a second register for the transmitter), which is connected to the data bus 33 through a data input.

The register 26 is controlled, through an address input, from the processor 32, through its third address output. Within the register 26, the symbols that are in a memory word are once again separated into symbols, placed in intermediate memory (which may also be referred to as a further intermediate memory), and then passed to the modulator 24 through a data output of the register 26, to a data input of the modulator 24.

The modulator 24 combines the symbols to form DAB
symbols and modulates the DAB symbols according to the DAB
Standard; it then passes the modulated DAB symbols to the transmitting device 21 that converts the modulated DAB
symbols to the transmitting frequency, amplifies them, and broadcasts them by way of the antenna 20.

Figure 2 shows a receiving device that is connected to a data bus 8. The receiving device 15 has an antenna 1, a receiving device 2, a demodulator 3, an intermediate memory 4, a register 7, a register 9, a processor 10, a channel decoder 13, a signal processing unit 14, and a loudspeaker 6.

The DAB signals that are received by means of the antenna 1 are amplified in the receiving device 2, filtered, and converted, and then passed to the demodulator 3, where the received DAB signals are demodulated. The demodulated DAB signals are passed as symbols from the demodulator 3 to the intermediate memory 4 by way of its data input. The processor 10 is connected through its first address output to an address input of the intermediate memory 4.

The processor 10 determines the memory addresses at which the intermediate memory 4 stores the demodulated symbols. The processor 10 is connected to an address input of the register 7 through a second address output. The processor 10 ensures that the symbols that have experienced the same delay in the DAB transmitter are passed to the register 7 (which may be referred to as a first register for the receiving device) together, where they are combined to form memory words.

From the register 7, the symbols that have been combined into memory words with the same delay are passed on the data bus 8 to the memory 11 (which may also be referred to as a main receiver memory), where the symbols that have been combined to form memory words are delayed until they have an overall delay that is identical for all the symbols.
This time is determined by a sorting unit 6 that is located in the memory 11. As an alternative, the sorting unit 6 can be integrated with the processor 10, the processor 10 having an address line to the memory 11, so that the symbols in the memory 11 are delayed in accordance with the sorting unit 15.

If the symbols in a memory word have undergone the overall delay, they are passed on the data bus 8 to the register 9 (which may be referred to as a second register for the receiving device) through a data input. In the register 9, the symbols that are combined to form memory words are separated into individual symbols and placed in intermediate memory (which may also be referred to as a further intermediate memory), so that they move from the register 9 to the channel decoder 13 in the correct sequence, the processor 10 controlling this separation into symbols by way of its third address output, which is connected to an address input of the register 9.

The channel decoder 13 performs the channel decoding and passes the channel decoded signals to the signal processing unit 14, which prepares the signals for the loudspeaker 16.

The register 9 has an additional memory for intermediate storage, and this is addressed from the processor 10, so that the symbols are stored in their original chronological sequence. The processor 10 knows, for example, that the first, seventeenth, thirty-fourth, and the fiftieth symbols are contained=in a memory word, since all these symbols were interleaved in the transmitter with the same delay. Furthermore, the processor 10 also 8a knows the position of these symbols in the memory word. Using this information, the processor 10 orders the symbols in the memory of register 9 in the first, seventeenth, thirty-fourth, and the fiftieth positions, so that when the memory of the register 9 is filled, the DAB symbols are sent to the channel decoder 13 in their original chronological sequence.

Alternatively, instead of the additional memory, the intermediate memory can be used for this sorting in place of the additional memory of the register 9.

Claims

CLAIMS:

1. A device for receiving digital signals, the digital signals having symbols, the signals that are received being in a modified sequence because of a cyclical delay in a transmitter, the device comprising:

- a demodulator for demodulating the digital signals that are received, - a channel decoder for channel decoding the symbols, - an intermediate memory for storing the symbols coming from the demodulator, - a first register for receiving the symbols from the intermediate memory, and for combining symbols having the same delay to form memory words, wherein a main receiver memory is connected to a data bus and the device is connected to the data bus, wherein the main receiver memory is adapted to receive and store the memory words coming from the first register via the data bus, the device further comprising:

- a second register for receiving the memory words from the main receiver memory, the symbols of memory words being received having the same overall delay that is identical for all of the symbols; the second register also being adapted for breaking down the memory words into symbols, and - a processor for transferring the symbols to the channel decoder in a sequence the same as the sequence originally received by the transmitter.

2. The device as defined in Claim 1, wherein the second register stores the symbols in a further intermediate memory in the original sequence until the second processor transfers the symbols to the channel decoder.

3. The device as defined in Claim 2, wherein a sorting unit determines the length of time the memory words remain in the main receiver memory, until the overall delay is identical for all the symbols.

4. A device for transmitting digital signals, the digital signals having symbols, the device comprising:

- a channel coder for channel coding the symbols, - an intermediate memory for holding symbols coming from the channel coder;

- a first register - for receiving the symbols from the intermediate memory, the symbols having been subjected to an equal delay, and - for combining the symbols to form memory words, wherein a main transmitter memory is connected to a data bus and the device is connected to the data bus, wherein the main transmitter memory is adapted to receive and store the memory words coming from the first register via the data bus, the device further comprising:

- a second register for receiving the memory words from the data bus, wherein for the memory words being received, the symbols in different memory words having a different delay, - a modulator for modulating the symbols, and - a processor for transferring the symbols to the modulator in a modified sequence.

5. The device as defined in Claim 4, wherein an interleaving unit determines how long the main transmitter memory delays the individual memory words.

6. The device as defined in Claim 5, wherein the second register holds the symbols in the modified sequence in a further intermediate memory until the processor transfers the symbols to the modulator.