EP1211070B2 - Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufenden Prozessen - Google Patents

Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufenden Prozessen Download PDF

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Publication number
EP1211070B2
EP1211070B2 EP01126527A EP01126527A EP1211070B2 EP 1211070 B2 EP1211070 B2 EP 1211070B2 EP 01126527 A EP01126527 A EP 01126527A EP 01126527 A EP01126527 A EP 01126527A EP 1211070 B2 EP1211070 B2 EP 1211070B2
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EP
European Patent Office
Prior art keywords
system clock
time
clock
values
motor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP01126527A
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German (de)
English (en)
French (fr)
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EP1211070B1 (de
EP1211070A2 (de
EP1211070A3 (de
Inventor
Kai Albrecht
Ulrich Grimm
Thomas Husterer
Reinhard Janzer
Helmut Meyer
Georg Roessler
Andreas Wagner
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Heidelberger Druckmaschinen AG
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Heidelberger Druckmaschinen AG
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Application filed by Heidelberger Druckmaschinen AG filed Critical Heidelberger Druckmaschinen AG
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41F—PRINTING MACHINES OR PRESSES
    • B41F33/00—Indicating, counting, warning, control or safety devices

Definitions

  • the invention relates to an apparatus and a method for the synchronization of processes that are performed by separate processors and are tuned to the system clock of a central unit.
  • Application finds this device or the process in completed processes on various components of a paper-processing machine
  • the EP 0 747 216 B1 Prior to connecting various units that are supplied with Winkelscellungssignale by two bus systems. Each unit receives by means of a bus system constantly the current angle value and by means of the other bus system information to be made to a switching operation. The angle setpoint at which the switching process is to be triggered is stored in a memory of the respective unit.
  • a plurality of slave units are connected to a master unit, which exchange data via a system bus.
  • the system bus continues to transmit a system clock to the slave units via the master unit.
  • This system clock serves the slave units as a reference signal.
  • the slave units synchronize by means of a PLL circuit respectively to the system clock and thus ensure a synchronous clock generation in the slave units to the master unit.
  • the PLL circuits in the slave units switch to stand-alone mode, ensuring clock generation for each slave unit until the system clock returns.
  • the device according to the invention and the corresponding method is based on the object to bring about a synchronization of many processes with simple means.
  • the device assumes that a central unit takes over the coordination of different further units located in the periphery.
  • the task of the central unit is to synchronize all processes running on the periphery.
  • the frequency of the system clock is chosen to be relatively low. The clock signal thus moves in a frequency range, whereby a distribution of the clock signal over longer distances is possible. Furthermore, it is possible to suppress the incoming system clock by suitable filter measures.
  • the device according to the invention proposes to multiply the incoming system clock in the peripheral unit according to the requirements.
  • This so-called module clock then generated has the desired resolution, or is advantageously adjustable to the desired resolution.
  • the clock always prevails at the peripheral unit, which is required for the respective process.
  • the device according to the invention provides a clock integrated in the peripheral units, which is synchronized by the system clock. Between the respective synchronization intervals by the system clock, the clock is free.
  • the module clock frequency stable at the peripheral unit proposes a variant of the invention to stabilize these by means of quartz. According to a calculated drift, which results from the quality of the stabilizing quartz, the time interval of the synchronization interval can be determined.
  • the generation of a local module clock has the advantage that in case of failure of the system clock generated in the central unit there is no risk that processes run uncontrolled and lead to accidents, since a vote of independently running processes is no longer possible.
  • the procedure is such that a failure of the system clock is detected by the processor in the peripheral unit, which then controlled down the process based on the local module clock to a stop.
  • the required time between failure of the system clock and the controlled shutdown of the process is so short that the drifting of the module clock from the system clock mentioned above does not lead to any significant problems.
  • all processes that take place at the various peripheral units and are synchronized with one another by the system clock are brought to a controlled halt by the locally generated module clock.
  • a method according to the invention also proposes that a so-called synchronization interval takes place at regular intervals, for example after every hundredth system clock.
  • a time announcement 37 is made to the peripheral unit, which adjusts the peripheral unit to the absolute time.
  • all peripheral units receive a time adjustment for absolute time, a so-called time stamp.
  • each peripheral unit can tune its processes to the running machine, that is, running processes can be kept synchronous by corrective measures, or starting processes can be started at the right time or angle of the machine.
  • the peripheral unit With the simultaneous notification of the value of the time of acquisition, the peripheral unit is able to extrapolate the transmitted value at any time between two transmitted values. This means that even the time delay in the transmission of the values results in the problem that when the values are received, they are no longer up to date.
  • the advantage of the device or method according to the invention is that it is almost irrelevant how long the transmission of the values takes, since the current value can always be determined.
  • the start time of a starting process between two transmitted values can be calculated exactly by the above-mentioned extrapolation.
  • the event to be performed can be triggered without the need for a time-synchronous instruction of the central unit.
  • Such an angle-dependent event can be triggered by each peripheral unit without the need for direct cabling with a central incremental encoder. This saves on the one hand cabling and on the other hand ensures a lower susceptibility to interference.
  • the method according to the invention proposes the following variant:
  • the auxiliary drive is equipped with its own setpoint generator. This setpoint generator calculates the setpoints for the auxiliary drive.
  • sampling cycles are defined in which the actual values of the auxiliary drive are read in and new nominal values are specified using various control algorithms.
  • the actual values of the main drive are sent at discrete times (for reasons of bus load), but their frequency is less than the sampling cycles of the auxiliary drive.
  • An additional application of the device or the method according to the invention is that different synchronously running motors are not controlled by the actual values of a main drive, but on a central command specification.
  • Running drives in a speed ratio e.g. Half-speed, third-speed or double-speed, a setpoint generator in the peripheral unit ensures the generation of correspondingly adapted setpoint values.
  • All motor controllers now use the same algorithm and always read the actual values of the motors at the exact same time. This time corresponds to the system clock. This ensures that all motors are controlled to a virtual electronic wave.
  • Fig. 1 shows a cross-linking of two processors 1a, b.
  • the processors 1a, b, together with an interface 2a, b and connected input / output cards 3a, b and motor control cards 4a, b respectively represent a unit 5a, b.
  • the respective local components, such as processor 1a and interface 2a, and 1b and 2b are interconnected by means of VME bus system 6.
  • On the interface 2a is still a system clock 7.
  • This system clock 7 is forwarded by means of free line 9, for example, a CAN bus system 10 to the located in the periphery input / output card 3a and the motor control board 4a.
  • the number of input / output cards 3a, or the number of motor control cards 4a is irrelevant.
  • the system clock is passed to the interface 2b of the unit 5b.
  • a system clock processing 8 for example, contains a filter or an amplifier.
  • the system clock 7 is also supplied to the unit 5b associated input / output card 3b and the motor control card 4b via line 9.
  • the input / output card 3b or motor control card 4b also referred to as subscribers, can be extended by subscribers 16a, b whose use is not defined.
  • the number of interfaces 2a, b per unit 5a, b may be greater than shown in this embodiment.
  • the system clock 7 is furthermore made available via the local VME bus system 6a, b to all local components 1a, b or 2a, b belonging to the unit 5a, b. Via a line 9d further units 5n can be connected to the system clock 7.
  • the multiplication unit 11 has the task to multiply the resolution according to the required conditions. This can, for example, based on an embodiment according to Fig.2 respectively.
  • Fig. 2 shows a block diagram of a multiplication unit 11 as it is present on the various input / output cards 3a, b and engine control cards 4a, b.
  • a frequency generator 12 a clock having a frequency of, for example, 1 MHz is generated. For frequency stabilization this is associated with a quartz 13.
  • a counter 14 is connected to the frequency generator 12. With the system clock 7, the counter 14 is started or reset. If the system clock 7 has, for example, a clock frequency of 1 kHz, the counter counts within a period of the system clock 7 from 0-999 and repeats this process constantly. More specifically, this means that the pulses of the frequency generator 12 are turned on in case they are synchronous with the system clock 7, so to speak.
  • the synchronized module clock 15 of the input / output card, 3ab or motor control card 4ab is provided at one output.
  • Fig. 3a to 3e are several diagrams showing the system clock 7 ( Fig. 3a ) the ramp function of the counter 14 ( Fig. 3b ) and a fine resolution of the module clock 15 ( Fig. 3c, d, e ) demonstrate.
  • the diagram after Fig. 3a shows the system clock 7, wherein in the diagram according to Fig. 3b the ramp function of the counter 14 is always started with the falling edge 30 of the system clock 7.
  • the counter 14 counts from 0-999 within a period each between the falling edges 30 of the system clock 7.
  • the ramp functions 33, 34, 35 show different behavior which is indicated by the diagrams according to FIG Fig. 3c, d, e can be explained. So is in Fig.
  • the diagram after Fig. 3d shows the case that the module clock 15 compared to the system clock 7 is slightly faster than the thousandth of the system clock 7. Because the counter 14 no longer increases its count at 999, the last count (999) remains until a reset of the Counter takes place by the falling edge 30 of the system clock 7. Likewise, there is thus again a correction or synchronization.
  • the diagram after Fig. 3e represents yet another variant. After reaching the count 999, the counter is not reset by the system clock 7, because this has failed, for example, but there is a reset of the counter due to exceeding a predetermined time window 36. This time window 36 is at a defined Counting (eg 990) starts and ends, for example 10 microseconds after reaching the count 999.
  • a forced resetting of the module clock 15 which simultaneously results in that the clocked by the module clock 15 processes from the time of the first failure of the system clock, controlled be brought to a standstill.
  • the effect of the time window 36 is also equal to a filtering.
  • a connection of the time window 36 with the system clock 7 can be achieved by means of an AND gate, as a result of which the system clock 7 is switched through only within the time window 36 is possible. Spurious signals that are on the line of the system clock 7 are ignored outside of the time window 36.
  • Figure 4 shows a timing diagram over the course of a section of the system clock 7.
  • the clock frequency of the system clock 7 is for example at 1 kHz and has an unequal duty cycle.
  • the rising edge 31 already occurs after, for example, 50 .mu.s.
  • the user 2b, 3ab, 4ab can start a measuring cycle 32 after the falling edge 30, for example 550 .mu.s after the falling edge 30, which as a rule is in the high state of System clocks 7 is located.
  • the subscriber 2b, 3ab, 4ab focuses his attention on recognizing when the next system clock 7 comes.
  • time announcement 37 Every 100 ms, that is to say after every one hundredth system clock 7, a so-called time announcement 37 occurs.
  • This time announcement 37 is recognized by the fact that 550 ⁇ s after the falling edge 30 no high state of the system clock prevails.
  • the subscriber 2b, 3ab, 4ab thus recognizes that this is the announcement of the time announcement 37.
  • This time announcement 37 receives each participant 2b, 3ab, 4ab an exact indication of the time that has elapsed since the machine was turned on (absolute time).
  • the advantage is that subscribers who are subsequently switched on, that is to say during which the machine is already running, are always informed of the absolute time of the machine.
  • Each subscriber 2b, 3ab, 4ab can then perform an event related to the absolute time without having to receive the command thereto from the central unit 5a.
  • Fig. 5 shows a block diagram for the control of two motors.
  • Fig. 5 is opposite Fig.1 to the effect that a motor 20a, b and an incremental encoder 21a, b have been added to the motor control board 4a, b.
  • the interface 2a is an input device 22 for inputs that can be done by the operator of the machine attached.
  • the motor 20a is the main motor responsible for the rotational movement of the cylinders of a printing press. This motor 20a is controlled as follows:
  • the operator of the machine enters a value for the speed.
  • This value is supplied via the CAN bus system 10 a of the motor control board 4 a, which determines therefrom the control values (current setpoint values) for the motor 20 a and adjusts.
  • the motor 20a is provided with an incremental encoder 21a which is either directly seated on the motor shaft of the motor 20a or at a suitable position of the gear train driven by the motor 20a.
  • the pulses of the incremental encoder 21a are read in by the motor drive board 4a. The reading-in process always takes place at the time of a system clock 7. From these pulses, the speed, the acceleration and the angular position of the motor 20a are calculated in the motor control board 4a.
  • these values are used to control the motor 20a, on the other hand, these values are always communicated together with the detection time to all other subscribers 3a, b4b.
  • the included acquisition time makes it irrelevant whether the data is transmitted quickly, whether the data is transmitted at a certain time or whether all participants receive the data at the same time.
  • motor control card 4b which has been given the task, for example, by the processor 2b of operating the motor 20b in synchronism with the motor 20a.
  • a task is implemented in the engine control card 4b by a so-called command interpreter.
  • the motor control card 4b now receives the values speed, acceleration and angular position of the motor 20a at regular intervals. From these values, the setpoint values for the own motor 20b are calculated.
  • the time interval between two transmissions of the values speed, acceleration and angular position of the motor 20a with the corresponding indication of the detection time is possibly too great for a synchronous attitude of two motors 20a, b, so that interpolation takes place in the meantime.
  • This interpolation is performed on the motor control board 4b and the setpoint values for the motor 20b are calculated on the basis of these interpolated values.
  • a multiplication unit 11 for generating a module clock 15 is located on the motor control card 4b Fig.2 ,
  • the resolution of the module clock 15 is set so that the operations executing on the motor drive board 4b (interpolation of the course of the motor 20a, input of the pulses of the incremental encoder 21b, calculation of the actual values of the motor 20b from the pulses of the incremental encoder 21b, calculation of new set values for the Motor 21b, etc.) are all considered time optimized.
EP01126527A 2000-11-29 2001-11-14 Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufenden Prozessen Expired - Lifetime EP1211070B2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10059270 2000-11-29
DE10059270A DE10059270B4 (de) 2000-11-29 2000-11-29 Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufende Prozesse

Publications (4)

Publication Number Publication Date
EP1211070A2 EP1211070A2 (de) 2002-06-05
EP1211070A3 EP1211070A3 (de) 2003-08-27
EP1211070B1 EP1211070B1 (de) 2010-06-30
EP1211070B2 true EP1211070B2 (de) 2013-01-16

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EP01126527A Expired - Lifetime EP1211070B2 (de) 2000-11-29 2001-11-14 Vorrichtung und Verfahren zur Synchronisation von an mehreren Einheiten ablaufenden Prozessen

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Country Link
US (1) US6948085B2 (zh)
EP (1) EP1211070B2 (zh)
JP (1) JP4078065B2 (zh)
CN (1) CN1272173C (zh)
AT (1) ATE472407T1 (zh)
CZ (1) CZ303068B6 (zh)
DE (2) DE10059270B4 (zh)
HK (1) HK1047726B (zh)

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DE10248690B4 (de) 2001-11-15 2019-10-31 Heidelberger Druckmaschinen Ag Verfahren zur Synchronisation mehrerer elektrischer Antriebseinheiten
DE10312379B4 (de) 2002-04-04 2018-06-28 Heidelberger Druckmaschinen Ag Verfahren und Vorrichtung zur Synchronisation von Antriebskombinationen
DE10246732A1 (de) 2002-10-07 2004-04-15 OCé PRINTING SYSTEMS GMBH Verfahren und Vorrichtung zum Synchronisieren von Aktionen, die über ein lokales, mehrere Mikrokontroller aufweisendes Datennetz gesteuert werden, sowie Verfahren und Vorrichtung zum Senden von Nachrichten über ein solches Datennetzwerk
US7091827B2 (en) * 2003-02-03 2006-08-15 Ingrid, Inc. Communications control in a security system
DE102005039450B4 (de) * 2005-08-18 2008-04-30 Dspace Digital Signal Processing And Control Engineering Gmbh Verfahren und Netzwerk zur synchronen Bearbeitung und Bereitstellung von Daten
US7596711B2 (en) 2005-08-19 2009-09-29 Dspace Digital Signal Processing And Control Engineering Gmbh Method and network for synchronistic processing and providing data using an extrapolation data set including at least one update time point
JP2007219642A (ja) * 2006-02-14 2007-08-30 Fanuc Ltd 制御システム
US8325767B2 (en) 2006-09-29 2012-12-04 Agilent Technologies, Inc. Enhancement of IEEE 1588 synchronization using out-of-band communication path
WO2008075404A1 (ja) * 2006-12-19 2008-06-26 Systemv Management Inc., 半導体製造システム
DE102007031709B4 (de) * 2007-07-06 2009-04-30 Schneider Electric Motion Deutschland Gmbh & Co. Kg Elektrischer Antrieb
US8516293B2 (en) * 2009-11-05 2013-08-20 Novell, Inc. System and method for implementing a cloud computer
DE102008039793A1 (de) * 2008-08-26 2010-03-04 Siemens Aktiengesellschaft Verfahren zur Taktsynchronisierung in einem Kommunikationsnetz und Kommunikationsnetz
US9766648B2 (en) * 2013-07-16 2017-09-19 Ford Global Technologies, Llc Controller system coordinated using a timing signal and method of controller coordination using a timing signal
JP6236996B2 (ja) 2013-08-28 2017-11-29 富士通株式会社 情報処理装置および情報処理装置の制御方法

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Also Published As

Publication number Publication date
DE50115536D1 (de) 2010-08-12
EP1211070B1 (de) 2010-06-30
CN1272173C (zh) 2006-08-30
US6948085B2 (en) 2005-09-20
DE10059270A1 (de) 2002-06-06
CZ20013655A3 (cs) 2002-07-17
CZ303068B6 (cs) 2012-03-21
JP2002258980A (ja) 2002-09-13
ATE472407T1 (de) 2010-07-15
JP4078065B2 (ja) 2008-04-23
US20020111696A1 (en) 2002-08-15
EP1211070A2 (de) 2002-06-05
HK1047726A1 (en) 2003-03-07
CN1356208A (zh) 2002-07-03
EP1211070A3 (de) 2003-08-27
DE10059270B4 (de) 2012-08-02
HK1047726B (zh) 2007-02-23

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