Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/20—Resistors
  • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01C—RESISTORS
  • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
  • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
  • H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01C—RESISTORS
  • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
  • H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
  • H01C17/075—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques
  • H01C17/08—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin film techniques by vapour deposition
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01C—RESISTORS
  • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
  • H01C7/006—Thin film resistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/0802—Resistors only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
  • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention is directed, in general, to integrated circuits and, more specifically, to buried thin film resistors, and a method of manufacture therefor.
• a thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second dielectric layer located over the resistive layer and the first and second contact pads.
• the thin film resistor further includes a first interconnect that contacts the first contact pad and a second interconnect that contacts the second contact pad.
• the method in an illustrative embodiment includes: (1) forming a resistive layer on a first dielectric layer, (2) forming first and second contact pads on the resistive layer, and (3) forming a second dielectric layer over the resistive layer and the first and second contact pads.
• FIGURE 1 illustrates one embodiment of a completed thin film resistor device as covered by the present invention
• FIGURE 2 illustrates the formation of an interconnect metallization structure layer over a substrate
• FIGURE 3 illustrates the formation of interconnect metallization structures
• FIGURE 4 illustrates the formation of a conformal dielectric layer over the interconnect metallization structures and substrate
• FIGURE 5 illustrates the formation of a thin layer of dielectric material over the conformal dielectric layer
• FIGURE 6 illustrates the planarization of the thin layer of dielectric layer and the conformal dielectric layer
• FIGURE 7 illustrates the partially completed thin film resistor device illustrated in FIGURE 6, after the formation of a first dielectric layer
• FIGURE 8 illustrates the formation of a resistive material layer
• FIGURE 9 illustrates the partially completed thin film resistor device illustrated in FIGURE 8, after formation of a contact pad layer
• FIGURE 10 illustrates the formation of a first contact pad and a second contact pad on the resistive material layer
• FIGURE 11 illustrates the etching of the resistive material layer
• FIGURE 12 illustrates a conformal deposition of a second dielectric layer over the first contact pad, the second contact pad, the resistive layer and the first dielectric layer
• FIGURE 13 illustrates the formation of contact pad vias or windows, and interconnect metallization structure vias or windows;
• FIGURE 14 illustrates the formation of a blanket metal layer within the contact pad vias and interconnect metallization structure vias, and over the second dielectric layer;
• FIGURE 15 illustrates the patterning and etching of the blanket metal layer, resulting with a first interconnect and a second interconnect ; and
• FIGURE 16 illustrates an integrated circuit, which is one embodiment where the present invention may be used.
• the thin film resistor device 100 contains interconnect metallization structures 110, formed on a substrate 120.
• the substrate 120 may be any layer in a semiconductor device, including a layer located at wafer level or a layer located above wafer level .
• the substrate may be an interlevel dielectric layer formed over traditional transistor devices.
• the completed thin film resistor device 100 also contains a first dielectric layer 140 formed over the interconnect metallization structure layer 130 and interconnect metallization structures 110.
• the first dielectric layer 140 may be further located between the interconnect metallization structures 110 and a resistive layer 150.
• the resistive layer 150 forms an integral part of the completed thin film resistor device 100.
• the resistive layer 150 has a first contact pad 160 and second contact pad 165 located thereon. As illustrated, the first and second contact pads 160, 165, may be located on opposing ends of the resistive layer 150.
• the contact pads 160, 165 in an exemplary embodiment, comprise a stack of one or more metals .
• a second dielectric layer 170 Located on the resistive layer 150 and a portion of the contact pads 160, 165, may be a second dielectric layer 170.
• the second dielectric layer 170 may comprise a similar material to the first dielectric layer 140 and furthermore allows the completed thin film resistor device 100 to be used with aluminum interconnects.
• a first interconnect 180 that contacts the first contact pad 160
• a second interconnect 190 that contacts the second contact pad 165.
• the completed thin film resistor device 100 allows for the integration of such thin film resistors with aluminum interconnects, which are currently widely used in today's technology.
• the completed thin film resistor device 100 can be easily manufactured using current manufacturing tools while retaining the same resistor reliability as exhibited in prior art resistors, may be laser trimmable like the prior art resistors and may be generally invisible to the consumer, i.e., no changes to the consumer end tailoring process are required.
• FIGURES 2-15 illustrated are detailed manufacturing steps instructing how one might, in an exemplary embodiment, manufacture the completed thin film resistor device 100 depicted in FIGURE 1.
• FIGURE 2 illustrated is a partially completed thin film resistor device 200 after the deposition of an interconnect metallization structure layer 220 over a substrate 210.
• the substrate 210 may be the lowest interlevel dielectric layer located over a transistor device, and in an exemplary embodiment is silicon oxy-nitride.
• the interconnect metallization structure layer 220 may be conventionally formed.
• interconnect metallization structure layer 220 may be used to form the interconnect metallization structure layer 220.
• the interconnect metallization structure layer 220 is an aluminum layer.
• other materials could comprise the interconnect metallization structure layer 220.
• the interconnect metallization structure layer 220 is conventionally patterned, using photoresist portions 310, as illustrated in FIGURE 3.
• the unprotected interconnect metallization structure layer 220 is subjected to a traditional metal etch.
• a dry plasma etch may be used to remove the unprotected interconnect metallization structure layer 220 (FIGURE 2) ; however other similar etch processes could be used to remove the unprotected interconnect layer 220, if compatible with the design of the device.
• the photoresist is removed, resulting in interconnect metallization structures 320.
• the interconnect metallization structures 320 in a preferred embodiment, may contact transistor devices of a completed integrated circuit.
• the dielectric layer 410 is conformally deposited using a traditional plasma enhanced chemical vapor deposition (PECVD) process, resulting in the dielectric layer 410 shown.
• PECVD plasma enhanced chemical vapor deposition
• the dielectric layer 410 is a silicon oxy-nitride dielectric layer and may be deposited to a thickness greater than the thickness of the interconnect metallization structures 320.
• PECVD plasma enhanced chemical vapor deposition
• the deposition process is not limited to a PECVD process and that other deposition processes within the scope of the present invention could be used.
• the substrate upon which the completed thin film resistor 100 (FIGURE 1) is formed should be substantially planar.
• a thin layer of dielectric material 510 for example spin on glass (SOG) in a preferred embodiment, may be conventionally deposited over the conformal dielectric layer 410.
• CMP chemical mechanical planarization
• FIGURE 7 illustrated is the partially completed thin film resistor device 200 illustrated in FIGURE 6, after the formation of a first dielectric layer 710.
• the first dielectric layer 710 in an exemplary embodiment, may be deposited to prevent any exposed portions of the thin layer of dielectric material 510, especially SOG, from contacting a resistive layer, formed in FIGURE 8.
• the first dielectric layer 710 has a thickness similar to that of the as deposited dielectric layer 410, for example a thickness of about 1200 nm.
• the resistive material layer 810 in an exemplary embodiment, is a tantalum nitride (Ta 2 N) resistive layer having a thickness ranging from about 20 nm to about 80 nm.
• Ta 2 N tantalum nitride
• the resistive material layer 810 may be formed using a sputtering process .
• the sputtering process may be performed using a tantalum target sputtered in the presence of nitrogen gas and argon gas.
• the resistive material layer 810 may be formed using other processes known to those skilled in the art .
• the tantalum nitride resistive layer may be slightly under nitrided.
• the nitrogen concentration may ranges from about 23 atomic percent to about 26 atomic percent.
• the tantalum nitride resistive layer in an illustrative embodiment, may have a tetragonal crystal structure. Even though specifics have been given with respect to the tantalum nitride resistive layer, one having skill in the art understands that the resistive layer 810 is not limited to a tantalum nitride resistive layer, and that other materials, such as those listed above, could comprise the resistive material layer 810.
• the surface of the first dielectric layer 710 may be subjected to a wet chemical clean comprising NH 4 0H/H 2 0 2 , followed by a plasma oxidation for about 60 minutes at 300 watts.
• the plasma oxidation may be followed by a second wet clean chemistry similar to that used for the first wet chemical clean.
• a wet chemical clean comprising NH 4 0H/H 2 0 2
• the plasma oxidation may be followed by a second wet clean chemistry similar to that used for the first wet chemical clean.
• the contact pad layer 910 in an illustrative embodiment, is a stack layer comprising a titanium layer 920 and a platinum layer 930. However, in a more illustrative embodiment, the contact pad layer 910 comprises a titanium layer having a thickness of about 100 nm, a titanium nitride layer having a thickness of about 7.5 nm and a platinum layer having a thickness of about 200 nm.
• the contact pad layer 910 may be formed using conventional PVD or other similar processes.
• a nitric-sulfuric clean of the resistive layer 810 could be conducted at about 85°C for 10 minutes.
• a layer of photoresist may be deposited, patterned and developed resulting in photoresist portions 1010, illustrated in FIGURE 10.
• the partially completed thin film resistor device 200 may be subjected to an etching process, resulting in the first contact pad 1020 and second contact pad 1030, located on the resistive material layer 810.
• the first and second contact pads 1020, 1030 should have a width about 3000 nm wider than the via that contacts them.
• portions of the platinum layer 930 and the titanium layer 920 are removed using separate etchant mixtures from one another.
• the platinum layer 930 may be etched in aqua regia, i.e., a 4:3:1 solution of water, hydrochloric acid and nitric acid, for about 8 minutes at about 75°C, and the titanium layer 920 may be etched in a solution of sulfuric acid, for about 2.5 minutes at about 125°C. It should be noted that separate etching steps are not required, and a single etching step could be used if it were consistent with the design of the device. If the titanium nitride layer were used, as discussed above, it would also need to be etched using a similar process to the platinum layer 930 and titanium layer 920. In the illustrative embodiment, after completing the etch of the platinum layer 930 and titanium layer 920, the photoresist portions 1010 should be removed.
• FIGURE 11 illustrated is the etching of the resistive material layer 810 (FIGURE 8) .
• a layer of photoresist may be deposited, patterned within the bounds of the contact pads 1020, 1030 for the purpose of self alignment, and developed leaving photoresist portions 1110 to protect a portion of the resistive material layer 810.
• the resistive material layer 810 will comprise the thin film resistor.
• the partially completed thin film resistor device 200 may be subjected to an etch process .
• the etch may be conducted by placing the partially completed thin film resistor device 200 within a plasma etcher, for example a Matrix 303 downstream etcher, and removing those areas not protected by the photoresist portion 1110 or the contact pads 1020, 1030, resulting in a resistive layer 1120.
• a plasma etcher for example a Matrix 303 downstream etcher
• the partially completed thin film resistor device 200 may undergo a stabilization process.
• the resistive layer 1120 may be subjected to a temperature of about 325°C for about 16 hours in air, for a grain boundary stuffing with oxygen. This, in an exemplary embodiment, converts about 5 nm to about 10 nm of the tantalum nitride to tantalum pentoxide (Ta 2 0 5 ).
• a stabilization process For example, the resistive layer 1120 may be subjected to a temperature of about 325°C for about 16 hours in air, for a grain boundary stuffing with oxygen. This, in an exemplary embodiment, converts about 5 nm to about 10 nm of the tantalum nitride to tantalum pentoxide (Ta 2 0 5 ).
• Ta 2 0 5 tantalum pentoxide
• FIGURE 12 illustrated is a conformal deposition of a second dielectric layer 1210 over the first contact pad 1020, the second contact pad 1030, the resistive layer 1120 and the first dielectric layer 710.
• the second dielectric layer 1210 may comprise a similar material to the first dielectric layer 710, for example silicon oxy-nitride.
• the second dielectric layer 1210 may have a thickness ranging from about 240 nm to about 600 nm and may be deposited using a conventional CVD or other similar process.
• the second dielectric layer 1210 substantially isolates the resistive layer 1120 from subsequent processing steps, for example the chemistries used for the formation of vias and interconnects.
• FIGURE 13 illustrated is the formation of contact pad vias or windows 1310 and interconnect metallization structure vias or windows 1320.
• the contact pad vias 1310 are formed over and down to the first contact pad 1020 and second contact pad 1030, and the interconnect metallization structure vias 1320 are formed over and down to the interconnect metallization structures 320.
• the contact pad vias 1310 and the interconnect metallization structure vias 1320 are formed simultaneously.
• the vias 1310, 1320 have different depths, and as such, pose a problem with the contact pad vias 1310 wallering out while the interconnect metallization structure vias 1320 continue to be formed.
• the first and second contact pads 1020, 1030 should have a width about 3000 nm wider than the contact pad vias 1310. As a result, the contact pad vias 1310, even if wallered out, will remain over the first and second contact pads 1020, 1030.
• the blanket metal layer 1410 may be typically formed using a traditional PVD or CVD process, but other similar processes are within the scope of the present invention.
• the blanket metal layer 1410 in an exemplary embodiment may be an aluminum layer, however, in an alternative exemplary embodiment the blanket metal layer 1410 may be a titanium/titanium nitride/aluminum/titanium nitride stack.
• aluminum and its alloys are currently an interconnect metal of choice, nonetheless, other interconnect metals are also within the scope of the present invention.
• FIGURE 15 illustrated is the patterning and etching of the blanket metal layer 1410, resulting with a first interconnect 1510 and a second interconnect 1520.
• a layer of photoresist may be deposited, patterned and developed leaving photoresist portions 1530 protecting areas of the blanket metal layer 1410 that is desired to remain.
• the unprotected areas are then subjected to a traditional metal etch, resulting in the first interconnect 1510 and the second interconnect 1520. It is this traditional metal etch that the resistive layer 1120 should not come into contact with.
• the first interconnect 1510 contacts the first contact pad 1020 and one interconnect metallization structure 320
• the second interconnect 1520 contacts the second contact pad 1030 and the other interconnect metallization structure 320.
• the photoresist portion 1530 may be removed, resulting in the completed thin film resistor device 100, illustrated in FIGURE 1.
• the integrated circuit 1600 may include complementary metal oxide semiconductor (CMOS) devices, bipolar devices, bipolar CMOS (BiCMOS) devices or any other type of similar device. Also shown in FIGURE 16, are components of the conventional integrated circuit 1600, including: a transistor 1610, a semiconductor wafer substrate 1620, a source region 1630, a drain region 1640, and a dielectric layer 1650.
• CMOS complementary metal oxide semiconductor
• BiCMOS bipolar CMOS
• components of the conventional integrated circuit 1600 including: a transistor 1610, a semiconductor wafer substrate 1620, a source region 1630, a drain region 1640, and a dielectric layer 1650.
• the integrated circuit 1600 contains the thin film transistor device 100, including: the interconnect metallization structures 110, the first dielectric layer 140, the resistive layer 150, the first and second contact pads 160, 165, the second dielectric layer 170 and the first and second interconnects 180, 190.
• the interconnect structures 110, 180,190 located within the dielectric layers 1650, 140, 170, electrically connect the transistors 1610 and the thin film resistor device 100 to form the integrated circuit 1600.
• each level of the integrated circuit 500 may be sequentially formed to the designed number of levels of the integrated circuit 1600.
• the present invention is not limited to the number of interconnect or dielectric levels shown, nor is the invention limited to the location of the thin film resistor device 100 within the integrated circuit 1600.

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• 2000
  • 2000-07-13 EP EP00948639A patent/EP1203400A1/de not_active Withdrawn
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