Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
  • H01L29/51—Insulating materials associated therewith
  • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
  • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
  • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Definitions

• the invention relates generally to perovskite materials.
• the invention relates ferroelectric materials usable in ferroelectric memory cells.
• Ferroelectric random access memories offer the possibility of a non-volatile memory to replace silicon ones since FRAMs do not require energy to retain their electrically impressed polarization state.
• the schematized general structure of an FRAM 10 is illustrated in FIG. 1 and includes two capacitor plates 12, 14 between which is placed a body 16 of ferroelectric material. Not only does the ferroelectric material 16 have a dielectric constant substantially in excess of unity, but also under the proper conditions the ferroelectric is bistable.
• the capacitor plates 12, 14 have poled the ferroelectric into either the upwardly or downwardly directed polarization state, the ferroelectric body 16 remains in that state even after the poling voltage is removed. That is, a charge (or voltage) remains on the cell 10 without any power being currently applied. Sometime later, the charge can be measured. Thereby, the FRAM 10 forms a non-volatile memory.
• the FRAM has included a polycrystalline ferroelectric material sandwiched between two metallic electrodes in a capacitor structure.
• Such a design however has suffered from reliability and aging problems.
• Dhote et al. have disclosed a platinum-based lower electrode in U.S. Patent Application, Serial No. 08/578,499, filed December 26, 1995, also published as PCT Publication 97/23886 on July 3, 1997.
• FRAM ferroelectric random access memory
• the overall FRAM structure is known and has been disclosed by Ramesh in the previously cited U.S. patents and applications. Kinney provides a good overview of FRAM integrated circuits in "Signal magnitudes in high density ferroelectric memories," Integrated Ferroelectrics, vol. 4, 1994, pp. 131-144.
• the FRAM 20 is formed on a (OOl)-oriented crystalline silicon substrate 22 so that other silicon circuitry can easily be incorporated.
• a metal-oxide-semiconductor (MOS) transistor is formed by diffusing or implanting dopants of conductivity type opposite to that of the substrate 22 into source and drain wells 24, 26.
• the intervening gate region is overlaid with a gate structure 28 including a lower gate oxide and an upper metal gate line, e.g., aluminum, to control the gate.
• a contact hole 32 is photolithographically etched through the first inter-level dielectric layer 30 over the source well 24, and polysilicon is filled therein to form a polysilicon contact plug to the transistor source 24.
• a metal source line 34 is photolithographically delineated on top of the first inter-level dielectric layer 30 and electrically contacts the polysilicon plug 32.
• a second inter-level dielectric layer 36 is then deposited over the first inter-level dielectric layer 30.
• Another contact hole 38 is etched through both the first and second inter- level dielectric layers 30, 36 over the area of drain well 26, and polysilicon is filled therein to form a contact to the transistor drain 26.
• a lift-off mask is then deposited and defined to have an aperture over the drain contact hole 38 but of a larger area for the desired size of capacitor, although in commercial manufacture a masked dry plasma etch would typically be performed. Over the mask and into the aperture are deposited a sequence of layers.
• a polysilicon layer 40 provides good electrical contact to the polysilicon plug 38.
• a TiN layer 42 and a platinum layer 44 form conductive barrier layers between the polysilicon and the oxidizing metal-oxide contacts.
• Polysilicon is semiconductive, but, if its surface is oxidized into SiO 2 , a stable, insulating layer is formed that prevents electrical contact.
• a layer 46 of a conductive metal oxide preferably a perovskite, such as lanthanum strontium cobalt oxide (LSCO), although other metal oxides may be used, especially layered perovskites.
• LSCO lanthanum strontium cobalt oxide
• This material has a composition nominally given by Lao 5 Sr 05 CoO 3 , although compositions of approximately La,_ x Sr x CoO 3 are possible with 0.15>x>0.85. It is now well known that LSCO forms an acceptable electrical contact, and it further promotes highly oriented growth of perovskite ferroelectric materials.
• the photomask is then lifted off leaving the lower stack of layers 40, 42, 44, 46 shown in FIG. 2.
• Another photomask is then defined allowing the conformal deposition of a
• Z-shaped field-oxide layer 48 which covers the sides of the previously defined lower stack, has a rim extending over the edge of the upper surface of the lower stack, and has a foot extending outwardly from the bottom of the lower stack, but leaves a central aperture for the after deposited upper ferroelectric stack.
• the field-oxide layer 48 electrically insulates the after deposited ferroelectric from the side portions of the lower electrode.
• the field-oxide layer 48 has been formed of SiO 2 or TiO 2 , but neither of these materials are ideal. Perovskite ferroelectrics when deposited over these materials tend to form in a mixture of perovskite and pyrochlore phases, which then differentially etch, resulting in unreliable etching.
• a better material for the field oxide layer 48 is bismuth titanate (approximately of the stoichiometric composition Bi 4 Ti 3 O 12 ), which is a perovskite and can be grown by the same growth process as the other perovskite layers. Ramesh in U.S.
• Patent 5,248,564 discloses that Bi 4 Ti 3 O 12 is a powerful templating layer for promoting the growth of crystallographically oriented perovskites over unoriented substrates so a Bi 4 Ti 3 O 12 field oxide layer 48 assures good quality ferroelectrics are grown over it.
• Other perovskite materials may be substituted for the bismuth titanate as long as they are not highly conducting and they display a low dielectric constant, e.g., not be a ferroelectric.
• the perovskite forms of the Bi 4 Ti 3 O 12 should have a layered structure, that is, have a c-axis lattice that is at least twice those of the a- and b-axes.
• ferroelectric layer 50 is then deposited under conditions favoring crystallographically oriented growth.
• the ferroelectric layer 50 comprises lead lanthanum zirconium titanate (PLZT) or lead niobium zirconium titanate (PNZT).
• PLA lead lanthanum zirconium titanate
• PNZT lead niobium zirconium titanate
• an upper conductive metal-oxide layer 52 Over the ferroelectric layer 50 is deposited an upper conductive metal-oxide layer 52, preferably symmetrically formed with the lower conductive metal-oxide layer 44, of a perovskite, such as LSCO.
• An upper platinum layer 54 is deposited over the upper conductive metal-oxide layer 52. This layer 54 is not considered to involve critical technology, and its platinum composition was selected only as an interim solution. It is anticipated that the composition will be changed to TiW or other metallizations common in silicon technology.
• the photomask is lifted off leaving the structure of the upper stack illustrated in FIG. 2.
• a third inter-level dielectric layer 56 is deposited and etched to cover the ferroelectric stack.
• This layer 56 is intended more as a passivation layer than as an inter-level dielectric.
• the upper electrode 54 is then electrically contacted by etching a via 60 through the third inter-level dielectric layer 56 overlying the ferroelectric stack, filling the via 60 with Ti/W, and delineating a metal capacitor line 62 of Al that electrically contacts the Ti/W plug 60.
• LSCO electrode 52, and the upper Pt layer 54 are typically deposited in a single chamber at a single temperature, the thermal budget becomes the product of the deposition temperature and the total deposition time.
• PNZT is a well known ferroelectric material. Dhote et al. give particular examples of the composition of PNZT as Pb 004 Nb 0 18 Zr 078 TiO 3 and PbNb 004 Zr 028 Ti 068 O 3 , that is, PNZT which is on one hand lead-poor or on the other hand lead-rich and zirconium-rich.
• ferroelectric memories of any sort A problem which needs to be addressed in ferroelectric memories of any sort is their fatigue behavior. It is generally observed that the ferroelectric or polarization properties of a ferroelectric cell degrade over a large number of read-write cycles. The polycrystalline cells suffer greatly from fatigue while the crystallographically oriented cells exhibit much greater resistance to fatigue. Nonetheless, fatigue is still believed to be problem with crystallographically oriented cells.
• a ferroelectric hysteresis loop 64 is illustrated in FIG. 3.
• the horizontal axis represents the voltage across the cell.
• the vertical axis represents the polarization of the material, whether immediately impressed or residual (remanent), that is, without a voltage being applied.
• the polarization is proportionately related to the time integral of the charge flowing into or from the cell.
• the hysteresis curve is highly non-linear. For this discussion, it is assumed that the characteristics are symmetric although this is not usually true in practice.
• the illustrated hysteresis curve implies that the hysteresis curve approaches a maximum polarization P sat as the applied voltage asymptotically approaches a saturation voltage V sat .
• the poling is usually performed along the voltage direction only to V max , which yields a P max of only about 90% of P sat .
• the pulsed polarization ⁇ P is equal to 2P r .
• the hysteresis curve should be as rectangular as possible. That is, the coercive voltage V c should be maximized for a given V max .
• V r should be made as large as possible and that the remanent polarization increases with the coercive voltage.
• ferroelectric memories are to be commercialized, they must be compatible with other silicon integrated circuits used in, for example, personal computers, computer work stations, and other computer controlled applications.
• a read transistor 66 is a read transistor 66, corresponding to the MOS transistor 23 in FIG. 2.
• a word line 68 controls the read transistors 66 of a column of memory cells 10, but in a direction orthogonal to the work line 68.
• the read transistor 66 selectively connects the ferroelectric cell 10 to a bit line 70, which is similarly connected to row of memory cells 10. That is, the word lines 68 and bit lines 70 run in perpendicular directions over a rectangular array of memory cells
• the ferroelectric cell 10 is temporarily connected to the bit line 70 and the charge stored on the cell 10, whether in the positive or negative state, is shared with a larger parasitic capacitance 74 associated with the bit line 70, thereby generating two possible voltages on the bit line 70.
• a sense amplifier 76 compares this voltage to a reference voltage resulting from a charge stored on a reference capacitor 78 and input to the sense amplifier 76 on line 79.
• the sense amplifier 76 outputs a digital signal OUT representing the charge state of the ferroelectric memory cell 10.
• the reference capacitor 78 is the parasitic capacitance associated with the complementary bit line -BL 79 not used in the current read cycle.
• the sense amplifier 76 is most often implemented as a cross-coupled bistable latch circuit that latches in one of two states depending upon which of the voltages on its two inputs lines 70, 79 is the highest. Hence, it is desirable to set the voltage on the reference capacitor 78 or associated bit line 79 at a voltage intermediate the complementary voltages induced on the active bit line 70 by the complementary states of the ferroelectric cell 10. All the above described operations are controlled, pre-charged, and discharged by a logic circuitry 80 having two power supply inputs at ground and at the DC power supply voltage V cc . As a result, barring the use of complex voltage multiplying circuitry, all operations within the memory circuit are limited to a maximum voltage swing of V cc .
• V max is limited to no more than approximately half of the power supply voltage V cc .
• the reading of a ferroelectric cell is typically done by dividing the charge stored on the ferroelectric capacitor with a larger capacitance associated with the bit line.
• V max or V sat is five time the coercive voltage V c . In any case, low values of the coercive voltage V c are reflected in low values of the saturation voltage V sat .
• the coercive voltage V c be 0.5 to 0.6VDC, with everything being switched by 0.9VDC.
• the saturation voltage V sat is also low.
• the ferroelectric layer have a minimum thickness of 0.23 ⁇ m or at least no less than 0.15 ⁇ m. At lesser thicknesses, the leakage current across the ferroelectric becomes excessive. As a result of the minimum thickness, the voltage applied across the ferroelectric layer must exceed a minimum value producing adequate capacitive charge storage.
• a ferroelectric cell The physical operation of a ferroelectric cell is believed to follow the mechanism illustrated in FIG. 5 for a simple ferroelectric material such as PZT ( PbZrTiO 3 ), PLZT (PbLaZrTiO 3 , and other well known materials. These first three materials are best characterized as alloys of the compounds PbZrO 3 , PbTiO 3 , LaZrO 3 , and LaNbO 3 , in the case of PLZT. Similar characterizations should be made for PNZT (PbNbZrTiO 3 ).
• a unit cell for these materials is generally tetragonal, that is, a rectangular cell having three perpendicular unit vectors, one having a value c and the other two having the same value a.
• c is greater than a.
• the ratio c/a will be defined to be the tetragonality factor of the ferroelectric material.
• the unit cell includes eight rare-earth atoms 82 of lead
• the low- energy cation position is located either above or below the cell center at one of the offset positions 86a, 86b.
• the displacement of the cation from the cell center provides the bistable ferroelectric behavior. Which of the two offset positions 86a, 86b the cation assumes determines the polarization state of the cell.
• the invention can be summarized as a ferroelectric capacitor cell having a crystallographically oriented ferroelectric layer formed on a metal-oxide electrode layer.
• the ferroelectric material is chosen to have a composition that has a low tetragonality factor, that is, a low c/a ratio for a tetragonal perovskite.
• the tetragonality factor may indicate a composition of a complex ferroelectric alloy that provides less than optimal ferroelectric characteristics. Nonetheless, a ferroelectric cell is likely to manifest better fatigue characteristics because of the less stress of the lower tetragonality factor, and the better characteristics may not be polable with voltage levels used in densely integrated memories.
• the effect has been demonstrated for lead lanthanum zirconium titanate (PLZT) and lead niobium zirconium titanate (PNZT).
• FIG. 1 is a schematic representation of a ferroelectric memory cell.
• FIG. 2 is a cross-sectional view of a ferroelectric memory cell to which the invention can be applied.
• FIG. 3 is a graph illustrating the important ferroelectric parameters of a ferroelectric cell.
• FIG. 4 is a electrical schematic diagram illustrating the read/write circuitry associated with a ferroelectric memory cell.
• FIG. 5 is a schematic orthographic illustration of the crystalline structure of ferroelectric materials such as PZT, PLZT and other perovskites.
• FIG. 6 is graph of hysteresis curves for two compositions of lead lanthanum zircotitanate.
• FIG. 7 is a graph of hysteresis curves for different poling voltages for a PLZT composition of the invention.
• FIG. 8 is a graph of hysteresis curves for three compositions of lead niobium zircotitanate.
• FIG. 9 is a graph of the switched polarization as a function of poling voltage for cells composed of PNZT with three values of niobium content.
• FIG. 10 is a graph of coercive voltage as a function of poling voltage for the three PNZT cells.
• FIG. 11 is a graph of bipolar switched polarization as a function of fatigue cycles for the three PNZT cells.
• the present invention attempts to take advantage of the countervailing considerations between large tetragonality promoting good ferroelectric behavior but poor fatigue characteristics and excessively high operating voltage and small tetragonality exhibiting poor ferroelectric characteristics but good fatigue characteristics and low operating voltages.
• the c/a factor of the ferroelectric material illustrated in FIG. 5, has major implications for the ferroelectric behavior and fatigue characteristics.
• a small c/a ratio means the unit cell is closer to a cubic symmetry while a larger ratio results in greater tetragonality of the cell.
• the larger the c/a ratio the greater is the polarizability of the material, as manifested by large values of the maximum polarization P max and of the remanent polarization P r .
• the lattice constant decreases in two dimensions from a 'to a while in the other dimension the lattice constant increases from a 'Xo c. Nonetheless, the newly tetragonal material remains atomically anchored to the substrate that does not undergo such a transition. As a result, the transition impresses a great amount of stress in the ferroelectric material, particularly near the interface with the templating layer, and the stress is larger for larger c/a ratios. Such high levels of stress are expected to drive several mechanisms contributing to fatigue and imprint in crystallographically oriented ferroelectrics.
• a second effect is that there are three possible orientations for the tetragonal structure as the material is cooled from the growth temperature to below the Curie temperature.
• the structure of FIG. 5 is based upon the generally preferred orientation that the c-axis is perpendicular to the plane of the templating layer. This is referred to as a c-domain.
• a c-domain This is referred to as a c-domain.
• one or the other of the two ⁇ -axes is perpendicular to the templating layer with the c-axis lying in the plane.
• These orientations are ⁇ -domains.
• the existence of both a- and c-orientations produce 90° domain walls between the two differentially oriented regions.
• Uniform c-domains are preferred, and generally the -domains will anneal to the orientation of the neighboring c-domains and form larger domains.
• any annealing at lower temperature includes a significant distortion from the existing crystal structure and the transition, while favorable, is difficult to activate. That is, the multiple orientations may be metastable.
• ferroelectric cells ultimately depends upon the switching of polarization domains. It is well known that ferroelectrics containing multiple domains with 90° domain walls between them require higher fields to switch compared to those with only 180° domain walls. Hence, it is desirable to suppress the multiple orientations arising from c-domains in the predominantly c-axis oriented ferroelectric material.
• ferroelectric integrated circuits which need to be operated at lower voltages should include a ferroelectric material of lower tetragonality, that is, a reduced c/a ratio though one having a value above unity.
• the c/a ratio may be described as a tetragonality factor for materials having the same or nearly the same a- axis lattice vectors in two directions.
• the polarization effects may be degraded by a lower c/a ratio, they may still be quite adequate.
• the fatigue characteristics are improved because of the reduced strain.
• the material is easier to anneal into a purely c-axis oriented material.
• ferroelectric cells of lower tetragonality are expect to be more easily switched. That is, the switching speed is increased. I believe, based on experiments presented below, that a c/a ratio of about 1.01 is most preferred, and beneficial results are obtained with values of the tetragonality factor extending down to 1.005.
• PLZT ferroelectric material
• Pb Pb
• x La x Zr y Ti Pb
• y a more compact designation
• x/y/l-y a large value of x decreases ferroelectric effects but favors crystalline quality because of the decreased tetragonality.
• PLZT with high values of x around 65% are used for electrooptical devices, but at these values of x, the material is non-tetragonal. I believe that for reduced voltage operation, PLZT should have a La content x of between 6 and 12%.
• the hysteresis loops are shown in FIG. 7: loop 94 for 5V poling; loop 96 for 2.3V poling; and loop 98 for 2V poling.
• the saturation polarization is about 35 ⁇ C/cm 2 at 5V, and the coercive voltages V c are all about 0.6V.
• PLZT capacitors may have somewhat less switchable polarization at longer pulse widths than do PZT capacitors, presumably because PLZT has a lower tetragonality factor than does PZT.
• the switchable polarization of PZT substantially falls while PLZT suffers a lesser decrease.
• the higher- lanthanum PLZT will operate better with very short pulse widths.
• PNZT PNZT
• Pb 1 . x Nb x Zr y Ti 1 . y O 3 Pb 1 . x Nb x Zr y Ti 1 . y O 3 .
• this material behaves similarly to PLZT, although less dramatically in the polarization effects, but the fatigue and timing effects are substantial.
• a series of prototype test capacitor structures were fabricated using the now conventional pulsed ablation deposition (PLD) technique.
• PLD pulsed ablation deposition
• a (lOO)-oriented silicon substrate was covered first with a TiN barrier layer.
• the TiN-covered substrate was then covered in a PLD process with a platinum contact layer.
• the ferroelectric layers were then grown by PLD in an oxygen environment at 600°C.
• the ferroelectric stack consisted of a lower contact template layer of LSCO, a PNZT ferroelectric layer, and a top contact layer of LSCO.
• the crystallographic parameters for thin films of Pb ! . x Nb x Zr 02 Ti 08 O 3 that is, (x/80/20)
• PNZT are given in TABLE 2.
• the fatigue results are even more interesting.
• the La or ⁇ b content should be raised to levels above those normally recommended for commercially viable ferroelectric memory cells.
• the lanthanum fraction x should be at least 3% and preferably more than 6% up to 12% when the Zr fraction is approximately 20%. I believe that 15% is the maximum preferred La fraction if reasonable polarizabilities are to be achieved.
• the highest value of the La content is limited by the PLZT forming in a non-ferroelectric phase.
• the Zr fraction can be increased to 50%, for which the La fraction is much less, preferably around 2%.
• the memory cell presented in FIG. 1 is presented only to explain the exact structure used in the examples.
• Other structures of crystallographically oriented ferroelectrics may be used. Particularly preferred are those not requiring any platinum, such as the one incorporating an intermetallic barrier, disclosed by Dhote et al. in U.S. Patent Application 08/582,545, filed January 3, 1996 and by Dhote et al. in U.S. Patent Application 08/871,059, filed June 19, 1997.
• the former corresponds to PCT Publication WO 97/25745.
• the invention thus provides a ferroelectric cell that trades off unneeded polarization for needed stress reduction, resulting in less fatigue and higher switching speeds.

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