EP1119937B1 - Variable spread spectrum clock - Google Patents

Variable spread spectrum clock Download PDF

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Publication number
EP1119937B1
EP1119937B1 EP99946661A EP99946661A EP1119937B1 EP 1119937 B1 EP1119937 B1 EP 1119937B1 EP 99946661 A EP99946661 A EP 99946661A EP 99946661 A EP99946661 A EP 99946661A EP 1119937 B1 EP1119937 B1 EP 1119937B1
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EP
European Patent Office
Prior art keywords
counter
output
register
providing
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99946661A
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German (de)
English (en)
French (fr)
Other versions
EP1119937A4 (en
EP1119937A1 (en
Inventor
Keith Bryan Hardin
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Lexmark International Inc
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Lexmark International Inc
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Publication date
Application filed by Lexmark International Inc filed Critical Lexmark International Inc
Publication of EP1119937A1 publication Critical patent/EP1119937A1/en
Publication of EP1119937A4 publication Critical patent/EP1119937A4/en
Application granted granted Critical
Publication of EP1119937B1 publication Critical patent/EP1119937B1/en
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/02—Details
    • H03D1/04—Modifications of demodulators to reduce interference by undesired signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
    • H04B15/04—Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission

Definitions

  • This invention relates to the field of digital circuits, and more particularly, to a clock circuit having reduced measurable electromagnetic interference (EMI) emissions.
  • EMI electromagnetic interference
  • each circuit be readily variable so that the same hardware design may be produced in volume, yet the circuit may be varied in use, either radically for widely different requirements, moderately for switching to a low activity mode, or slightly to optimize the operation for otherwise identical operation.
  • a reference signal drives one input of a phase detector while the other input is varied by values which define the spread spectrum.
  • the memory for such value receives and stores variable data.
  • the memory is loaded with such data at initialization or power-on reset by the data processor.
  • the circuit passes signals from the data processor to the components which vary the spectrum.
  • the memory has control data and the data processor issues a signal which causes the circuit to pass signals from the memory to the components which vary the spectrum.
  • the circuitry which controls the spectrum is a loop having two counters. One is set from a register which is programmable. That one drives a counter which is set from the memory. This combined use of the register and the memory permits the memory size to be substantially reduced. Similarly, such memory size is further reduced by the output of the memory being added to the programmable content of a register, with that sum being entered into the second counter.
  • Fig. 1 is a functional circuit diagram of one embodiment
  • Fig. 2 is a similar drawing of a very similar equivalent embodiment.
  • a crystal 1 or outer standard reference source controls a steady state oscillator 3.
  • the preferred frequency may be 3.5 megaHz to 100 megaHz.
  • Line 5 is a lead from oscillator 3 bypassing the spread spectrum control circuit.
  • Oscillator 3 drives thirty-two state counter 7. For all counters in this embodiment an output is produced when the counter reaches a maximum or terminal count (thirty-two in the case of counter 7) by counting up or down.
  • the counter sizes are preferred but other sizes may be used depending on application.
  • the count begins at the reset amount. (Assuming register 9 contains 8, counter 7 reaches 0 (i.e., is reset at count 32) after 24 transitions from oscillator 3, at which time it produces an output pulse to phase detector 11 and is again reset to 8.)
  • Register 9 is programmable at initialization.
  • phase detector 11 is switched current signal proportional in time to the difference in phase between the signal from counter 7 and the signal from 256 state counter 13, which is the other input to phase detector 11.
  • the output of phase detector 11 passes to loop filter 15; the output of loop filter 15 drives voltage controlled oscillator 16.
  • Phase detector 11 and filter 15 is also known as phase frequency detector and charge pump.
  • the foregoing description of elements 11, 15 and 16 may be entirely standard elements of phase locked loops, the loop filter 15 typically being a shunt circuit to ground of a capacitor (not shown) in parallel with a resistance and capacitance (not shown) in series.
  • Voltage controlled oscillator 16 drives one (i.e., bypass) or more state counter 17, which is reset by programmable register 19.
  • the output of counter 13 drives one input of phase detector I 1 and 256 state counter 21.
  • Counter 21 is reset by programmable register 23.
  • Counter 13 is reset with entry of the content of adder 25 from the output of adder 25.
  • normal operation switching circuit (multiplexer) 27 passes four bits of digital data from 256 byte random access memory 29 to one input of adder 25.
  • a second input of adder 25 receives the digital content of register 31. The data from memory 29 and register 31 are summed in adder 25.
  • Counter 13 is reset when it reaches 256 to the content of adder 25.
  • initiation data processor 33 (shown illustratively, normally a microprocessor) first loads programmable register 35 to a value which sets flip flop circuit 37 which controls multiplexer 27 to pass signals only on line 39. Signals on line 39 are from data processor 33. These signals are initiation data. The initiation data may define some spread spectrum characteristics, but this is not essential since they control only during initiation. Initially all of the registers are at a preset value, but oscillator 3, the counters and the phase locked loop, including voltage controlled oscillator 16, are operational, so a clock signal is generated. Using the clock signal, data processor 33 fills the programmable registers and RAM 29 and then applies a start signal on line 44.
  • the start signal on line 44 resets counter 21 and produces a signal on line 41 which reverses flip flop 37, causing multiplexer 27 to pass only the data from memory 29.
  • the signal on line 44 may also be reset by different devices, like video, horizontal sync, another spread spectrum generator or any signal that the modulation profile is to be synchronized to.
  • Memory 29 has variable data uniquely addressed by each output of counter 21 to define a spread spectrum output from the output of voltage controlled oscillator 16. This is reduced in frequency by being input to divider 43 (also a counter) which is reset by register 45. (Register 45 is not variable.)
  • the output of divider 43 is connected through multiplexer 47 to drive an electrical apparatus 49 (shown illustratively) such as a printer or computer.
  • Multiplexer 47 may be switched by a signal on line 51 to pass the signal on line 5 from oscillator 3, thereby bypassing the spread spectrum signal.
  • the contents of counter 17 varies the period of time before a single digital value from RAM 29 produces an output from counter 13.
  • the content of register 23 defines the number of values, from RAM 29 used before the pattern is repeated. Of course, the content of RAM 29 is selected to conform to the register values and the desired spread spectrum pattern.
  • phase locked loop bandwidth is the best mode to operate the phase locked loop to give a smooth, accurate profile for voltage controlled oscillator frequencies between 96MHz to 200 MHz respectively.
  • the ideal transfer function with operating point of the phase locked loop is shown below as a standard Laplace transform.
  • CL th ( s ) is the ratio of clock output frequency to the input frequency at the reference input of the phase detector 11. This transfer function is used to determine the values of the phase locked loop parameters which include the voltage controlled oscillator 16 gain, filter 15 current, capacitance to ground of filter 15, resistance capacitance in series to ground of filter 15, for given feedback division and input frequency values.
  • n 1 , n 2 , d 1 , d 2 and d 3 were empirically determined for the particular operating point and are directly related to the phase locked loop parameters listed above.
  • a PD post divider number
  • FBD feedback divider number C 1 , C 2 ,
  • R 1 loop filter values
  • n 1 6.04167*10 10
  • n 2 2.77778*10 4
  • This circuit is entirely flexible and may be used for a wide variety of applications, all under program control of data processor 33.
  • clements having substantially identical function to those of the Fig. 1 embodiment have the same reference numerals. Consistent with that, only 256 state counter 60 has a new number. That is true because the output of voltage controlled oscillator 16 is employed, through counter 60, as the reference signal input in the phase locked loop formed by phase detector 11, loop filter 15 and voltage controlled oscillator 16.
  • the data entered in RAM 29 is somewhat different from that of the Fig. I embodiment to provide the desired spectrum where the reference signal source of the phase locked loop is the voltage controlled oscillator 16 rather than the external crystal 1 and the external crystal 1 directly drives counter 17.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP99946661A 1998-10-08 1999-08-27 Variable spread spectrum clock Expired - Lifetime EP1119937B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/169,110 US6167103A (en) 1998-10-08 1998-10-08 Variable spread spectrum clock
US169110 1998-10-08
PCT/US1999/019653 WO2000021237A1 (en) 1998-10-08 1999-08-27 Variable spread spectrum clock

Publications (3)

Publication Number Publication Date
EP1119937A1 EP1119937A1 (en) 2001-08-01
EP1119937A4 EP1119937A4 (en) 2004-09-08
EP1119937B1 true EP1119937B1 (en) 2005-08-03

Family

ID=22614308

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99946661A Expired - Lifetime EP1119937B1 (en) 1998-10-08 1999-08-27 Variable spread spectrum clock

Country Status (8)

Country Link
US (1) US6167103A (zh)
EP (1) EP1119937B1 (zh)
JP (1) JP3975287B2 (zh)
KR (1) KR20010080031A (zh)
CN (1) CN1158808C (zh)
AU (1) AU5902499A (zh)
DE (1) DE69926521T2 (zh)
WO (1) WO2000021237A1 (zh)

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US6643317B1 (en) * 2000-02-25 2003-11-04 Electronics For Imaging, Inc. Digital spread spectrum circuit
US6980581B1 (en) * 2000-07-18 2005-12-27 Cypress Semiconductor Corp. Adaptive spread spectrum
US6665019B1 (en) * 2000-07-28 2003-12-16 Koninklijke Philips Electronics N.V. Method and apparatus for spread spectrum clocking of digital video
US6404834B1 (en) * 2000-09-20 2002-06-11 Lexmark International, Inc. Segmented spectrum clock generator apparatus and method for using same
US6356127B1 (en) * 2001-01-10 2002-03-12 Adc Telecommunications, Inc. Phase locked loop
JP3567905B2 (ja) * 2001-04-06 2004-09-22 セイコーエプソン株式会社 ノイズ低減機能付き発振器、書き込み装置及び書き込み装置の制御方法
US6798302B2 (en) * 2001-05-06 2004-09-28 Altera Corporation Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system
EP1289150A1 (en) * 2001-08-24 2003-03-05 STMicroelectronics S.r.l. A process for generating a variable frequency signal, for instance for spreading the spectrum of a clock signal, and device therefor
US8254430B1 (en) * 2001-09-10 2012-08-28 Narendar Venugopal Method and apparatus for detection and control of spread spectrum EMI reduction
JP3997069B2 (ja) * 2001-10-03 2007-10-24 キヤノン株式会社 周波数拡散発振器を有する集積回路装置及び該装置を有するインクジェット記録装置
US6658043B2 (en) 2001-10-26 2003-12-02 Lexmark International, Inc. Method and apparatus for providing multiple spread spectrum clock generator circuits with overlapping output frequencies
EP1333581B1 (de) 2002-01-30 2015-04-08 Infineon Technologies AG Taktsignalerzeugungseinrichtung
US7305020B2 (en) * 2002-02-04 2007-12-04 Vizionware, Inc. Method and system of reducing electromagnetic interference emissions
JP3958084B2 (ja) * 2002-02-08 2007-08-15 キヤノン株式会社 光学的記録再生方法
US6982707B2 (en) * 2002-03-14 2006-01-03 Genesis Microchip Inc. Method and apparatus utilizing direct digital synthesizer and spread spectrum techniques for reducing EMI in digital display devices
KR100456285B1 (ko) * 2003-02-12 2004-11-09 한국과학기술원 위상 반전을 이용한 스프레드 스펙트럼 클럭 발생기
US20050105591A1 (en) * 2003-02-28 2005-05-19 Xemi, Inc. Noise source synchronization for power spread signals
US7561652B2 (en) * 2003-04-22 2009-07-14 Paul Kevin Hall High frequency spread spectrum clock generation
US20050028020A1 (en) * 2003-07-28 2005-02-03 Ryan Zarrieff Spread spectrum clocking for data transfer bus loading
US6974779B2 (en) * 2003-09-16 2005-12-13 Tokyo Electron Limited Interfacial oxidation process for high-k gate dielectric process integration
US7363563B1 (en) 2003-12-05 2008-04-22 Pmc-Sierra, Inc. Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers
US7515646B2 (en) 2004-02-05 2009-04-07 Lexmark International, Inc. Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway
US7161970B2 (en) * 2004-09-10 2007-01-09 Ftd Solutions Pte, Ltd. Spread spectrum clock generator
US20070206641A1 (en) * 2005-11-10 2007-09-06 X-Emi, Inc. Encoding and deserialization-serialization for digital signals
US8035455B1 (en) 2005-12-21 2011-10-11 Cypress Semiconductor Corporation Oscillator amplitude control network
US7437590B2 (en) * 2006-02-22 2008-10-14 Analog Devices, Inc. Spread-spectrum clocking
KR100856123B1 (ko) * 2006-03-20 2008-09-03 삼성전자주식회사 Ｅｍｉ 방출을 감소시킬 수 있는 데이터 처리장치와 그방법
US7590163B1 (en) 2006-05-19 2009-09-15 Conexant Systems, Inc. Spread spectrum clock generation
US20080250175A1 (en) * 2007-04-03 2008-10-09 Vizionware, Inc. Cable assembly having an adaptive two-wire bus
US20080246626A1 (en) * 2007-04-03 2008-10-09 Vizionware, Inc. Data transaction direction detection in an adaptive two-wire bus
US20080250184A1 (en) * 2007-04-03 2008-10-09 Vizionware, Inc. Adaptive two-wire bus
US20080250170A1 (en) * 2007-04-03 2008-10-09 Vizionware, Inc. Clock mode detection in an adaptive two-wire bus
US20080247414A1 (en) * 2007-04-03 2008-10-09 Vizionware, Inc. Clock stretching in an adaptive two-wire bus
US7970042B2 (en) * 2008-01-11 2011-06-28 Lexmark International, Inc. Spread spectrum clock interoperability control and inspection circuit
US8340152B2 (en) * 2008-07-31 2012-12-25 International Business Machines Corporation Spread spectrum clocking with transmitted modulation
JP5567389B2 (ja) * 2010-05-17 2014-08-06 スパンション エルエルシー クロック発生回路
US11714127B2 (en) 2018-06-12 2023-08-01 International Business Machines Corporation On-chip spread spectrum characterization
US11146307B1 (en) 2020-04-13 2021-10-12 International Business Machines Corporation Detecting distortion in spread spectrum signals
US11693446B2 (en) 2021-10-20 2023-07-04 International Business Machines Corporation On-chip spread spectrum synchronization between spread spectrum sources

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Also Published As

Publication number Publication date
US6167103A (en) 2000-12-26
AU5902499A (en) 2000-04-26
JP3975287B2 (ja) 2007-09-12
EP1119937A4 (en) 2004-09-08
CN1325576A (zh) 2001-12-05
DE69926521D1 (de) 2005-09-08
KR20010080031A (ko) 2001-08-22
EP1119937A1 (en) 2001-08-01
JP2002527940A (ja) 2002-08-27
WO2000021237A1 (en) 2000-04-13
CN1158808C (zh) 2004-07-21
DE69926521T2 (de) 2006-06-08

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