Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
  • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a thin film semiconductor structure and methods of making such a structure.
• thin layer semiconductor structure means a structure having a thin semiconductor layer on the surface in which electronic devices will be manufactured (this layer is called the active layer) and a substrate playing a mechanical support role.
• This substrate is generally electrically insulated from the surface layer.
• the substrate is made either of a solid insulating material (a dielectric in the case of SOS), or of a conductive or semiconductor material. In the latter case, it may be the same material as that of the surface layer (case of SOI), generally isolated from the surface layer by an insulating layer.
• the mechanical substrate usually consists of a silicon substrate with a layer of silica on the surface, but it can also consist of a solid substrate of molten silica (silicon on quartz).
• Thin layer ser ⁇ conductive structures such as SOI structures are increasingly used to make electronic devices.
• SOI structures are used in particular to fabricate VLSI logic and analog circuits or to fabricate power components.
• An SOI structure (or substrate) has several advantages compared to a solid silicon substrate. One of these advantages is that the insulator underlying the silicon layer makes it possible to reduce the stray capacitances of the devices produced in the silicon layer, and this all the more so as this insulator is thick.
• a process that has become conventional for producing an SOI substrate is the SIMOX (Separation by IMplanted OXygen) process.
• the insulator is a buried layer of silicon oxide Si0 2 obtained by uniform implantation of oxygen in a silicon substrate.
• Wafer Bonding This technique is now competed with by other methods of the type called "Wafer Bonding" according to English terminology, (and which will be designated subsequently by the name of molecular adhesion), for example the BSOI method ( described by J. HAISMA et al. in Jap. J. Appl. Phys., vol. 28, page L 725, 1989) or the UNIBOND process (described by M. BRUEL in Electron. Lett., vol. 31, page 1201 , 1995).
• the SIMOX technique is still widely used. It is based on a very high dose oxygen implantation. It allows the production of buried layers of silica only for thicknesses between 100 and 400 nm.
• the major drawback of this technique is its cost due to ion implantation at high doses, and the need to use non-standard microelectronics equipment.
• Molecular adhesion type techniques do not have this drawback and, in principle, also make it possible to modulate the thicknesses of the layers as well as the nature of the material constituting the insulator.
• the UNIBOND process also allows lower cost and better homogeneity of the silicon layer.
• amorphous silica Si02 as the base material for the buried insulation layer. This material is a good insulator, is easy to manufacture and gives very good interfaces with silicon because it has few fixed charges and interface states. It also has a low dielectric constant, which is a favorable factor for the speed of the components because of the reduction in stray capacitances.
• silica has a major drawback: its very low thermal conductivity which is of the order of 0.02 W.rn ⁇ .K "1. This results in significant transient and localized heating, which is quite troublesome for the proper functioning of the One method to reduce this heating is to reduce the thickness of the buried silica layer.
• this reduction in thickness has the drawbacks on the one hand of increasing the parasitic capacities (therefore of reducing the speed of the components) and, on the other hand, to reduce the electrical resistance.
• the reduction in thickness of the insulating layer is not easy to obtain in the implementation of processes of the molecular adhesion type where good quality bonding is obtained much more easily with layers whose thickness exceeds 300 n.
• Sic type structures on silicon or AsGa on silicon with generally an intermediate insulating layer are also Sic type structures on silicon or AsGa on silicon with generally an intermediate insulating layer. These structures are often used for the production of microwave power components. As a result, the heat dissipation in the component is enormous and the thermal conductivity of the silicon and / or of the dielectrics used is insufficient to ensure a junction temperature which is not prohibitive.
• a thin layer semiconductor structure having several layers between the semiconductor surface layer, from which the electronic components will be produced, and the support substrate so as to decouple the functions thermal conductivity and electrical insulation.
• This decoupling makes it possible to optimize, by a choice of suitable materials, these two functions, it being understood that these materials must also allow a good interface quality (mechanical strength).
• the material in contact with the semiconductor layer must also have an interface of good electrical quality.
• the layer in contact with the semiconductor surface layer can be produced by means of an insulating layer offering good electrical insulation and good electrical interface quality.
• a layer of a material having thermal conductivity is used to remedy the problem of overheating produced by electronic components.
• Another layer can be used to ensure the quality bond with the support substrate if the layer of good thermal conductivity does not allow it. It can be of low thermal conductivity. If this layer is insulating, its role can also be to maintain a sufficient thickness of insulator of low permittivity under the surface semiconductor layer in order to keep low parasitic capacities for the electronic components and to allow an easy bonding in the case of the use of the molecular adhesion technique.
• the subject of the invention is therefore a semiconductor structure in a thin layer comprising a semiconductor surface layer separated from a support substrate by an intermediate zone, the intermediate zone being a multilayer electrically insulating the semiconductor surface layer from the support substrate, having an electrical quality d 'interface considered to be sufficiently good with the semiconductor surface layer and comprising at least a first layer, of thermal conductivity satisfactory for ensuring that the electronic device or devices which are to be developed from the semiconductor surface layer function as correct, characterized in that the intermediate zone also comprises a second layer, insulating and of low dielectric constant, located between the first support layer and substrate.
• the thickness of the first layer is chosen as a function of the size of the heat dissipation zones of the electronic devices.
• a thickness of the same order of magnitude or greater than the dimension of the largest heat dissipation zone will advantageously be chosen as the thickness for the first layer.
• this must be as thin as possible to optimize the role of the first layer.
• the second layer may be capable of ensuring an adhesion considered to be satisfactory between the intermediate zone and the support substrate.
• Good adhesion is understood to mean mechanical adhesion with the least possible macroscopic defects (that is to say localized lack of adhesion).
• the intermediate zone may comprise a third layer, insulating between the first layer and the semiconductor surface layer, said third layer conferring on the intermediate zone said electrical interface quality. If the semiconductor structure is an SOI structure, the third layer is advantageously a layer of silicon oxide obtained for example by thermal oxidation.
• the second layer may be a layer of silicon oxide.
• the first layer may not be insulating. Its thickness is adjusted according to the heat generation zones in the semiconductor layer. It can in particular be multilayer. More precisely, for the layer of good thermal conductivity to play its role effectively in the diffusion of the heat generated in the components, its thickness must be sufficient. Conversely, the thickness of any intermediate layers of relatively low thermal conductivity between this layer and the semiconductor layer should be minimized. In practice, the respective thicknesses of these layers necessary for proper thermal operation will depend on the size of the components and their operation (size of the heat dissipation zones) and on the thermal conductivities of the different materials (semiconductor layer, dissipative layer, layers and substrate).
• the first layer may consist of a material chosen from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride, silicon carbide.
• the first layer may be in contact with the semiconductor surface layer and be able to impart said electrical interface quality.
• the semiconductor structure being an SOI structure
• the first layer can be a layer of cubic silicon carbide.
• the second layer of the intermediate zone has a sufficient thickness of insulator of low dielectric constant so that the stray capacitances present between the semiconductor surface layer and the support substrate are sufficiently low to ensure a operation considered to be correct of the electronic device or devices which must be produced from the semiconductor surface layer.
• the subject of the invention is also a method of manufacturing a semiconductor structure as defined above, characterized in that it comprises the following steps:
• the production of said semiconductor surface layer may include reducing the thickness of the first substrate.
• Bonding of the first substrate on the second substrate can be achieved by molecular adhesion.
• the step of manufacturing the layers of the intermediate zone can comprise the deposition of at least one bonding layer to allow bonding by molecular adhesion.
• said bonding layer is a layer of silicon oxide.
• the first layer may be a layer of a material chosen from polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and the silicon carbide deposited by CVD.
• the reduction of the thickness of the first substrate can be obtained by the use of one or more techniques among: rectification, chemical attack, polishing, separation following a heat treatment along a cleavage plane induced by ion implantation.
• FIG. 1 shows, in transverse view, a semiconductor structure with a heat distribution layer according to the present invention
• FIG. 2A to 2D illustrate different stages of a first method of producing a semiconductor structure according to the present invention
• FIG. 3A and 3B illustrate different stages of a second method of producing a semiconductor structure according to the present invention.
• Figure 1 shows a first example of a semiconductor structure according to the invention.
• This structure comprises a support substrate 1 for example of silicon, a surface layer 2 of silicon and a intermediate zone 3.
• the intermediate zone 3 comprises at least one layer 4 of good thermal conductivity, an insulating layer 5 giving good electrical quality of the interface with the surface semiconductor layer 2 and an insulating layer 6, which can be of low thermal conductivity , adhering to the support substrate 1.
• layer 6 of silica In the case of an SOI structure implementing the molecular adhesion process, it is possible in particular to produce layer 6 of silica. This layer 6 can of course be a multilayer.
• the layer 4 of good thermal conductivity makes it possible to have a good electrical interface directly with the surface layer of silicon 2, the layer 5 can be omitted.
• the structure according to the invention makes it possible to keep the materials and the thicknesses allowing both easy manufacture and good functioning of the electronic devices which will be produced on or in the semiconductor surface layer.
• Layer 4 acts as a heat distributor and makes it possible to reduce the rise in temperature at the level of the heat emitting device while making it possible to keep the underlying layer or layers of low thermal conductivity and relatively thick.
• the insulating layer 5 can also be an insulating multilayer.
• the advantage of the invention from the thermal point of view can be shown by the following example relating to an SOI structure.
• a localized heating of 0.2 ⁇ m in diameter is assumed, roughly corresponding to the heating created by an advanced generation transistor.
• the resulting heating was calculated by fixing the nature (silica) and the thickness of the materials of layers 5 and ⁇ (respectively 0.1 and 0.3 ⁇ m) and we varied the nature and thickness of layer 4.
• layer 4 an insulating material and if possible a low dielectric constant. This in fact makes it possible to reduce the capacitances and the dielectric losses.
• FIGS. 2A to 2D A first method for producing a semiconductor structure according to the present invention will now be described in relation to FIGS. 2A to 2D.
• FIG. 2A shows a first substrate 10, for example made of silicon or Sic, on one side of which a layer 15 of an insulating material has been produced, with the substrate 10 having an electrical interface quality considered to be sufficiently good.
• the layer 15 is a layer of silica obtained by thermal oxidation.
• a layer 14 having a satisfactory thermal conductivity is then deposited on the layer 15.
• the materials capable of being used there may be mentioned polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering from an aluminum target, nitride silicon, aluminum nitride, boron nitride deposited by CVD and Sic deposited by CVD.
• an insulating layer 16 ′ which can facilitate bonding can optionally be deposited, preferably a layer of silica deposited for example by CVD, unless layer 14 allows direct bonding with a second substrate 11.
• the silicon substrate 10 has a layer 17 of microcavities arranged parallel to the face of the substrate on which the insulating layers 15, 14 and 16 ′ have been obtained.
• This layer of microcavities 17 delimits in the substrate 10 a layer 12 intended to become the semiconductor surface layer of the structure.
• the microcavities were obtained by ion implantation of hydrogen under the conditions described in document FR-A-2 681 472 in order to obtain a separation into two parts of the substrate 10 along a cleavage plane during a treatment. posterior thermal.
• the ion implantation operation can be carried out before or after obtaining the insulating layers 15, 14 and 16 ′ or between the deposition of one of these layers and the deposition of another layer.
• FIG. 2B shows a second substrate 11, for example made of silicon, serving as a support substrate, on one face of which a bonding layer 16 "has been produced.
• This bonding layer is preferably a layer of silica produced by thermal oxidation. 'is only necessary if the nature of the substrate 11 does not allow direct bonding with the layer 16'.
• FIG. 2C illustrates the step of bonding, by molecular adhesion, of the two substrates by bringing the free and prepared faces into contact with the bonding layers 16 'and 16 ".
• An appropriate heat treatment (see document FR-A-2 681 472) then makes it possible to obtain the separation into two parts of the substrate 10 along the layer of microcavities 17.
• the structure shown in FIG. 2D is then obtained, which is an SOI structure comprising a support substrate 11 and a silicon surface layer 12 separated by an intermediate zone 13.
• the zone 13 comprises an electrical interface layer 15, a layer 14 of satisfactory thermal conductivity and a bilayer 16 (formed of the layers 16 'and 16 "in silica) ensuring good adhesion with the substrate 11.
• the free face of the surface layer 12 can then be conditioned by polishing and cleaning.
• FIG. 3A shows a first substrate 20, for example made of silicon, on one face of which a material of good thermal conductivity has been produced, for example by epitaxy, to obtain a corresponding layer 24.
• the epitaxy material can be cubic silicon carbide produced according to known techniques.
• an insulating layer 26 is then deposited, for example a layer of silica.
• the silicon substrate 20 has a layer 27 of microcavities arranged parallel to the face of the substrate on which the insulating layers 24 and 26 have been deposited.
• This layer of microcavities 27 delimits in the substrate 20 a layer 22 intended to become the layer semiconductor surface of the SOI structure.
• the layer 27 of microcavities was produced under the conditions described in the document FR-A-2 681 472.
• the two substrates are then bonded, by molecular adhesion, by bringing the free face of the layer 26 into contact (see FIG. 3A) with a free face of the substrate 21.
• the result obtained is shown in FIG. 3B.
• a suitable heat treatment step then makes it possible to obtain the separation into two parts of the substrate 20 along the layer of microcavities 27.
• the ionic implantation of hydrogen in the silicon carbide when this material is used, makes it perfectly insulating. This provides an SOI structure of the required quality.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
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• Materials Engineering (AREA)
• Element Separation (AREA)
• Recrystallisation Techniques (AREA)
• Thin Film Transistor (AREA)

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• 1998
  • 1998-07-10 FR FR9808919A patent/FR2781082B1/fr not_active Expired - Fee Related
• 1999
  • 1999-07-08 EP EP99929439A patent/EP1103072A1/fr not_active Ceased
  • 1999-07-08 KR KR1020017000370A patent/KR100662694B1/ko not_active IP Right Cessation
  • 1999-07-08 WO PCT/FR1999/001659 patent/WO2000003429A1/fr active IP Right Grant
  • 1999-07-08 JP JP2000559589A patent/JP2002525839A/ja active Pending

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