EP1078352B1 - A bus arrangement for a driver of a matrix display - Google Patents

A bus arrangement for a driver of a matrix display Download PDF

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Publication number
EP1078352B1
EP1078352B1 EP99921838.1A EP99921838A EP1078352B1 EP 1078352 B1 EP1078352 B1 EP 1078352B1 EP 99921838 A EP99921838 A EP 99921838A EP 1078352 B1 EP1078352 B1 EP 1078352B1
Authority
EP
European Patent Office
Prior art keywords
semiconductor switches
conductors
terminal
terminals
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99921838.1A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1078352A2 (en
Inventor
Roger Green Stewart
Frank Paul Cuomo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
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Thomson Licensing SAS
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Publication date
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Publication of EP1078352A2 publication Critical patent/EP1078352A2/en
Application granted granted Critical
Publication of EP1078352B1 publication Critical patent/EP1078352B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/10—Intensity circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes

Definitions

  • This invention relates generally to a bus arrangement for display devices and particularly to a system for applying brightness signals to pixels of a display device, such as a liquid crystal display (LCD) or a plasma display.
  • a display device such as a liquid crystal display (LCD) or a plasma display.
  • Display devices such as liquid crystal displays or plasma displays, are composed of a matrix or an array of pixels arranged horizontally in rows and vertically in columns.
  • the video information to be displayed is applied as brightness (gray scale) signals to data lines which are individually associated with each column of pixels.
  • the rows of pixels are sequentially scanned and the capacitances of the pixels within the activated row are charged to the various brightness levels in accordance with the levels of the brightness signals applied to the individual columns.
  • the M brightness information signals are applied to an input port of an input demultiplexer of the array.
  • the demultiplexer converts the M brightness information signals to MXN signals developed in MXN parallel conductors that are coupled via MXN data line drives to MXN column conductors of the array.
  • the input demultiplexer may be formed by MXN thin film transistor (TFT's). Groups of M parallel conductors are successively selected, during each horizontal line interval of the video signal. The selection of each group of M parallel conductors is obtained by selection pulse signals developed in a bus of N parallel conductors.
  • the capacitance of the input busing structure associated with the N selection parallel conductors and the input busing structure associated with the M brightness information carrying parallel conductors can be a major source of both power dissipation and yield loss, especially for higher resolution self-scanned Active Matrix Liquid Crystal Displays (AMLCDs).
  • AMLCDs Active Matrix Liquid Crystal Displays
  • Long metal runs across the display and multiple crossovers (Source/Drain metal-to-Gate metal) cause significant capacitive loads, resulting in both capacitance shorting failures, unwanted crosstalk among the brightness information carrying conductors and excessive dynamic power dissipation. It is desirable to reduce the number of crossovers of the input busing structure associated with the N selection parallel conductors and of the input busing structure associated with the M brightness information carrying parallel conductors.
  • Dependant claim relates to an advantageous embodiment.
  • FIGURE 1 illustrates an integrated driver arrangement for storing information in an SVGA liquid crystal array. It should be understood that the invention may be utilized for storing information in pixels of a plasma display.
  • Analog circuitry 11 receives a video signal representative of picture information to be displayed from, for example, an antenna 12. The analog circuitry 11 provides a video signal on a line 13 as an input signal to an analog-to-digital converter (A/D) 14.
  • A/D analog-to-digital converter
  • A/D converter 14 includes an output bus 19-to provide brightness levels, or gray scale codes, to a memory 21 having 100 groups of output lines 22. Each group of output lines 22 of memory 21 applies the stored digital information to a corresponding digital-to-analog (D/A) converter 23. There are 100 D/A converters 23 that correspond to the 100 groups of lines 22, respectively.
  • An output analog signal DBS(j) from a given D/A converter 23 is coupled via a corresponding brightness information carrying conductor DB(j) to a demultiplexer transistor MN1 associated with a corresponding column.
  • Transistors MN1 may be thin film transistors (TFTs).
  • TFTs thin film transistors
  • Demultiplexer transistor MN1 applies the information of signal DBS(j) carried on corresponding brightness information carrying conductor DB(j) to a corresponding sampling capacitor C43 for storing an analog signal VC43 in capacitor C43.
  • Signal VC43 is coupled to a corresponding data line driver 100 that drives corresponding data line 17 associated with a corresponding column.
  • a select line scanner 60 produces row select signals in lines 18 for selecting, in a conventional manner, a given row of array 16.
  • the voltages carried in 100 data lines 17 are applied during a 32 microsecond line time to pixels 16a of the selected row.
  • the sampling in a given group of 100 signals DBS(j) of FIGURE 1 carried in brightness information carrying conductors DB(j) occurs simultaneously under the control of a corresponding data-word pulse signal DWS(i) forming a selection word.
  • the symbol (i) assumes values from 1 to 24 associated with the 24 separate conductors DW(i).
  • Each pulse signal DWS(i) controls the sampling of a corresponding group of 100 signals DBS(j) in capacitors C43.
  • a two-stage pipeline cycle may be used.
  • Signals DBS(j) are demultiplexed and stored in 2400 capacitors C43 by the operation of pulse signals DWS(i). Then, the information in capacitors C43 is transferred simultaneously to data line driver 100. Thus, capacitors C43 become available for the demultiplexing of the next row information, while the previous row information is applied to the pixels.
  • FIGURE 1 may operate, for example, similarly to that described in, for example, U. S. Patent No. 5,673,063 in the name of Sherman Weisbrod , entitled "A DATA LINE DRIVER FOR APPLYING BRIGHTNESS SIGNALS TO A DISPLAY".
  • the busing arrangement of conductors DW(i) and DB(j), embodying an inventive feature, is explained in connection with FIGURE 2 . Similar symbols and numerals in FIGURES 1 and 2 indicate similar items or functions.
  • the crossover capacitance of the input busing structure associated with conductors DW(i) and DB(j) can be a major source of both power dissipation and yield loss, especially for higher resolution self-scanned Active Matrix Liquid Crystal Displays (AMLCDs).
  • AMLCDs Active Matrix Liquid Crystal Displays
  • Long metal runs across the display and multiple crossovers (Source/Drain metal-to-Gate metal) cause significant capacitive loads, resulting in both capacitance shorting failures, unwanted crosstalk among the brightness information carrying conductors, and excessive dynamic power dissipation.
  • the busing arrangement of FIGURE 2 reduces the number of capacitive crossovers associated with the input bus structure thus reducing the power dissipation and improving yield.
  • the brightness information carrying conductors DB(j) instead of being arranged individually and uniformly across the display, are grouped together into local “clusters” such as, for example, brightness information carrying conductors DB(1) - DB(4).
  • the cluster of brightness information carrying conductors DB(1) - DB(4) are coupled to four transistors MN1 having gate electrodes that share, in common, conductor DW(24).
  • the number of crossovers of brightness information carrying conductors DB(j)-to-data-word conductors DW(i) have been reduced by a factor of about 4 : 1. This, advantageously, reduces dynamic power dissipation, improves yield and reduces the crosstalk among the brightness information carrying-conductors.
  • the cluster busing arrangement adds a multiplicity of new local sub-arrays DBSA to the bus structure. Although these new local sub-arrays do add some additional crossovers of their own (2.5 per brightness information carrying conductor), this is a small price to pay for reducing the average number of crossovers in the main brightness information carrying conductor to data-word conductor matrix from 20/data-line to only 5/data-line. The total capacitive coupling in the input bus structure is thereby cut by a factor of approximately 4 using the cluster bus technique.
  • cluster busing therefore, include higher yield, lower power dissipation, and reduced crosstalk.
  • another advantage to cluster busing is that we now break up the pattern of consecutive columns connected to a single signal DBS(j). Small errors in signal DBS(j)-to-signal DBS(j) will normally result in noticeable "block” errors because the human eye is very sensitive to large block patterns. Using the cluster bus technique, the blocks are broken-up into a finer pitch that is, advantageously, less obvious to the viewer.
  • the structure may be improved through the addition of clusters of sub-arrays to reduce the complexity and capacitance of the main array.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Electronic Switches (AREA)
EP99921838.1A 1998-05-16 1999-05-11 A bus arrangement for a driver of a matrix display Expired - Lifetime EP1078352B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8576698P 1998-05-16 1998-05-16
US85766P 1998-05-16
PCT/US1999/010227 WO1999060555A2 (en) 1998-05-16 1999-05-11 A buss arrangement for a driver of a matrix display

Publications (2)

Publication Number Publication Date
EP1078352A2 EP1078352A2 (en) 2001-02-28
EP1078352B1 true EP1078352B1 (en) 2015-07-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP99921838.1A Expired - Lifetime EP1078352B1 (en) 1998-05-16 1999-05-11 A bus arrangement for a driver of a matrix display

Country Status (9)

Country Link
EP (1) EP1078352B1 (enExample)
JP (1) JP5240884B2 (enExample)
KR (1) KR100660446B1 (enExample)
CN (1) CN1183501C (enExample)
AU (1) AU3894799A (enExample)
MX (1) MXPA00011202A (enExample)
TW (1) TW519612B (enExample)
WO (1) WO1999060555A2 (enExample)
ZA (1) ZA200006423B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100578911B1 (ko) 2003-11-26 2006-05-11 삼성에스디아이 주식회사 전류 역다중화 장치 및 이를 이용한 전류 기입형 표시 장치
KR100578913B1 (ko) 2003-11-27 2006-05-11 삼성에스디아이 주식회사 역다중화기를 이용한 표시 장치 및 그 구동 방법
KR100578914B1 (ko) 2003-11-27 2006-05-11 삼성에스디아이 주식회사 역다중화기를 이용한 표시 장치
KR100589381B1 (ko) 2003-11-27 2006-06-14 삼성에스디아이 주식회사 역다중화기를 이용한 표시 장치 및 그 구동 방법
KR101126343B1 (ko) * 2004-04-30 2012-03-23 엘지디스플레이 주식회사 일렉트로-루미네센스 표시장치
KR100600350B1 (ko) 2004-05-15 2006-07-14 삼성에스디아이 주식회사 역다중화 및 이를 구비한 유기 전계발광 표시 장치
KR100622217B1 (ko) 2004-05-25 2006-09-08 삼성에스디아이 주식회사 유기 전계발광 표시장치 및 역다중화부
TWI309813B (en) 2005-12-23 2009-05-11 Au Optronics Corp Display device and pixel testing method thereof
JP6064313B2 (ja) 2011-10-18 2017-01-25 セイコーエプソン株式会社 電気光学装置、電気光学装置の駆動方法および電子機器
JP6141590B2 (ja) 2011-10-18 2017-06-07 セイコーエプソン株式会社 電気光学装置および電子機器
JP2014029438A (ja) * 2012-07-31 2014-02-13 Sony Corp 表示装置、駆動回路、および電子機器
JP6535441B2 (ja) 2014-08-06 2019-06-26 セイコーエプソン株式会社 電気光学装置、電子機器、及び電気光学装置の駆動方法
JP6581951B2 (ja) * 2016-09-07 2019-09-25 セイコーエプソン株式会社 電気光学装置の駆動方法
JP6626802B2 (ja) * 2016-09-07 2019-12-25 セイコーエプソン株式会社 電気光学装置および電子機器
JP6702352B2 (ja) * 2018-05-07 2020-06-03 セイコーエプソン株式会社 電気光学装置及び電子機器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03121415A (ja) * 1989-06-30 1991-05-23 Toshiba Corp ディスプレイ装置

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
EP0238867B1 (en) * 1986-02-21 1994-12-14 Canon Kabushiki Kaisha Display apparatus
US5170158A (en) * 1989-06-30 1992-12-08 Kabushiki Kaisha Toshiba Display apparatus
JPH07152350A (ja) * 1993-11-30 1995-06-16 Sharp Corp 表示装置及びその駆動方法
JP3403027B2 (ja) * 1996-10-18 2003-05-06 キヤノン株式会社 映像水平回路
JP4011715B2 (ja) * 1997-03-03 2007-11-21 東芝松下ディスプレイテクノロジー株式会社 表示装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03121415A (ja) * 1989-06-30 1991-05-23 Toshiba Corp ディスプレイ装置

Also Published As

Publication number Publication date
JP2002516417A (ja) 2002-06-04
WO1999060555A2 (en) 1999-11-25
CN1301377A (zh) 2001-06-27
CN1183501C (zh) 2005-01-05
AU3894799A (en) 1999-12-06
EP1078352A2 (en) 2001-02-28
ZA200006423B (en) 2002-01-30
KR20010043655A (ko) 2001-05-25
KR100660446B1 (ko) 2006-12-22
JP5240884B2 (ja) 2013-07-17
TW519612B (en) 2003-02-01
MXPA00011202A (es) 2003-04-22
WO1999060555A3 (en) 2000-03-09

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