EP1075016B1 - Selbstjustierter genauer RHO Hochschicht-Widerstand für gemischte Signalanwendung - Google Patents

Selbstjustierter genauer RHO Hochschicht-Widerstand für gemischte Signalanwendung Download PDF

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EP1075016B1
EP1075016B1 EP00480073A EP00480073A EP1075016B1 EP 1075016 B1 EP1075016 B1 EP 1075016B1 EP 00480073 A EP00480073 A EP 00480073A EP 00480073 A EP00480073 A EP 00480073A EP 1075016 B1 EP1075016 B1 EP 1075016B1
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layer
resistor
regions
dielectric
capacitor
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French (fr)
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EP1075016A3 (de
EP1075016A2 (de
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Kai Shao
Shao-Fu Sanford Chu
Cerdin Lee
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GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Definitions

  • the invention relates to the fabrication of Integrated Circuit (IC) devices and, more particularly, to a method for forming a high value poly resistor of accurate value that is required in mixed-mode configurations, that is applications where capacitors coexist with logic applications on the same Integrated Circuit.
  • the developments in the semiconductor industry have, similar to developments in many other industries, been driven by improved semiconductor device performance at reduced cost.
  • the semiconductor industry serves and addresses the data processing industry (computers and the like) and a significant number of peripheral applications (video games and the like) in the entertainment industry. What these applications have in common is that data is handled in digital form and that the functions that are performed by the semiconductor devices are functions of data manipulation or functions of data storage.
  • the former category of functions is also referred to as logic functions, the latter category as memory functions. Since these functions are of a different nature, they have typically been provided by semiconductor devices that address either the logic function or the storage functions but not both simultaneously. This does not imply that no semiconductor device was ever created that did not incorporate both functions.
  • capacitors form a basic component of many of these analog circuits that are used for analog applications such as switched capacitor filters. It is well known in the art that capacitors are widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor.
  • DRAM Dynamic Random Access Memory
  • the layer of silicide is formed by the deposition of a layer of reactive metal, such as titanium or cobalt, over the surface of silicon (substrate) where the layer of silicide needs to be formed.
  • the reactive metal is annealed with the underlying silicon forming silicides such as TiSi 2 over the regions where low resistance electrical contact must be established.
  • a resistive load component can, in its simplest form, be created by sandwiching a lightly doped layer of polysilicon between two points of electrical contact. To the points of electrical contact can be connected for instance metal of polysilicon interconnect lines or interconnect lines that are created by N+ diffusion (thereby forming low resistance interconnect lines).
  • the sandwiched layer of poly serves as a resistor, which typically has a high resistive value.
  • Increased N+ dopant concentration in the poly will decrease the resistive value of the poly
  • another parameter that can be used to manipulate the resistive value is by the selection of the cross section of the layer of poly in a plane that is essentially perpendicular to the flow of current through the layer of poly. An increased surface area of the cross section will decrease the value of the resistance and visa versa.
  • the resistor load is applied to the SRAM, the resistor must make electrical contact with the gate electrode and the drain region of the pull-down transistor as well as to the metal line to pass gate transistor.
  • a resistor tab that makes contact with the gate and the drain regions can be created by depositing dopants at the interfaces between these regions and the resistive load.
  • the light doping of the poly determines the resistive value of the resistive load
  • the resistive load is interconnected to the surrounding components by means of a high dope implant on either side of the resistor for which a doping mask is used.
  • the resistive load has a high value of ohmic resistance.
  • the value of this ohmic resistance must further be within tight limits; the ohmic resistance must also remain within these tight limits when creating the resistive load within a manufacturing environment and over an extended period of time.
  • POCl 3 is used as a dopant for the polysilicon of the resistive load; this dopant however exhibits a significant amount of lateral diffusion making exact control of the resistive value of the load resistance very difficult to achieve.
  • the blanket implant methodology that is used to establish the interconnect points for the resistive load also does not lend itself to tight implant control due to the fact that a lower thermal budget with high implant energy is used for this implant.
  • the implant mask used during this process further does not accurately define the resistive load.
  • a method must therefore be provided that allows better control of the resistive value of the load resistor while at the same time allowing for tight control of the design parameters that determine the interconnect of the resistive load.
  • US 5,866,451 shows a process for a mixed mode capacitor with a SRAM and poly resistor.
  • US 6,069,036 discloses a semiconductor device wherein a resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction region are formed at both sides of the gate in the substrate.
  • a dummy gate electrode over the resistor where a first insulating layer is arranged between the resistor and the dummy gate electrode and an upper plate over the lower plate where a second insulating layer is arranged between the lower and upper plates, are simultaneously formed.
  • a metal silicide layer is then formed over the dummy gate electrode, the resistor, the gate electrode, the junction regions and the lower and upper plates of the analog capacitor.
  • US 5,527,722 discloses a semiconductor device with a high-voltage portion including NMOS transistor and PMOS transistor and a low-voltage portion including NMOS transistor and PMOS transistor .
  • the high-voltage NMOS transistor includes source/drain regions having N- regions that are self-ailgned with a gate and N+ regions ) that are self-aligned with sidewall spacers formed on sidewalls of the gate to improve reliability under continuous high voltage operating conditions.
  • the low voltage NMOS transistor includes source/drain regions that are self-aligned with sidewall spacers to permit channel lengths to be scaled to less than 2 microns.
  • the low-voltage PMOS transistor and high-voltage PMOS transistor include source/drain regions that are selfaligned with sidewall spacer extension regions formed over sidewall spacers permitting low-voltage PMOS transistor channel lengths to be scaled to less-than 2 microns.
  • a principle objective of the invention is to provide a method for the creation of a high value polysilicon resistor load component.
  • Another objective of the invention is to provide a method for the creation of a high value polysilicon resistor load component whereby the ohmic value of the resistor load is within tight limits.
  • Yet another objective of the invention is to provide a method for the creation of a high value polysilicon resistor load whereby the ohmic value of the resistor load does not vary within the sequential creation in a manufacturing environment of successive resistor load components.
  • a still further objective of the invention is to avoid lateral diffusion during the creation of a resistive load component.
  • a new method is provided, as defined in independent claim 1 for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor.
  • the resistive load is created using the concept of a self-alignment resistor mask.
  • the active areas in the surface of a substrate are defined with field isolation regions; a thin layer of gate oxide is created over these active regions.
  • the process starts with the deposition of a layer of poly 2 (no layer of poly 1 is used), this poly 2 is used for the gate electrode, for the bottom plate of the adjacent capacitor and for the resistor of high ohmic value.
  • the gate poly is doped; optionally the bottom plate of the capacitor can be doped.
  • a dielectric layer is deposited for the dielectric of the capacitor; a layer of poly 3 is deposited, patterned and etched to form the capacitor top plate.
  • the capacitor (dielectric and bottom plate), poly gates and the load resistor are patterned; the LDD regions for the poly gates are created.
  • the (gate, capacitor, resistor) spacers are formed, a key point of the invention is that during the etch of the spacers a resistive spacer (called spacer since it serves to space or separate the two contact points of the resistor) is formed over the surface of the (poly 2) resistor.
  • the source/drain implants are performed thereby concurrently performing (self-aligned, due to the resistor spacer) implants for the contact regions of the resistor. All contacts (gate poly, source/drain and two contact points on the resistor) are salicided to achieve lower contact resistance.
  • Fig. 1 there is shown a cross section of the semiconductor substrate 10 after the definition of the active regions, the formation of gate oxide, the deposition of a layer of poly 2 and the implant for the poly gate.
  • Field Oxide regions are used to electrically isolate the discrete devices, such as Field Effect Transistors (FETs), in ULSI circuits on semiconductor chips that are formed from silicon substrate.
  • FETs Field Effect Transistors
  • One conventional approach in the semiconductor industry for forming field isolation is by the Local Oxidation of Silicon (LOCOS) method.
  • LOCOS uses a patterned silicon nitride (Si 3 N 4 ) as an oxidation barrier mask, the silicon substrate is selectively oxidized to form the semi-planar isolation.
  • this method requires long oxidation times (thermal budget) and lateral oxidation under the barrier mask limits the minimum spacing between adjacent active device areas, and therefore prevents further increase in device packaging density.
  • One method of circumventing the LOCOS limitations and to further reduce the field oxide (FOX) minimum features size is to allow shallow trench isolation (STI).
  • STI shallow trench isolation
  • One method of making STI is to first etch trenches having essentially vertical sidewalls in the silicon substrate. The trenches are then filled with a CVD of silicon oxide (SiO 2 ) and the SiO 2 is then plasma etched back or polished back using CMP, to form the FOX isolation region. It is desirable to make FOX areas that extend higher than the substrate surface to avoid problems of recesses in the field oxide at the edge of the device areas.
  • the FOX regions 12 can typically be grown by patterning a composite insulator, oxidation mask that contains an overlying layer of silicon nitride and an underlying layer of silicon dioxide.
  • the patterning of this layer is accomplished via conventional photolithography exposure follower by Reactive Ion Etching (RIE).
  • RIE Reactive Ion Etching
  • the photoresist that is used for the patterning is removed via plasma oxygen ashing, the surface is wet cleaned and the thick layer of FOX is grown in the regions of the silicon substrate that are not covered with the composite insulator oxidation mask.
  • the composite insulator oxidation mask is then removed by using hot phosphoric acid for the removal of the silicon nitride layer and buffered hydrofluoric acid solution for the removal of the underlying layer of silicon
  • the layer 14 of gate oxide is next grown over the surface of the substrate at a temperature between 800 and 1000 degrees C in a steam oxygen ambient to a thickness of between 50 to 300 Angstrom.
  • the poly 2 layer 16 is next blanket deposited by using Low Pressure Chemical Vapor Deposition (LPCVD) at a temperature between 500 and 700 degrees C. to a thickness between 1000 and 5000 Angstrom, and preferably between 2000 and 3000 Angstrom.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the poly 2 layer is used to form the gate poly, the bottom plate of the capacitor and the body of the load resistor.
  • An N+ implant is performed into layer 16 of poly 2, this implant forms the conductivity level of the NMOS poly gate. During this implant, the PMOS region in the layer of poly 2 is masked with a photoresist mask 13.
  • the layer 16 of poly 2 is in this manner doped (18) with phosphorous ions at a dosage of between 4E14 and 2E15 atoms/cm 2 with an energy of between 50 and 100 KeV resulting in a N+ poly gate structure.
  • the ion implant to create PMOS devices is doping the layer 16 with indium or boron ions at a dosage of between 4E14 and 2E15 atoms/cm 2 with an energy of between 10 and 50 KeV.
  • the step as shown in Fig. 2 is an optional step.
  • Fig. 2 shows a cross section after this (optional) implant for the bottom plate of the capacitor.
  • Capacitor mask 20 of photoresist is used to define the capacitor bottom plate.
  • the implant 24 of the poly 2 layer 16 is an arsenic or phosphorous implant with a dopant concentration of between 1.2E20 and 2.8E20 atoms/cm 2 at an energy between 30 and 100 KeV.
  • the optional implant that is shown in Fig. 2 depends on the value of the load resistance that is being created whereby a resistance of higher value requires this capacitor implant in order to improve the capacitive conductivity relative to the resistivity of the created load resistor.
  • the sheet resistance of the poly layer 16 is typically less than 100 ohm/cm 2 while the sheet resistance for the load resistor is typically required to be in excess of 1 Kohm/cm 2 .
  • the bottom plate of the capacitor therefore needs more doping, the load resistor in the other hand is not critically dependent on specific doping parameters and conditions.
  • Fig. 3 shows a cross section after the deposition of a layer of dielectric for the capacitor and the deposition and patterning of a layer of poly 3 for the top plate of the capacitor.
  • Layer 24 is a layer of LPCVD silicon dioxide using tetraethylorthosilicate (TEOS) as a source at a temperature between 600 and 750 degrees C. to a thickness of between 100 and 1000 Angstrom.
  • TEOS tetraethylorthosilicate
  • the poly 3 layer 26 is blanket deposited by using Low Pressure Chemical Vapor Deposition (LPCVD) at a temperature between 500 and 700 degrees C. to a thickness between 1000 and 5000 Angstrom, and preferably between about 2000 and 3000 Angstrom.
  • Poly 3 layer 26 is in-situ doped using LPCVD at a temperature between about 530 and 600 degrees C. to a thickness between 1000 and 5000 angstrom using SiH 4 and PH 3 as the dopant gas.
  • the poly 3 layer is used to form the top plate of the capacitor.
  • the capacitor mask 28 is used to expose (using conventional process of photolithography) and subsequently etch the layer 26 of polysilicon thereby forming the top plate (not shown in Fig.
  • Polysilicon layer 26 can be etched by exposing the layer to oxygen or oxygen-plasma at high temperatures (over 100 degrees C.). Polysilicon can also be etched using RIE or a high plasma density using an etchant gas having a high selectivity of poly to oxide, such as a gas containing clorine (Cl) species. Techniques are also known in the art whereby polysilicon can be etched using SF 6 , SiO 2 and Si 3 N 4 with a fluorocarbon.
  • Fig. 4 shows a cross section patterning of the poly gates, the dielectric and the lower plate of the capacitor and the resistive load component.
  • Resistor mask 30 defines the load resistor
  • gate mask 32 defines the gate structure for a NMOS device
  • capacitor mask 34 defines the dielectric and the lower plate of the capacitor
  • gate mask 36 defines the gate structure for a PMOS device.
  • Conventional processes of photolithography expose layer 26 (of poly 3) and layer 24 (of TEOS) thereby forming the respective elements of the device as indicated.
  • the layer 16 of poly 2 is removed from the exposed areas thereby essentially leaving the poly 2 layers for the resistor, the gate electrodes and the capacitor in place. The contours of these elements are shown in Fig. 5 .
  • Fig. 5 shows a cross section after the LDD implant for the gate electrodes and the formation of the gate spacers, a spacer for the load resistive is formed concurrent with the formation of the gate spacers.
  • the LDD implants of the invention use small doses of implanted impurities in order to avoid any adverse affects on the value of the load resistor that is being formed.
  • the step after the gate electrode has been completed is the formation of self-aligned Lightly Doped Diffusion (LDD) regions adjacent to the gate electrode and adjacent to the regions of field oxide (for instance region 47 of N- polarity). These regions of LDD implant are (N-) regions 47, 48 and 50 and (P-) regions 68 and 70.
  • LDD Lightly Doped Diffusion
  • the LDD regions 48 and 50 are formed by a self-aligned implant of N-type dopant in the source/drain regions in the substrate, this is a first phase in forming the substrate N+ source/drain regions of the MOSFET.
  • the LDD regions 68 and 70 are formed by a self-aligned implant of P-type dopant in the source/drain regions in the substrate, this is a first phase in forming the substrate P- source/drain regions of the MOSFET.
  • a second N+/P+ implant is performed to set the conductivity of the gate regions to a desired level and to complete the N+/P+ source/drain regions. Titanium is then deposited on the exposed upper surfaces of the N+/P+ source/drain regions and the polysilicon gate region ard annealed, thereby causing the titanium to react with the underlying N+/P+ silicon of the substrate source/drain regions and the doped polysilicon gate to form titanium salicide on these surfaces.
  • LDD regions 47, 48, 50, 68, 70
  • the forming of LDD regions (47, 48, 50, 68, 70) for source and drain regions of the gate electrodes is based on the use of arsenic with an energy between 1 to 10 KeV and a dose between 1e14 to 1e16 atoms/cm 2 or on the use of phosphorous with an energy between about 10 to 50 KeV and a dose between 1e12 to 5e13 atoms/cm 2 .
  • the forming of LDD regions for source and drain regions of the gate electrodes is based on the use of indium with an energy between 1 to 10 KeV and a dose between 1e14 to 1e16 atoms/cm 2 or one the use of boron with an energy between about 5 to 40 keV and a dose between 1e12 to 5e13 atoms/cm 2
  • a layer 38, Fig. 5 , of poly 2 has remained in place after the process of patterning and etching of the layer 16 of poly 2 as highlighted under Fig. 4 .
  • This layer 38 is, during the formation of the LDD regions as indicated above, also subjected to dopant injection and, as a consequence, becomes an N- doped layer of poly 2. It is clear that the dopant used and the density of the dopant used determine the value of the resistor after the process of doping has been completed.
  • phosphorous or boron can be used as dopants at a dosage of between 1E13 and 3E14 atoms/cm 2 and an energy of between 30 and 60 KeV.
  • This level of doping results in a resistance value of between 1 and 500 gigaohm and depends or the requirements of the application of the resistor in the device functionality.
  • the LDD regions adjacent to the NMOS gate electrode 40 must be N- doped and must therefore be doped using phosphorous (or arson) as the dopant and under the processing conditions that have been indicated above.
  • the LDD regions adjacent to the PMOS gate electrode 46 must be P- doped and must therefore be doped using boron or indium as the dopant and under the processing conditions that have been indicated above.
  • Fig. 5 shows that, at this point in the discussion, the poly gate electrode structures 40 (NMOS) and 46 (PMOS) have been formed as well as the capacitor bottom plate 42, the capacitor dielectric 43 and the capacitor top plate 44. Further has been formed the load resistor 38, all of the structures having been formed on the surface of substrate 10. I-DD regions (N- regions 47, 48 and 50 and P-regions 68 and 70) have been implanted self-aligned with the gate structures and adjacent to the regions 12 of field oxide.
  • the next processing steps is the formation of the spacers on the sidewall of these structures, that is spacers 52 on the sidewalls of the load resistor, spacers 56 on the sidewalls of the NMOS gate electrode 40, spacers 54 on the sidewalls of the capacitor layers and spacers 58 on the sidewalls of the PMOS gate electrode structure 46.
  • Typical gate spacer materials are silicon nitride, silicon oxide, BSG, PSG, polysilicon, other materials preferably of a dielectric nature and CVD oxide formed from a TEOS source. Often used are amorphous materials that inhibit the deposition of epitaxial silicon thereupon.
  • Forming a gate spacer comprises, for instance, the thermally growing, grown in an oxygen steam ambient at a temperature between 850 and 1000 degrees C. and to a thickness of 50 to 200 Angstrom, of a thin oxide on the sides of said gate electrode using a short dry-oxidation process whereupon a conformal CVD oxide film is deposited by decomposing TEOS at between 600 and 750 degrees C. followed by an anisotropic dry etch thereby leaving the gate spacers on the sidewalls of the gate electrodes.
  • Another method of forming gate spacers is by a process including a substantially conformal deposition within the trench of a spacer of material that is selected from the group consisting of nitride, oxide, BSG, PSG and any combination thereof, and a subsequent, substantial anisotropic etch of this spacer material.
  • the load resistor spacer 60 is formed on the surface of the body 52 of the load resistor by using the resistor block mask 62.
  • the purpose of spacer 60 is to separate (or space) the contacts of the load resistor 52 as will become apparent during the subsequent discussion.
  • the load resistor spacer is therefore formed using the same materials as previously indicated for the spacers 52, 56, 54 and 58; the spacer 60 is typically formed to a thickness of between 1500 and 4000 Angstrom.
  • Fig. 6 shows the completion of the (N+) source 64 and (N+) drain 66 regions of the NMOS gate electrode 40, the (P+) source 68 and (P+) drain 70 regions of the PMOS gate electrode 46, as well as concurrent N+ implant of the contact regions 72 and 74 of the load resistor 38.
  • the N+ polarity type implants are based on arsenic or phosporous at a dose of between 2.0E14 and 1.0E16 atoms/cm 2 and an energy of between about 30 and 100 KeV.
  • the P-polarity type implants are based on boron or indium at a dose of between 1.0E15 and 1.0E16 atoms/cm 2 and an energy of between 50 and 90 KeV.
  • the latter implant is done at the same time as the previously detailed N+ implant of the source 64 and drain 66 regions of the NMOS gate electrodes 40 making regions 72 and 74 low resistance N+ regions. It must also be pointed out that the N+ implant into the contact regions 72 and 74 of the load resistance 38 is spaced by the spacer 60, the implant is therefore self-aligned with the resistance. This approach therefore eliminates the use of the contact mask implant that has been required in typical applications where an extra mask is needed for the implant of the N+ resistor contacts.
  • the surfaces where these contacts must be made are then salicided, that is the top surfaces of regions 72 and 74 and the surfaces of the source/drain regions (64/66 and 68/70), the surface of the gate electrodes (40 and 46) and the top (44) and bottom plate (42) of the capacitor.
  • This process of salicidation is, as previously indicated, performed by the deposition of a layer of reactive metal, such as titanium or cobalt, over the surfaces where the layer of silicide needs to be formed.
  • the reactive metal is annealed with the underlying layer (of poly 2, silicon or TEOS) forming silicides such as TiSi 2 over the regions where the (low resistance) electrical contact must be established.
  • the annealing is performed in a temperature between 600 and 700 degrees C. for a time of between 20 and 40 seconds and then a rapid thermal annealing in a temperature of between 800 and 900 degrees C. for a time between 20 and 40 seconds.
  • Fig. 7 shows a cross section of a detailed view of the load resistor. Most of the elements that are shown in this cross section have previously been discussed, remains to be pointed out the deposition of a layer 78 of Intra Level Dielectric (ILD). This layer has been patterned and etched to establish contact points with regions 72 and 74 of the load resistor, a layer of metal has been deposited over the layer 78 of ILD and selectively etched to remove the metal from above the layer of ILD in order to avoid electrical shorts between the contact regions 72 and 74 of the load resistor 38. A final process of polishing the surface of the layer 76 of metal completes the creation of the load resistor in the device environment that has been selected for the subject description as an example of a load resistor application.
  • ILD Intra Level Dielectric
  • the invention which provides a method for forming a self aligned precision resistor on a semiconductor substrate, the self-aligned resistor being formed with gate electrodes and a capacitor, can be summarized as follows:
  • the claimed invention which provides for forming a self aligned precision resistor on a semiconductor substrate, the self-aligned resistor being formed with gate electrodes and a capacitor, can be summarized as follows:
  • the claimed invention can further be summarized by the regions of surface isolation comprising a minimum of two regions whereby:
  • the claimed invention can further be summarized by the performing a first and second ion implant establishing conductivity of a gate electrode is performing ion implant into the first layer of dielectric that is shielded such and of a polarity species such that regions of conductivity for NMOS and PMOS gate electrodes are created in the first layer of dielectric that are adjacent to the first and the second field oxide regions with a restriction that MOS devices that are created adjacent to the first and the second field oxide regions are of opposite polarity.
  • the claimed invention can further be summarized by the ion implant to create NMOS devices is doping the first layer of dielectric with phosphorous or arson ions at a dosage of between 4E14 and 2E15 atoms/cm2 with an energy of between 50 and 100 KeV resulting in a N+ poly gate structure
  • the claimed invention can further be summarized by the patterning the third layer of dielectric is creating a layer of the third dielectric overlaying and being aligned with the second field oxide region, thereby creating a top plate of the capacitor.
  • the claimed invention can further be summarized by the patterning the second and the first layer of dielectric comprising:
  • the claimed invention can further be summarized by the creating spacers for the gate electrodes, for the capacitor structure and for the resistor thereby concurrently forming patterned layer of spacer material over the resistor is:
  • the claimed invention can further be summarized by the completing formation of the source and drain regions of the gate electrode is performing N+ polarity type implants self-aligned with a NMOS gate and performing P- polarity type implants self-aligned with a PMOS gate.
  • the claimed invention can further be summarized by forming regions of electrical contact on the resistor is exposing the resistor to the N+ polarity implant that is applied to complete the formation of the source and drain regions for the NMOS gate electrode, whereby the resistor is partially shielded from the exposure by a patterned layer of spacer material over the resistor, thereby forming regions of high electric conductivity in opposite extremities of the resistor.
  • the claimed invention can further be summarized by the points of electrical contact comprising the source and drain regions, a top and a bottom plate of the capacitor, the gate electrodes and opposite extremities of the resistor.
  • the claimed invention can further be summarized by a first additional step of exposing the first layer of dielectric to an N+ implantation, the first additional step being performed prior to the depositing a second layer of dielectric, thereby establishing conductivity of a bottom plate of the capacitor.
  • the claimed invention can further be summarized by second additional steps of forming electrical contacts to the salicided points of electrical contact, the second additional steps being performed after the step of forming layers of salicide on points of electrical contact, the second additional steps comprising:

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Claims (24)

  1. Verfahren zur Bildung eines selbstjustierten Präzisionswiderstands auf einem Halbleitersubstrat, wobei der selbstjustierte Widerstand mit Gate-Elektroden und einem Kondensator gebildet wird und das Verfahren Folgendes umfasst:
    - Bereitstellen eines Halbleitersubstrats (10), wobei das Substrat in ihm geschaffene n-dotierte und p-dotierte Bereiche aufweist, wobei das Substrat ferner aktive Bereiche aufweist, welche durch Oberflächen-Isolierungs-Bereiche begrenzt sind, wobei eine Schicht aus Gate-Oxid (14) die aktiven Bereiche überlagert;
    - Aufbringen einer ersten Schicht aus Dielektrikum (16) über dem Gate-Oxid, wodurch die Oberflächen-Isolierungs-Bereiche eingeschlossen werden;
    - Ausführen einer ersten lonenimplantierung, wodurch die Leitfähigkeit einer NMOS-Gate-Elektrode (40) in der ersten Schicht aus Dielektrikum (16) festgelegt wird;
    - Ausführen einer zweiten lonenimplantierung, wodurch die Leitfähigkeit einer PMOS-Gate-Elektrode (46) in der ersten Schicht aus Dielektrikum (16) festgelegt wird;
    - Aufbringen einer zweiten Schicht (24) aus Dielektrikum über der ersten Schicht aus Dielektrikum;
    - Aufbringen einer Polysiliziumschicht (26) über der zweiten Schicht aus Dielektrikum (24);
    - Versehen der Polysiliziumschicht (26) mit einem Muster, wodurch einer obere Platte (44) eines Kondensators gebildet wird;
    - Versehen der zweiten und der ersten Schicht (24, 26) aus Dielektrikum mit Mustern, wodurch die Gate-Elektroden, ein Widerstand (38) gebildet werden und ferner eine dielektrische Schicht und untere Platte (42) des Kondensators gebildet werden;
    - Bilden von LDD-Bereichen für Source (64, 68)- und Drain (66, 70)-Bereiche der Gate-Elektroden (40, 46);
    - Schaffen von Abstandshaltern (52, 54, 56, 58) für die Gate-Elektroden (40, 46), den Kondensator und den Widerstand (36), wobei gleichzeitig eine mit einem Muster versehene Schicht aus Abstandshaltermaterial (60) über dem Widerstand gebildet wird;
    - Fertigstellen der Bildung der Source (64, 68)- und Drain (66, 70)-Bereiche der Gate-Elektroden (40, 46), wobei gleichzeitig elektrische Kontaktbereiche auf dem Widerstand gebildet werden; und
    - Bilden von Salicide-Schichten an elektrischen Kontaktpunkten.
  2. Verfahren nach Anspruch 1, wobei die Oberflächen-Isolierungs-Bereiche mindestens zwei Bereiche enthalten, wodurch:
    - ein ganz links befindlicher Bereich einen ersten Feldoxid-Bereich (12) bildet;
    - ein ganz rechts befindlicher Bereich einen zweiten Feldoxid-Bereich (12) bildet;
    - Gate-Elektroden entgegengesetzter Polaritäten (40, 46) neben jedem der Feldoxid-Bereiche liegen;
    - der erste Feldoxid-Bereich (12) der Feldoxid-Bereich ist, über dem ein hochpräziser, hochohmiger Arbeitswiderstand (38) geschaffen wird;
    - der zweite Feldoxid-Bereich der Feldoxid-Bereich ist, über dem ein Kondensator (42, 43, 44) geschaffen wird;
    - sich eine NMOS-Gate-Elektrode (40) zwischen dem ersten Feld und dem zweiten Feld befindet; und
    - sich eine PMOS-Gate-Elektrode (46) neben dem zweiten Feldoxid-Bereich befindet.
  3. Verfahren nach Anspruch 1, wobei die erste Schicht aus Dielektrikum (16) Polysilizium mit einer Dicke zwischen 100 und 500 nm (1.000 bis 5.000 Ångström) umfasst.
  4. Verfahren nach Anspruch 1, wobei die zweite Schicht (24) aus Dielektrikum TEOS mit einer Dicke zwischen 10 und 100 nm (100 bis 1.000 Ångström) umfasst.
  5. Verfahren nach Anspruch 1, wobei die Polysilizium-Schicht (26) eine Dicke zwischen 100 und 500 nm (1.000 und 5.000 Ångström) aufweist.
  6. Verfahren nach Anspruch 1, wobei das Ausführen einer ersten und einer zweiten lonenimplantierung, wodurch die Leitfähigkeit einer Gate-Elektrode festgelegt wird, im Ausführen einer lonenimplantierung in die erste Schicht (16) aus Dielektrikum besteht, die derart abgeschirmt wird und eine derartige Art von Polarität aufweist, dass leitfähige Bereiche für NMOS- und PMOS-Gate-Elektroden (40, 46) in der ersten Schicht aus Dielektrikum geschaffen werden, welche neben dem ersten und zweiten Feldoxid-Bereich liegen, mit einer Einschränkung, dass neben dem ersten und zweite Feldoxid-Bereich geschaffene MOS-Vorrichtungen eine entgegengesetzte Polarität aufweisen.
  7. Verfahren nach Anspruch 6, wobei die lonenimplantierung zur Schaffung von NMOS-Vorrichtungen im Dotieren der ersten Schicht aus Dielektrikum mit Phosphor- oder Arsenionen in einer Dosierung zwischen 4E14 und 2E15 Atomen/cm2 mit einer Energie zwischen 50 und 100 KeV besteht, woraus eine N+ Poly-Gate-Struktur resultiert.
  8. Verfahren nach Anspruch 6, wobei die lonenimplantierung zur Schaffung von PMOS-Vorrichtungen im Dotieren der ersten Schicht aus Dielektrikum mit Indium- oder Borionen in einer Dosierung zwischen 4E14 und 2E15 Atomen/cm2 mit einer Energie zwischen 10 und 50 KeV besteht, woraus eine P+ Poly-Gate-Struktur resultiert.
  9. Verfahren nach Anspruch 1, wobei das Versehen der Polysiliziumschicht (26) mit einem Muster die Schaffung der Polysiliziumschicht umfasst, welche den zweiten Feldoxid-Bereich (12) überlagert und mit ihm fluchtet, wodurch eine obere Platte (44) des Kondensators geschaffen wird.
  10. Verfahren nach Anspruch 1, wobei das Versehen der zweiten (24) und der ersten Schicht (16) aus Dielektrikum mit einem Muster Folgendes beinhaltet:
    - Versehen des Widerstandes (38) mit einem ersten Muster, welches einen ersten Feldoxid-Bereich überlagert und mit ihm fluchtet;
    - Versehen der Gate-Elektroden (40, 46) mit einem zweiten Muster zwischen und neben dem ersten und zweiten Feldoxid-Bereich;
    - Versehen des Dielektrikums und der unteren Platte (42, 43) des Kondensators mit einem dritten Muster, welches unterhalb einer oberen Platte (44) des Kondensators liegt, wobei das dritte Muster einen zweiten Feldoxid-Bereich überlagert; und
    - Entfernen der zweiten und ersten Schicht (16, 24) aus Dielektrikum entsprechend dem ersten, zweiten und dritten Muster, wobei die erste Schicht aus Dielektrikum an ihrem Platz verbleibt und der Widerstand (38) und die Gate-Elektroden (40, 46) gebildet werden, wodurch ferner die erste (16) und zweite Schicht (24) aus Dielektrikum an ihrem Platz verbleiben und ein Dielektrikum (42) und eine untere Platte (43) des Kondensators gebildet werden.
  11. Verfahren nach Anspruch 1, wobei das Bilden von LDD-Bereichen (47, 48, 50, 68, 70) für Source- und Drain-Bereiche der Gate-Elektroden in einer LDD-Implantierung für eine NMOS-Implantierung unter Verwendung von Arsen mit einer Energie zwischen 1 und 10 KeV und einer Dosierung zwischen 1 e14 und 1 e16 Atomen/cm2 besteht.
  12. Verfahren nach Anspruch 1, wobei das Bilden von LDD-Bereichen für Source- und Drain-Bereiche der Gate-Elektroden in einer LDD-Implantierung für eine NMOS-Implantierung unter Verwendung von Phosphor mit einer Energie zwischen 10 und 50 KeV und einer Dosierung zwischen 1 e12 und 5e13 Atomen/cm2 besteht.
  13. Verfahren nach Anspruch 1, wobei das Bilden von LDD-Bereichen für Source- und Drain-Bereiche der Gate-Elektroden in einer LDD-Implantierung für eine PMOS-Implantierung unter Verwendung von Indium mit einer Energie zwischen 1 und 10 KeV und einer Dosierung zwischen 1 e14 und 1 e16 Atomen/cm2 besteht.
  14. Verfahren nach Anspruch 1, wobei das Bilden von LDD-Bereichen für Source- und Drain-Bereiche der Gate-Elektroden in einer LDD-Implantierung für eine PMOS-Implantierung unter Verwendung von Bor mit einer Energie zwischen 5 und 40 KeV und einer Dosierung zwischen 1 e12 und 5e13 Atomen/cm2 besteht.
  15. Verfahren nach Anspruch 1, wobei die Schaffung von Abstandshaltern (52, 54, 56, 58) für die Gate-Elektroden (40, 46) für die Kondensator-Struktur (42, 43, 44) und für den Widerstand (38), wodurch gleichzeitig eine mit einem Muster versehene Schicht aus Abstandshaltermaterial (60) über dem Widerstand (38) gebildet wird, Folgendes beinhaltet:
    - Aufbringen einer Schicht aus Abstandshaltermaterial, welches ausgewählt wird aus der Gruppe aus Nitrid, Oxid, BSG, PSG oder Polysilizium oder einer beliebigen Kombination hiervon, über dem Widerstand (38), Gate-Elektroden (40, 46) und Kondensator (42, 43, 44), wodurch eine freiliegende Oberfläche des Substrats eingeschlossen wird;
    - Abschirmen des Widerstands (38) gegen ein Muster, so dass der Widerstand im Wesentlichen gegen einen anschließenden Schritt des Versehens mit einem Muster blockiert ist, wobei Enden des Widerstands freiliegend bleiben; und
    - Ausführen eines im Wesentlichen anisotropischen Ätzvorgangs der Schicht aus Abstandshaltermaterial (60).
  16. Verfahren nach Anspruch 1, wobei das Fertigstellen der Bildung der Source- und Drain-Bereiche der Gate-Elektrode im Ausführen von Implantierungen des N+ Polarität-Typs, welche selbsttätig mit einem NMOS-Gate (40) ausgerichtet sind, und im Ausführen von Implantierungen des P- Polarität-Typs, welche selbsttätig mit einem PMOS-Gate (46) ausgerichtet sind, besteht.
  17. Verfahren nach Anspruch 16, wobei die Implantierungen des N+ Polarität-Typs im Implantieren von Arsen oder Phosphor in einer Dosierung zwischen 2.0E14 und 1.0E16 Atomen/cm2 und mit einer Energie zwischen 30 und 100 KeV bestehen.
  18. Verfahren nach Anspruch 16, wobei die Implantierungen des P-Polarität-Typs im Implantieren von Bor oder Indium in einer Dosierung zwischen 1.0E15 und 1.0E16 Atomen/cm2 und mit einer Energie zwischen 50 und 90 KeV bestehen.
  19. Verfahren nach Anspruch 1, wobei die Bildung von elektrischen Kontaktbereichen auf dem Widerstand (38) darin besteht, den Widerstand der Implantierung des N+ Polarität-Typs zu unterziehen, welche zur Fertigstellung der Bildung der Source- und Drain-Bereiche für die NMOS-Gate-Elektrode (40) angewandt wird, wodurch der Widerstand (38) gegen diese Einwirkung durch eine mit einem Muster versehene Schicht aus Abstandshaltermaterial (60) über dem Widerstand (38) teilweise abgeschirmt ist, wodurch Bereiche mit hoher elektrischer Leitfähigkeit in einander gegenüberliegenden Enden des Widerstands gebildet werden.
  20. Verfahren nach Anspruch 1, wobei die elektrischen Kontaktpunkte die Source- und Drain-Bereiche, eine obere (44) und eine untere (42) Platte des Kondensators, die Gate-Elektroden (40, 46) und einander gegenüberliegenden Enden des Widerstands (38) umfassen.
  21. Verfahren nach Anspruch 1, wobei die Bildung von Salicide-Schichten an elektrischen Kontaktpunkten Folgendes beinhaltet: Aufbringen einer Schicht aus reaktivem Metall wie Titan oder Cobalt über den Oberflächen, gefolgt von einem schnellen thermischen Ausglühen bei einer Temperatur zwischen 600 und 700 °C für eine Dauer zwischen 20 und 40 Sekunden und dann einem schnellen thermischen Ausglühen bei einer Temperatur zwischen 800 und 900 °C für eine Dauer zwischen 20 und 40 Sekunden.
  22. Verfahren nach Anspruch 1, mit einem ersten zusätzlichen Schritt, darin bestehend , die erste Schicht aus Dielektrikum (16) einer N+ Implantierung zu unterziehen, wobei der erste zusätzliche Schritt vor dem Aufbringen einer zweiten Schicht (24) aus Dielektrikum ausgeführt wird, wodurch die Leitfähigkeit einer unteren Platte (42) des Kondensators festgelegt wird.
  23. Verfahren nach Anspruch 22, wobei die N+ Implantierung eine Arsen- oder Phosphor-Implantierung mit einer Dotierungskonzentration zwischen 1.2E20 und 2.8E20 Atomen/cm2 mit einer Energie zwischen 30 und 100 KeV ist.
  24. Verfahren nach Anspruch 1, mit zweiten zusätzlichen Schritten, bestehend in der Bildung elektrischer Kontakte für die salicidierten elektrischen Kontaktpunkte, wobei die zweiten zusätzlichen Schritte nach dem Schritt der Bildung von Salicide-Schichten auf elektrischen Kontaktpunkten ausgeführt werden, wobei die zweiten zusätzlichen Schritte Folgendes umfassen:
    - Aufbringen einer Schicht (78) aus Interlevel-Dielektrikum (ILD) über dem Widerstand (38), den Gate-Elektroden (40, 46), dem Kondensator, salicidierten elektrischen Kontaktpunkten und freiliegenden Oberflächen der Substrat-Oberflächen-Isolierungs-Bereiche;
    - Versehen der ILD-Schicht mit einem ILD-Muster, welches zu einem Muster aus salicidierten elektrischen Kontaktpunkten passt und mit diesem ausgerichtet ist;
    - Abdecken der mit einem Muster versehenen ILD-Schicht mit einer Metallschicht:
    - Versehen der Metallschicht mit einem Muster entsprechend dem ILD-Muster, wobei das Metallmuster zumindest zu dem ILD-Muster passt und mit ihm ausgerichtet ist, wobei das Metallmuster ferner zusätzliches Abzweigen, Metall-Zwischenverbindungen und ein Fan-Out aus dem ILD-Muster schafft.
EP00480073A 1999-08-06 2000-08-05 Selbstjustierter genauer RHO Hochschicht-Widerstand für gemischte Signalanwendung Expired - Lifetime EP1075016B1 (de)

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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015611A (ja) * 1999-07-01 2001-01-19 Mitsubishi Electric Corp 半導体装置の製造方法
JP2001185628A (ja) * 1999-12-22 2001-07-06 Nec Corp 半導体装置及びその製造方法
US6548363B1 (en) * 2000-04-11 2003-04-15 Taiwan Semiconductor Manufacturing Company Method to reduce the gate induced drain leakage current in CMOS devices
US7217613B2 (en) * 2001-04-11 2007-05-15 Newport Fab, Llc Low cost fabrication of high resistivity resistors
US6830975B2 (en) * 2002-01-31 2004-12-14 Micron Technology, Inc. Method of forming field effect transistor comprising at least one of a conductive metal or metal compound in electrical connection with transistor gate semiconductor material
JP4108444B2 (ja) * 2002-10-31 2008-06-25 富士通株式会社 半導体装置の製造方法
US6727133B1 (en) * 2002-11-21 2004-04-27 Texas Instruments Incorporated Integrated circuit resistors in a high performance CMOS process
US6969646B2 (en) * 2003-02-10 2005-11-29 Chartered Semiconductor Manufacturing Ltd. Method of activating polysilicon gate structure dopants after offset spacer deposition
KR100593958B1 (ko) * 2003-11-12 2006-06-30 매그나칩 반도체 유한회사 반도체 소자의 저항 제조 방법
US6887748B1 (en) * 2004-02-10 2005-05-03 United Microelectronics Corp. Mixed-mode process
US7189635B2 (en) * 2004-09-17 2007-03-13 Hewlett-Packard Development Company, L.P. Reduction of a feature dimension in a nano-scale device
CN100409449C (zh) * 2005-04-27 2008-08-06 上海华虹Nec电子有限公司 多晶硅-绝缘层-多晶硅电容和高阻多晶硅器件的制作方法
KR100731087B1 (ko) * 2005-10-28 2007-06-22 동부일렉트로닉스 주식회사 바이씨모스 소자 및 그의 제조방법
KR100731054B1 (ko) * 2005-10-28 2007-06-22 동부일렉트로닉스 주식회사 전력용 반도체 소자 및 그의 제조방법
US7855422B2 (en) * 2006-05-31 2010-12-21 Alpha & Omega Semiconductor, Ltd. Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process
US8004060B2 (en) * 2007-11-29 2011-08-23 International Business Machines Corporation Metal gate compatible electrical antifuse
KR20100076256A (ko) * 2008-12-26 2010-07-06 주식회사 동부하이텍 Ｐｉｐ 커패시터의 제조 방법
JP5546298B2 (ja) * 2010-03-15 2014-07-09 セイコーインスツル株式会社 半導体回路装置の製造方法
KR20130086663A (ko) * 2012-01-26 2013-08-05 삼성전자주식회사 반도체 소자
KR102070094B1 (ko) * 2012-12-13 2020-01-29 삼성전자주식회사 저항 전극을 갖는 반도체 소자
CN106816433A (zh) * 2015-12-01 2017-06-09 无锡华润上华半导体有限公司 一种多晶硅高阻的制造方法
US10256233B2 (en) * 2017-05-26 2019-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Device including resistor-capacitor (RC) structure and method of making the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2705476B2 (ja) * 1992-08-07 1998-01-28 ヤマハ株式会社 半導体装置の製造方法
US5472887A (en) * 1993-11-09 1995-12-05 Texas Instruments Incorporated Method of fabricating semiconductor device having high-and low-voltage MOS transistors
US5489547A (en) * 1994-05-23 1996-02-06 Texas Instruments Incorporated Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient
US5543350A (en) * 1995-09-29 1996-08-06 Chartered Semiconductor Manufacturing Pte Ltd SRAM resistor tab doping by plug implant from buried contact
KR100209278B1 (ko) * 1995-12-30 1999-07-15 김영환 반도체 소자의 폴리레지스터 구조 및 그 제조방법
US5652174A (en) * 1996-05-20 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors
US5866451A (en) * 1996-05-28 1999-02-02 Taiwan Semiconductor Manufacturing Company Ltd Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic
US5605853A (en) * 1996-05-28 1997-02-25 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells
US5792681A (en) * 1997-01-15 1998-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication process for MOSFET devices and a reproducible capacitor structure
US5843815A (en) * 1997-01-15 1998-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a MOSFET device, for an SRAM cell, using a self-aligned ion implanted halo region
US5918119A (en) * 1997-12-08 1999-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Process for integrating MOSFET devices, comprised of different gate insulator thicknesses, with a capacitor structure
JPH11312791A (ja) * 1998-04-30 1999-11-09 Fujitsu Ltd 半導体装置の製造方法及び半導体装置

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