EP1064681A1 - Procede de production de circuits integres a l'aide de cellules standards - Google Patents

Procede de production de circuits integres a l'aide de cellules standards

Info

Publication number
EP1064681A1
EP1064681A1 EP98925416A EP98925416A EP1064681A1 EP 1064681 A1 EP1064681 A1 EP 1064681A1 EP 98925416 A EP98925416 A EP 98925416A EP 98925416 A EP98925416 A EP 98925416A EP 1064681 A1 EP1064681 A1 EP 1064681A1
Authority
EP
European Patent Office
Prior art keywords
standard cells
subsequently
cell
transistors
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98925416A
Other languages
German (de)
English (en)
Inventor
Winfried Kamp
Ronald KÜNEMUND
Eva Lackerschmid
Heinz SÖLDNER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1064681A1 publication Critical patent/EP1064681A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • FIG. 1 shows a standard cell that can be parameterized with regard to the transistor widths in comparison to a conventional one
  • FIG. 2 shows a standard cell which can be parameterized with regard to the channel length in comparison to a conventional standard cell with a fixed channel length
  • Figure 3 shows a standard cell with respect to the width
  • FIG. 4 shows two standard cells with standard cells that can be parameterized with regard to their mutual position
  • FIG. 5 shows two standard cells with parameterizable cell width for generating additional over-wiring paths (feedthrough),
  • FIG. 6 shows two standard cells with polysilicon regions which can be parameterized with regard to their length in order to produce an internal connection of regions of two standard cells with the aid of polysilicon regions,
  • FIG. 7 shows two standard cells with polysilicon regions that can be parameterized with regard to their length in order to establish an internal connection between the standard cells with an additional output number for the intermediate node and
  • FIG. 1 shows two standard cells Z and Z 'in the form of inverter circuits, the left standard cell Z having a p-channel MOS transistor T10 and an n-channel transistor T2, each with a channel area of a width covered by a gate G. W10 has.
  • An inverter input E is contacted with the gate G and one connection of each 3 transistors T10 and T2 are connected to an output A via an aluminum track.
  • Another connection of the transistor T10 is connected to an aluminum conductor for the supply voltage VSUP1 and a further connection of the transistor T2 is connected to an aluminum conductor for the supply voltage VSUP2.
  • the right standard cell Z 'from FIG. 1 differs from the left standard cell in FIG.
  • the width of the channel area covered by the gate is subsequently increased from the width W10 to the generally different widths W1 'and W2'.
  • the width of the transistor T2 could also be increased / decreased compared to the width W10 of the transistor T10.
  • the generated layout that is to say the arrangement of the individual areas for connecting tracks, contacts, oxide layers and doping areas, after the placement and wiring of the standard cells, is subsequently changed with regard to the electrical properties of the integrated circuit, such as processing speed, current yield or the like adapted before transfer to a corresponding semiconductor material, for example using a photolithographic process.
  • the word “afterwards” is to be understood accordingly in the further explanations.
  • FIG. 1 it is also indicated that, despite the parameterization of certain layout areas, even areas, here the supply voltage lines VSUP1 and VSUP2, are not adapted accordingly, but rather retain their original position and / or size if, for example, the cell height H the cell Z is subsequently increased to the cell height H 'of the cell Z'.
  • the other layout areas of a standard cell can also be adapted by parameterizing individual layout areas or that they can remain as originally specified.
  • FIG. 2 shows two standard cells in the form of inverter circuits, the left standard cell having a p-channel MOS transistor T10 and an n-channel transistor T2, each with a channel area of length L covered by a gate G.
  • An inverter input E is contacted with the gate G and one connection of the transistors T10 and T2 is connected to an output A via an aluminum track.
  • Another connection of the transistor T10 is with an aluminum conductor for the supply voltage VSUP1 and another connection of the transistor T2 is with a
  • the right standard cell of FIG. 2 differs from the left standard cell in FIG. 2 by the differently designed transistors Tl ', T2' which have a gate G 'with widened subregions over the channel areas, the widened channel area having a length L' that is greater is the length L.
  • the length of the channel region covered by the gate is subsequently increased in both transistors from the length L to the length L '.
  • FIG. 3 shows that the conductor tracks for the VSUP1 and VSUP2 for the supply voltages are subsequently widened to lines VSUP1 'and VSUP2' for supply voltages if the line resistance is too high or higher currents are required.
  • interconnects VSUP2 and VSUP2 ′′ can subsequently be connected to form a common interconnect. Furthermore, the location of the supply railways can be changed later. 5
  • the cell widths of the standard cells can be parameterized, so that the internal areas of the standard cells can move so far apart that a so-called feedthrough can be formed between adjacent gates.
  • 5 shows a left cell with a width B + B1, an inverter structure with an input E1 and an output AI, and a right standard cell with a width B + B2, an inverter structure with an input E2 and an output A2, the left cell the figure 5 on the left side is subsequently widened by B1 and the right cell on the right side by B2.
  • So-called additional feed-throughs can be implemented in this widening area
  • FIG. 6 shows two different standard cells for inverter circuits lying directly next to one another, a polysilicon region LOCCON1 being provided at the output of the first inverter circuit and a polysilicon region LOCCON2 at the input of the second standard cell, and both polysilicon regions being variable in length are, whereby a local connection between the first and second standard cell and thus a series connection of two inverters can be subsequently established.
  • the channel width W1 for the transistor T1 and the width W2 for the transistor T2 or the width W1 'for the transistor T1' 'and the width W2' for the transistor T2 subsequently differ in size within a respective standard cell can be chosen. This means that the transistor widths within a standard cell and with different standard cells can be selected differently from one another.
  • FIG. 7 not only a polysilicon connection, as in FIG. 6, but also a direct contacting of the intermediate node is realized.
  • the polysilicon areas that can be subsequently parameterized in length are in this 6 sem case with LOCCON1 'and L0CC0N2' and the additional Viahole of the intermediate node with AZ.
  • an aluminum connection area L0CC0N1 '' is provided in a left standard cell, which immediately adjoins a right standard cell at the output of the inverter of the first standard cell, and an aluminum area L0CC0N2 '' is provided at the input of the inverter of the left standard cell, both in their Length can be parameterized in such a way that a connection is subsequently established locally between the output of the first inverter and the input of the second inverter, that is to say a series connection of inverters afterwards. As shown by way of example in FIG.
  • an output contact can be dispensed with and an aluminum conductor path between the transistors T1 and T2 can directly adjoin the connection area LOCCON1 '' and in the second standard cell, for example, the aluminum area LOCCON2 '' with the input contacting of the inverter of the right standard cell be contacted.
  • the local connecting elements can thus, for example, effect a series connection of gates after placement and wiring at the local level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé selon lequel, après la mise en place et le câblage des cellules standards, il est également procédé à la définition de paramètres de conception des cellules standards. Il est, par exemple, possible de procéder à des modifications locales d'agencement et même de réaliser des connexions locales entre les cellules standards, et il est également possible d'avoir une absorption minimale de la perte de puissance, étant donné que de cette façon les exigences relatives à la vitesse, concernant le circuit intégré, peuvent être remplies avec précision.
EP98925416A 1998-03-20 1998-03-20 Procede de production de circuits integres a l'aide de cellules standards Withdrawn EP1064681A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE1998/000820 WO1999049515A1 (fr) 1998-03-20 1998-03-20 Procede de production de circuits integres a l'aide de cellules standards

Publications (1)

Publication Number Publication Date
EP1064681A1 true EP1064681A1 (fr) 2001-01-03

Family

ID=6918625

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98925416A Withdrawn EP1064681A1 (fr) 1998-03-20 1998-03-20 Procede de production de circuits integres a l'aide de cellules standards

Country Status (3)

Country Link
EP (1) EP1064681A1 (fr)
JP (1) JP2002508593A (fr)
WO (1) WO1999049515A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4537869B2 (ja) 2005-03-11 2010-09-08 株式会社東芝 半導体集積回路の設計装置及び自動設計方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575745A (en) * 1983-06-21 1986-03-11 Rca Corporation Tailorable standard cells and method for tailoring the performance of IC designs
JP2573414B2 (ja) * 1990-11-21 1997-01-22 株式会社東芝 半導体集積回路製造方法
JPH06140505A (ja) * 1992-10-28 1994-05-20 Mitsubishi Electric Corp 半導体集積回路装置
US5689432A (en) * 1995-01-17 1997-11-18 Motorola, Inc. Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method
US5619420A (en) * 1995-05-04 1997-04-08 Lsi Logic Corporation Semiconductor cell having a variable transistor width

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9949515A1 *

Also Published As

Publication number Publication date
JP2002508593A (ja) 2002-03-19
WO1999049515A1 (fr) 1999-09-30

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