EP0941517A1 - Installation assurant le fonctionnemnt d'une carte a puce et l'echange de donnees entre une carte a puce et un syteme assiste par microprocesseur - Google Patents

Installation assurant le fonctionnemnt d'une carte a puce et l'echange de donnees entre une carte a puce et un syteme assiste par microprocesseur

Info

Publication number
EP0941517A1
EP0941517A1 EP98954213A EP98954213A EP0941517A1 EP 0941517 A1 EP0941517 A1 EP 0941517A1 EP 98954213 A EP98954213 A EP 98954213A EP 98954213 A EP98954213 A EP 98954213A EP 0941517 A1 EP0941517 A1 EP 0941517A1
Authority
EP
European Patent Office
Prior art keywords
microprocessor
chip card
based system
circuit
card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98954213A
Other languages
German (de)
English (en)
Inventor
Jürgen VELSEN
Rainer Neumann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SC ITEC GmbH
Original Assignee
Orga Kartensysteme GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orga Kartensysteme GmbH filed Critical Orga Kartensysteme GmbH
Publication of EP0941517A1 publication Critical patent/EP0941517A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers

Definitions

  • the invention relates to a device for the operation of a chip card and the data exchange between a chip card and a microprocessor-based system, for example a personal computer, according to the preamble of claim 1.
  • a microprocessor-based system means any system that contains a microprocessor, that is also a system with a microcontroller or a personal computer.
  • chip cards have been widely used as bank and credit cards, identification and access authorization cards in the mobile radio sector (GSM cards, Global System of Mobile Communication), health insurance cards, telephone cards and in many other areas.
  • GSM cards Global System of Mobile Communication
  • the chip cards For communication with so-called card read / write devices, the chip cards have metallic contact surfaces on the card body, which are connected to the chip (microprocessor chip or memory chip with logic unit) in the card.
  • the card read / write device in turn now has a contacting unit with contacts which correspond to the contact areas of the chip card, the contacts and the contact areas being brought into an electrically conductive connection after the card has been inserted into the card read / write device.
  • VCC supply voltage
  • VDD reference voltage / ground
  • CLK clock frequency
  • I / O serial data exchange
  • RST reset line
  • the standards provide a contact area for the supply of a programming voltage, which, however, is no longer required for most chip cards, since the programming voltage is generated internally in the chip itself from the supply voltage. Furthermore, two contact areas are planned for future applications.
  • the data exchange between the chip card and the card reader / writer is synchronous with memory cards, while it is asynchronous with microprocessor cards.
  • the reading device has several discrete components.
  • VCC supply voltage
  • the object of the invention is to provide a device for the operation of a chip card and the data exchange between a chip card and a microprocessor-based system, which enables fast communication between the microprocessor-based system and the chip card, can be easily integrated into microprocessor-based systems and above is also inexpensive to manufacture.
  • the device is designed as a peripheral interface unit based on the microprocessor-based system, in which the following components are contained:
  • VCC supply voltage
  • the microprocessor-based system controls the chip card directly via this peripheral interface unit without the interposition of another microprocessor.
  • the device according to the invention thus represents a hardware support (hardware protocol converter) of the microprocessor-based system, with certain, time-critical processes (lower layers of the communication protocol used in each case) in communication with the chip card now no longer using software, but instead using a permanently defined (“hard-wired ”) circuit can be implemented, which only executes predetermined circuit sequences depending on certain input signals. Only not so time-critical processes (upper layer of the communication protocol) are implemented in software in the microprocessor-based system. This significantly accelerates the communication between the chip card and the microprocessor-based system .
  • the device according to the invention is much easier to integrate into a microprocessor-based system than a card write / read reader with its own microprocessor, since it is not necessary that those who have to carry out the integration and who are familiar with their own microprocessor-based system also know themselves have to work into a microprocessor type that is foreign to them.
  • a software libray for installation on the microprocessor-based system for controlling the device according to the invention Is made available.
  • This software library preferably includes various communication protocols.
  • the device according to the invention can thus be used universally for various microprocessor-based systems.
  • the device according to the invention is designed as a monolithic interface semiconductor component in the form of an application-specific, integrated circuit, a so-called ASIC (abbreviation for the expression: Application Specific Integrated Circuit).
  • ASIC abbreviation for the expression: Application Specific Integrated Circuit
  • the interface semiconductor module is preferably implemented in CMOS technology in order to ensure low power consumption.
  • the device according to the invention represents an inexpensive solution, especially in the case of large quantities.
  • the omission of the microprocessor also reduces the chip area required for the monolithic interface module, which in turn lowers costs.
  • both digital and analog circuit functions can be implemented on the monolithic interface module.
  • An analog circuit for generating and controlling the supply voltage for the chip card is also provided on the monolithic semiconductor module.
  • only a purely digital circuit for controlling the supply voltage, which is implemented externally by an analog circuit, is also provided.
  • the device according to the invention is intended, for example, for installation in card-writing Z-readers which are connected to a microprocessor-based system, or for installation in portable, microprocessor-based terminals which include a card input slot and a contacting unit, for example mobile card readers for health insurance cards, where the card contains them Microprocessor ZControUer on the one hand the device according to the invention communicates with the chip card and on the other hand in the
  • the microprocessor-based system (2) is preferably connected via a parallel, bidirectional interface to the device (30) according to the invention, preferably in the form of a monolithic interface semiconductor module, which is located in the card write / read device (3); for this purpose there is a multi-core interface cable (20) between the microprocessor-based system (2) and the card write / read device (3).
  • the device (30) according to the invention there is a quartz oscillator (32) and a power supply unit (33, power pack, battery or a rechargeable accumulator) in the card writing / reading device (3).
  • a circuit (30A) for communication with the microprocessor-based system (2) and a circuit (30B) for communication with the chip card (1) are integrated in the monolithic interface semiconductor module (30), and this communication is carried out in accordance with the microprocessor-based system ( 2) Data received and control instructions enabled.
  • a circuit (30D) for generating the supply voltage (VCC) for the chip card (1) and a circuit (30C) for generating the clock signal (CLK) for the chip card (1) are integrated in the monolithic interface semiconductor module (30) .
  • the circuit (30A) in one embodiment includes a parallel, bidirectional interface.
  • the circuit (30A) comprises a buffer memory area, in particular one based on the First In First Out (FIFO) principle, for the temporary storage of data and control instructions. This prevents data loss and creates reliable operation even when the microprocessor-based system is busy with other things.
  • FIFO First In First Out
  • Such an interface is known to experts under the abbreviation ECP (Extended Capability Port, according to the IEEE1284 standard) and has meanwhile become a standard.
  • the circuit (30A) comprises a so-called ⁇ P bus interface.
  • both the above-mentioned ECP and the ⁇ P bus interface are integrated in the device (30) according to the invention.
  • the selected interface operating mode is then selected via the control line S 0 (see FIGS. 2 and 3).
  • the interface module (30) is reconfigured to support the selected operating mode, the functionality of the control lines (S, S *) changing.
  • FIGS. 3A and 3B the time status diagram for the control Z signal lines (S, S *) for the case of write access of the microprocessor-based system (2) to the interface module (30) is shown in each case in FIGS. 3A and 3B.
  • a parallel interface of the microprocessor-based system (2) can be connected to several of the interface units (30) according to the invention.
  • a specific interface unit (30) is then selected using an identification number (so-called device ED).
  • the circuit (30 A) comprises a serial interface.
  • FIG. 2 shows a more detailed illustration of the interface unit (30) according to the invention.
  • This comprises a control unit which can be reconfigured depending on the interface operating mode and which regulates the communication with the microprocessor-based system (2).
  • an address register is used to select which register (timer, interrupt mask register, interrupt register, status register, control register, mode register) is to be read or written by the microprocessor-based system.
  • registers are in turn connected to a UART (Universal Asynchronus ReceiverZTransmitter) connected, which carries out the parallel / serial conversion of the data from and to the chip card.
  • This UART preferably has a circuit for error detection with regard to the data bits to be exchanged using a parity bit.
  • Events are stored in the interrupt register that should be able to trigger an interrupt; for example, an excess of the current on the Vcc line to the chip card or the fact whether a card is inserted or removed.
  • Masking in the interrupt mask register can be used to determine which of the interrupt registers are actually used for interrupts.
  • the status of the supply line (VCC) to the chip card (1) or the occurrence of a parity error during data transmission are stored in the status register.
  • control register for example, the convention of data transmission with regard to the assignment of the logical states (1,0) to the voltage levels (high, praise) is defined.
  • the card clock generator generates the clock signal for the chip card (CLK) from the externally applied clock of a quartz oscillator (32). For this purpose, the frequency of the clock supplied by the quartz oscillator (32) is divided.
  • the device (30) according to the invention provides the numbers 2 to 31 as division factors.
  • the permissible range for the clock of the oscillating quartz oscillator (32) supplied from the outside is 1 MHz to 32 MHz; a typical value is 29.4 MHz.
  • the device (30) according to the invention is thus very flexible with regard to the variation of the frequency of the clock signal (CLK) for the chip card (1). For example, with a quartz oscillator (32) with 29.4 MHz and a division factor of 8, there is a frequency for the chip card clock signal (CLK) of 3,675 MHz.
  • the data transfer rate for data transfer to and from the chip card (1) is now derived from the chip card clock signal (CLK) and the associated frequency, which, as explained above, can also be programmed with the device (30) according to the invention.
  • CLK chip card clock signal
  • a microprocessor chip card (1) in turn contains a division factor which indicates the number of clock cycles (CLK) per bit, which results in the time duration for one bit (elementary time unit, etu).
  • the device (30) according to the invention is now even in able to support chip cards (1) that contain more than one division factor for generating different transmission rates (corresponds to different ETUs).
  • the chip card (1) informs the interface module which division factors are possible.
  • the chip card (1) and the interface module (30) agree on a common division factor, preferably the smallest possible factor, which consequently provides the highest transmission rate.
  • the interface module (30) supports the division factors from 1 to 2047.
  • the division factor 372 is activated, since this also sends the ATR from the chip card (1), in which it only tells what other division factors are possible.
  • the device (30) according to the invention is thus also very flexible with regard to the possible transmission rates.
  • the chip card clock (CLK) and the data transmission on the I / O line (setting the corresponding levels) are effected directly via the signal register, for which purpose the multiplexers M1 and M2 are switched accordingly.
  • the device (30) has an I / O line for sending (I / O-TXD, transmit data) and one for receiving (I / O-RXD, receive data).
  • a driver is provided for each direction, so that data transmission over longer distances is also possible.
  • these are then combined again as an I / O contact for the chip card (1)
  • the signal register also generates the reset (RST) signal for the chip card (1) and a signal (Out) that is still free for use (e.g. an LED could be activated to indicate whether a card is inserted).
  • RST reset
  • Out signal that is still free for use (e.g. an LED could be activated to indicate whether a card is inserted).
  • the timer which - either adjustable via the M 3 multiplexer - counts either the card clock (CLK) or the ETU clock, generates a time-out signal for a waiting time between data strings.
  • the voltage regulator generates the supply voltage (VCC) for the chip card (1) from an external supply voltage (V). It is designed so that it can optionally generate at least two different supply voltages (VCC) to support different cards (3V cards, 5V cards). When switching from one supply voltage to another, the levels for the I / O line are also automatically adjusted.
  • a power control and switch-off unit which monitors the supply current to the chip card (on the VCC line) and, if exceeded, the signals (VCC, I / O, CLK, RST) in a defined sequence to defined levels sets - shutdown sequence (see Fig. 4B).
  • the limit is 15 mA.
  • an external transistor circuit must be provided for the device (30) according to the invention.
  • the switch-off sequence is also triggered when the chip card (1) is withdrawn, which is determined via a card-in contact in the contacting unit (31).
  • the shutdown sequence is triggered each time the device (30) according to the invention is reset.
  • the shutdown sequence is started after a response time of typically 100 ⁇ s after the triggering event.
  • a delay counter is provided to determine the response time.
  • the response time of 100 ⁇ s allows the card to be brought into a defined state, for example in the case of a card that was incorrectly removed during communication.
  • the switch-on sequence takes place under software control of the microprocessor-based system.
  • the device (30) according to the invention is able to generate signals on the lines (I / O, RST, CLK) with a very low, defined maximum edge limitation: 100ns for RST and I / O and 10 nS for CLK.
  • the connections (I / O, VCC, RST, CLK) are designed to be high-voltage safe by means of internal circuits, so that static charges on an inserted chip card (1) do not damage the device according to the invention.

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  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Microcomputers (AREA)

Abstract

La présente invention porte sur une installation assurant le fonctionnement d'une carte à puce et l'échange de données entre une carte à puce et un système assisté par microprocesseur. Cette installation permet l'activation de ladite carte à puce grâce au système assisté par microprocesseur sans nécessiter l'interconnexion d'un autre microprocesseur.
EP98954213A 1997-09-26 1998-09-22 Installation assurant le fonctionnemnt d'une carte a puce et l'echange de donnees entre une carte a puce et un syteme assiste par microprocesseur Withdrawn EP0941517A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19742459 1997-09-26
DE19742459A DE19742459C2 (de) 1997-09-26 1997-09-26 Einrichtung für den Betrieb einer Chipkarte und den Datenaustausch zwischen einer Chipkarte und einem mikroprozessorgestützten System
PCT/DE1998/002805 WO1999017247A1 (fr) 1997-09-26 1998-09-22 Installation assurant le fonctionnemnt d'une carte a puce et l'echange de donnees entre une carte a puce et un syteme assiste par microprocesseur

Publications (1)

Publication Number Publication Date
EP0941517A1 true EP0941517A1 (fr) 1999-09-15

Family

ID=7843670

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98954213A Withdrawn EP0941517A1 (fr) 1997-09-26 1998-09-22 Installation assurant le fonctionnemnt d'une carte a puce et l'echange de donnees entre une carte a puce et un syteme assiste par microprocesseur

Country Status (4)

Country Link
US (1) US6520416B1 (fr)
EP (1) EP0941517A1 (fr)
DE (1) DE19742459C2 (fr)
WO (1) WO1999017247A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10011554A1 (de) * 2000-03-09 2001-09-13 Techno Team Bildverarbeitung G Verfahren und Anordnung zur Kopplung eines digitalen Signalprozessors (DSP) mit einem Personalcomputer
GB0027810D0 (en) * 2000-11-15 2000-12-27 Pace Micro Tech Plc Signal sequencing control means
EP1503559A1 (fr) * 2003-07-28 2005-02-02 Canal + Technologies Procédé de détection automatique de protocole de transmission pour objet portable de type carte à puce ou clé à puce
US7792122B2 (en) 2003-07-28 2010-09-07 Nagra Thomson Licensing Transmission protocol automatic detection method for a portable object such as a chip card or a chip key
DE102004009349A1 (de) * 2004-02-26 2005-09-15 Giesecke & Devrient Gmbh System mit einem mobilen Datenträger und einem Endgerät
DE102004023903A1 (de) * 2004-05-13 2005-12-29 Giesecke & Devrient Gmbh System bestehend aus einem tragbaren Datenträger und einer Leseeinrichtung
DE102004049671B4 (de) 2004-10-12 2007-08-02 Mühlbauer Ag Elektronisches Modul für die Herstellung, Programmierung und das Testen von Chipkarten und zugehöriges Verfahren
CN117851306B (zh) * 2024-03-06 2024-05-31 牛芯半导体(深圳)有限公司 一种运行模式的确定方法、芯片、芯片模组及存储介质

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JPS62229491A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 携帯可能記録媒体の読取り／書込み装置
US6089459A (en) * 1992-06-16 2000-07-18 Smartdiskette Gmbh Smart diskette device adaptable to receive electronic medium
JPH06177940A (ja) * 1992-12-08 1994-06-24 Mitsubishi Electric Corp Ｕａｒｔおよびこれを用いたシステム
FR2723224B1 (fr) * 1994-07-28 1996-09-06 Sgs Thomson Microelectronics Systeme lecteur de carte a memoire ou a puce
JP3540414B2 (ja) * 1995-02-20 2004-07-07 株式会社東芝 Ｉｃカードリーダライタ
US5679945A (en) * 1995-03-31 1997-10-21 Cybermark, L.L.C. Intelligent card reader having emulation features
DE19522527A1 (de) * 1995-06-23 1997-01-02 Ibm Verfahren zur Vereinfachung der Kommunikation mit Chipkarten
US5815426A (en) * 1996-08-13 1998-09-29 Nexcom Technology, Inc. Adapter for interfacing an insertable/removable digital memory apparatus to a host data part

Non-Patent Citations (1)

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Title
See references of WO9917247A1 *

Also Published As

Publication number Publication date
DE19742459C2 (de) 2000-02-03
WO1999017247A1 (fr) 1999-04-08
US6520416B1 (en) 2003-02-18
DE19742459A1 (de) 1999-04-08

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