EP0932328B1 - Substrat pour monter un element electronique et procede pour le fabriquer - Google Patents

Substrat pour monter un element electronique et procede pour le fabriquer Download PDF

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Publication number
EP0932328B1
EP0932328B1 EP96941888A EP96941888A EP0932328B1 EP 0932328 B1 EP0932328 B1 EP 0932328B1 EP 96941888 A EP96941888 A EP 96941888A EP 96941888 A EP96941888 A EP 96941888A EP 0932328 B1 EP0932328 B1 EP 0932328B1
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EP
European Patent Office
Prior art keywords
patterns
mount opening
opening portion
portions
electronic parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96941888A
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German (de)
English (en)
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EP0932328A1 (fr
EP0932328A4 (fr
Inventor
Naoto-Ibiden Co. Ltd. ISHIDA
Teruo-Ibiden Co. Ltd. HAYASHI
Kiyotaka-Ibiden Co. Ltd. TSUKADA
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Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
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Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to EP03010873A priority Critical patent/EP1351296B1/fr
Publication of EP0932328A1 publication Critical patent/EP0932328A1/fr
Publication of EP0932328A4 publication Critical patent/EP0932328A4/fr
Application granted granted Critical
Publication of EP0932328B1 publication Critical patent/EP0932328B1/fr
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Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.

Definitions

  • the present invention relates to an electronic parts mounting substrate in which side-surface patterns having a plurality of potentials are disposed on wall surfaces of a mount opening portion for mounting the electronic parts, and a method of manufacturing same.
  • an electronic parts mounting substrate having a mount opening portion 95 at which electronic parts 8 are mounted Japanese Patent Application JP-A-7 086 752
  • a plurality of side-surface patterns 901 are disposed on wall surfaces of the mount opening portion 95.
  • the side-surface patterns 901 are connected to wiring patterns 53 formed inside of the electronic parts mounting substrate 9.
  • the electronic parts 8 mounted at the mount opening portion 95 are electrically connected to band-like side-surface pads 903, disposed above the side-surface patterns 901, through bonding wires 80.
  • wiring patterns 54 are disposed on an upper surface of the electronic parts mounting substrate 9.
  • the wiring patterns 54 are connected to through-holes 99 provided in the periphery of the electronic parts mounting substrate 9.
  • a lead pin 86 is installed inside each of the through-holes 99.
  • cut holes 90 having side-surface pattern formation portions as wall surfaces are first formed in an insulating substrate 92, which is an upper layer of the electronic parts mounting substrate, as shown in Fig. 28.
  • the cut holes 90 are arranged in such a manner that they surround, in the form of a square, the peripheral edges of a mount opening portion formation portion 909 on the insulating substrate 92.
  • a metal plating film 902 is coated on each wall surface of the cut holes 90, and the band-like side-surface pads 903, the wiring patterns 54 and the bonding pads 540 are formed on the upper surface of the insulating substrate 92.
  • insulating substrate 91 is laminated and crimped on the bottom surface of the above mentioned insulating substrate 92 to obtain a multi-layer plate 98.
  • the through-holes 99 are formed in the peripheral edge of the multi-layer plate 98, and their interiors are coated with the metal plating film 909.
  • a lead pin 86 is installed inside of each of the through-holes 99. Accordingly, the electronic parts mounting substrate 9 shown in Fig. 27 is obtained.
  • the metal plating film 902 at each of the ends of the above side-surface patterns 901 covering on the wall surfaces 919 of the mount opening portion will be drawn and peeled off from the wall surfaces by the blade of the router machining tool.
  • the metal plating film 902 will further peel off from the portions of the wall surfaces from which the metal plating film 902 has already peeled off when there is a thermal shock, resulting in a risk that reliable electric conductivity of the side-surface patterns will be interrupted. Consequently, the router machining must be conducted gradually with high accuracy, and since the router machining rate cannot be increased, productivity is lowered.
  • each of the wall surfaces of the mount opening portion 95 be punched at a predetermined portion to form a punched portion 912, and the side-surface pattern 901 be formed between the respective punched portions 912.
  • side-surface patterns 901 having various potentials such as a power supply circuit P, a grounding circuit G or a signal circuit S can be formed.
  • the side-surface patterns 901 can function as the power supply circuit P, the grounding circuit G or the signal circuit S.
  • the end portion 902 of the side-surface pattern 901 may peel off when the mount opening portion 95 is punched.
  • the present invention has been made in view of the above problems with the prior art, and therefore an object of the present invention is to provide an electronic parts mounting substrate and a method of manufacturing the substrate, which are capable of preventing the side-surface pattern from peeling-off and facilitate the formation of the side-surface patterns having a plurality of potentials.
  • a first means for solving the problems is directed to an electronic parts mounting substrate as set out in Claim 1. projection portions.
  • An electronic parts mounting substrate therefore has projection portions that project toward the interior of the mount opening portion from the wall surfaces thereof.
  • the end portions of the respective side surfaces extend to the side surfaces of the projection portions.
  • the projection portion is designed such that the length between its base portion and an inside end portion is 0.1 to 0.5 mm. This enables the peeling-off of the side-surface pattern to be more effectively prevented. Also, there is no risk that the projection portion would become an obstacle when the electronic parts are mounted on the substrate. If the length is less than 0.1 mm, there is a risk that the side-surface pattern would be peeled off, while there is a risk that the projection portion would become an obstacle if the length exceeds 0.5 mm.
  • the base portion of the above projection portion means a position on a straight line connecting a pair of corners which are boundaries between the side surface of the projection portion and the wall surface of the mount opening portion.
  • the inner end of the above mount opening portion means the inner surface of the mount opening portion which faces the interior of the mount opening portion, and no metal plating film is coated on the inner surface of the mount opening portion.
  • the invention also provides a method of manufacturing the above electronic parts mounting substrate as set out in Claim 3.
  • the cutting can be made with a router machining tool without damaging the metal plating film that covers the wall surfaces of the mount opening portion, and the cutting is facilitated. Therefore, the electronic parts mounting substrate can be readily formed without damaging the side-surface patterns.
  • the projection portions remaining when the router machining is performed are preferably designed such that a length between their base portion and their inner end is 0.1 to 0.5 mm.
  • an electronic parts mounting substrate 3 of this example includes insulating substrates 31 and 32, a mount opening portion 2 for mounting electronic parts 8 thereat, and a plurality of side-surface patterns 11 and 12 provided on the wall surfaces of the mount opening portion 2.
  • a length L of the projection portion 21 extending from a base portion 215 to an inner end 212 is 0.5 mm.
  • the side-surface pattern 11 and the side-surface pattern 12 are alternately disposed on the wall surfaces of the mount opening portion 2 as shown in Fig. 1.
  • the side-surface pattern 11 is a power supply circuit that supplies electricity to the electronic parts
  • the side-surface pattern 12 is grounding circuit for grounding the electronic parts.
  • the side-surface patterns 11 and 12 are connected thereof at upper portions to band-like side-surface pads 71 and 72 that surround the mount opening portion 2.
  • the grounded side-surface pattern 12 is connected to a grounded wiring pattern 79 disposed between the insulating substrates 31 and 32 at a lower portion thereof.
  • the power supply side-surface pattern 11 is connected to a power supply wiring pattern (omitted in the figure) disposed between the insulating substrates 31 and 32.
  • a signal wiring pattern 76 and a bonding pad 760 disposed at an end of the wiring pattern 76 are provided as shown in Fig. 1.
  • the wiring pattern 76 is connected to through-holes 39 that pass through the electronic parts mounting substrate 3. Inside of the through-hole 39 is disposed, for example, a lead pin 86 as shown in Fig. 2.
  • the electronic parts 8 mounted at the mount opening portion 2 are electrically connected to the side-surface pads 71, 72 and the bonding pad 760 through bonding wires 80.
  • the insulating substrate to be used is a glass epoxy resin substrate, a glass polyimide resin substrate, a glass bismaleimidotriazine resin substrate or the like.
  • a plurality of partition holes 201 that have the side-surface pattern formation portions as portions of the wall surfaces are formed in the mount opening portion formation portion of the insulating substrate 32 which will form the upper layer by deforming the respective partition holes 201 with partition walls 210 by router machining or a punching process.
  • the partition holes 201 are sectioned into four holes with the cross-shaped partition walls 210 which are transverse to the mount opening portion formation portion.
  • Each of the partition holes 201 is triangular with the side-surface pattern formation portion as one side, and one corner thereof opposite a center portion 219 of the partition wall 210.
  • a metal plating film 10 made of copper is coated on the walls surface of the above partition holes 201.
  • the partition walls 210 of the partition holes 201 is cut off along a dotted line 200 as shown in Figs. 3 and 4 by router machining.
  • portions of the partition walls 210 remain so as to form the projection portions 21 that project toward the interior of the mount opening portion 2.
  • the mount opening portion 2 and a plurality of the side-surface patterns 11 and 12 are formed on the wall surfaces of the mount opening portion 2.
  • the electronic parts mounting substrate 3 of this example has the projection portions 21 that project toward the interior of the mount opening portion 2 at both ends of the side-surface patterns 11 and 12.
  • the metal plating films 10 that are the end portions of the respective side-surface patterns 11 and 12 extend to the side surfaces of each the projection portions 21.
  • the highly accurate router machining is not required. Also, because the router machining is performed at a position away from the wall surfaces of the mount opening portion 2 in such a manner that portions of the partition walls between the partition holes 201 remain, the cutting process can be performed without damaging the metal plating film 10 that coats the wall surfaces of the mount opening portion with the blade of the router machining tool.
  • An electronic parts mounting substrate of this example includes not only projection portions 21 that project from the corners 218 of the mount opening portion 2, but also projection portions 22 that project at a right angle from the plane portions 29 of the mount opening portion 2 as shown in Fig. 6.
  • the power supply side-surface patterns 11 and the grounded side-surface patterns 12 are alternately disposed between the respective projection portions 21 and 22.
  • the band-like side-surface pads 71 and 72 are disposed on the upper surface of the insulating substrate 32 which is situated above the respective side-surface patterns 11 and 12, and the wiring patterns are disposed on the lower surface of the insulating substrate 32 which is situated below the respective side-surface patterns 11 and 12.
  • a plurality of partition holes 202 and 203 having the side-surface pattern formation portions as a part of the wall surfaces are formed by router machining or a punching process in the mount opening portion formation portion of the insulating substrate 32 which will form the upper layer.
  • the partition holes 202 and 203 are formed in the peripheral portion of the mount opening portion formation portion.
  • the partition holes 202 are triangular, and two partition holes 202 are formed at each of the four corners of the mount opening portion formation portion so as to sandwich the partition walls 211.
  • the partition holes 203 are rectangular, and two partition holes 203 are formed at each of the plane portions 29 of the mount opening portion formation portion so as to sandwich the partition walls 213.
  • the partition walls 211 and 213 are connected to the center portion 230 of the mount opening portion formation portion.
  • partition walls 211 and 213 of the above-mentioned partition holes are cut off along dotted line 200 shown in Fig. 7 by router machining.
  • the projection portions 21 and 22 that project toward the interior of the mount opening portion 2 are formed in such a manner that portions of partition walls 211 and 213 remain.
  • the projection portions 21 and 22 are designed such that the lengths of the projection portions 21 and 22 extending from the base to the inner end thereof are set to 0.5 mm and 0.3 mm, respectively.
  • the mount opening portion 2 is formed, and a plurality of the side-surface patterns 11 and 12 having the projection portions 21 and/or 22 at both ends thereof are formed.
  • An electronic parts mounting substrate of this example includes a plurality of projection portions 22 that project at a right angle from the plane portions 29 of the wall surfaces of the mount opening portion 2 as shown in Fig. 8.
  • the power supply side-surface patterns 11 and the grounded side-surface patterns 12 are alternately disposed between the respective projection portions 22.
  • the band-like side-surface pads 71 and 72 are disposed on the upper surface of the insulating substrate 32 which is situated above the respective side-surface patterns 11 and 12, and the wiring patterns are disposed on the lower surface of the insulating substrate 32 which is situated below the respective side-surface patterns 11 and 12.
  • a large hole 205 that opens the entire mount opening portion formation portion is formed in the mount opening portion formation portion of the insulating substrate 32, which will form the upper layer, by router machining or a punching process.
  • the large hole 205 includes wavy irregular portions 207 at its periphery.
  • a plurality of convex portions 222 project from the insulating substrate 32 at right angles at the irregular portion 207.
  • the convex portions 222 are cut off along a dotted line 200 shown in Fig. 9 by router machining.
  • the projection portions 22 that project toward the interior of the mount opening portion 2 are formed in such a manner that portions of the convex portions 222 remain.
  • the mount opening portion 2 is formed, and a plurality of the side-surface patterns 11 and 12 are formed.
  • An electronic parts mounting substrate 30 includes, as shown in Fig. 10, an insulating substrate 7 having a mount opening portion 73 for mounting electronic parts thereat and a plurality of side-surface patterns 51 disposed on the wall surfaces of the mount opening portion 73.
  • the side-surface patterns 51 are formed by etching side-surface pattern non-formation portions of a conductive layer 5 formed on the wall surfaces of the mount opening portion 73 in a state where the side-surface pattern formation portions are coated.
  • the respective side-surface patterns 51 are insulated from each other by exposed surfaces 731 provided between the patterns where portions of the insulating substrate 7 are exposed by etching.
  • the side-surfacepatterns 51 are disposed on substantially the same plane as the exposed surface 731 between the patterns.
  • the upper and lower end portions 511 of the side-surface patterns 51 are connected to side-surface pads 52 along the end portions thereof.
  • the side end portions of each of the side-surface pads 52 has a tapered portion 521 which expands from the edge portion 730 of the mount opening portion 73 toward the exterior of the mount opening portion 73.
  • the respective side-surface pads 52 are insulated from each other by the exposed surfaces 732 between the pads, which is nearly triangular, with the tapered portion 521 as one side.
  • a pitch A of the side-surface pattern 51 is set to 0.54 mm.
  • a clearance B between the adjacent side-surface patterns 51 is set to 0.2 mm.
  • a width C of the side-surface pad 52 is set to 100 to 150 m. When the width C is smaller than 100 m, there is a risk that the side-surface pad will be difficult to form. When the width C exceeds 150 m, there is a risk that bonding pads 550 of the wiring patterns 55 will be damaged.
  • the wiring patterns 55 and 56 are formed on the upper surface and the lower surface of the insulating substrate 7, respectively.
  • each of the wiring patterns 55 formed on the upper surface of the insulating substrate 7 has a bonding pad 550 in the periphery of the mount opening portion 73.
  • the wiring patterns 56 formed on the lower surface of the insulating substrate 7 is a wide flat layer and is connected to the side-surface patterns 51 shown in Fig. 10.
  • the side-surface pattern 51 is connected to the side-surface pad 52 and the bonding pad 520 provided on the upper surface of the insulating substrate 7.
  • the wiring patterns 55 and the bonding pads 550 formed on the upper surface of the insulating substrate 7 are made up of signal circuits S1, S2, ... Sx with different potentials (x indicates the number of signal circuits, and applies hereinafter).
  • the wiring patterns 56 formed on the lower surface of the insulating substrate 7 are made up of power supply circuits P1, P2, ... Py with different potentials (y indicates the number of power supply circuits, and applies hereinafter), and grounded circuits G1, G2, ... Gz (z indicates the number of grounded circuits, and applies hereinafter).
  • the side-surface patterns 51 connected to those wiring patterns 56 are made up of the power supply circuits P1, P2, ... Py and the grounded circuits G1, G2, ... Gz which correspond to the respective wiring patterns.
  • the side-surface pads 52 and the bonding pads 520 which are connected to the respective side-surface patterns are also made up of circuits of the same type.
  • a plurality of insulating substrates 7 are laminated to form an electronic parts mounting substrate 30 with a multi-layer structure.
  • an insulating substrate formed of a glass bismaleimidotriazine substrate is prepared.
  • the mount opening portion 73 is opened in the insulating substrate 7 by router machining.
  • through-holes 78 are opened in the vicinity of the peripheral edge of the insulating substrate 7.
  • the insulating substrate 7 is subjected to an electroless copper plating process to form the conductive layer 5 on the entire surface of the insulating substrate 7 including the interior of the mount opening portion 73.
  • the entire surface of the conductive layer 5 is coated with a side-surface pattern resist film 6 made of a negative photosensitive resin by an electrodeposition coating process.
  • a side-surface pattern mask 40 is mounted on the upper surface and the lower surface of the insulating substrate 7.
  • the side-surface pattern mask 40 has slits 41 for exposing the side-surface pattern non-formation portions at portions where the mount opening portion 73 of the insulating substrate 7 is coated.
  • the slit 41 is made up of, as shown in Fig. 18, a wall-surface exposure portion 411 for exposing the side-surface pattern non-formation portion and a peripheral edge exposure portion 412 for exposing the side-surface pad non-formation portion.
  • the wall-surface exposure portion 411 is open in the interior of the mount opening portion 73 so that an exposure light reaches the lower edge portion 730 of the mount opening portion 73 from the upper edge portion 730 thereof.
  • the peripheral edge exposure portion 412 is open at the side-surface pad non-formation portion in the vicinity of the edge portion 730 of the mount opening portion 73.
  • the peripheral edge exposure portion 412 is defined by a portion surrounded by the edge portion 730 of the mount opening portion 73 and an oblique side which is reduced from the edge portion 730 toward the exterior of the mount opening portion 73, and has a triangular shape.
  • the side-surface pattern non-formation portion of the side-surface pattern resist film 6 is exposed by a scattered light 4 which is scattered in all directions.
  • the scattered light 4 is reflected by the side-surface pattern resist film 6 on the insulating substrate surface at various angles after passing through the slit 41 so as to be irradiated on the wall surfaces of the mount opening portion 73 and its periphery.
  • the scattered light 4 is uniformly irradiated onto the side-surface pattern non-formation portion of the side-surface pattern resist film 6 from the upper edge portion 730 of the mount opening portion 73 to the lower edge portion 730. Also, the scattered light 4 is uniformly irradiated on the side-surface pattern resist film 6 in the vicinity of the edge portion 730 of the mount opening portion 73. As a result, a portion of the side-surface pattern resist film 6 on which the scattered light 4 is irradiated is sensitized, and removably dissolved by development.
  • the side-surface pattern resist film 6 is developed to remove the side-surface pattern non-formation portion and the side-surface pad non-formation portion.
  • the conductive layer 5, exposed from the side-surface pattern resist film 6, is removed by etching.
  • the exposed surfaces 731 between the patterns where portions of the insulating substrate 7 are exposed are formed on the wall surfaces of the mount opening portion 73.
  • the exposed surfaces 732 between the pads which have a triangular shape that narrows toward the exterior of the mount opening portion 73, are formed in the vicinity of the opening portion 730 of the mount opening portion 73 so as to be continuous with the exposed surfaces 731 provided between the above-mentioned patterns.
  • the side-surface pattern resist film 6 which remains on the surface of the conductive layer 5 is removed with an alkali solution.
  • the side-surface patterns 51 insulated from each other by the exposed surfaces 731 between the patterns of the mount opening portion 73 are formed on substantially the same plane as the exposed surfaces 731 between the patterns.
  • a portion surrounded by the tapered portion 521 which will form the side end portion of the side-surface pad is exposed on the upper surface and the lower surface of the insulating substrate 7.
  • the entirety of upper and lower surfaces of the insulating substrate 7 are coated with the conductive layer 5 as they are, except for the exposed surfaces 732 between the pads which are formed between the tapered portions 521.
  • the wiring pattern masks 31 and 32 for forming the wiring patterns and the side-surface pads are mounted on the upper surface and the lower surfaces of the insulating substate 7 so as to be coated on the wiring pattern formation portion and the mount opening portion 73.
  • the portions of the conductive layer 5 which are exposed from the wiring pattern masks 31 and 32 are removed by etching. Subsequently, the wiring pattern masks 31 and 32 are removed. As a result, as shown in Figs. 10 to 13, the side-surface pads 52 continuous with the upper and lower end portions 511 of the above-mentioned side-surface patterns 51, and the wiring patterns 55, 56 are formed on the upper surface and the lower surface of the insulating substrate 7.
  • a plurality of the above-described insulating substrates 7 are laminated and crimped to obtain a multi-layer electronic parts mounting substrate 30.
  • the side-surface patterns are formed, as shown in Fig. 21, by etching the side-surface pattern non-formation portions of the conductive layer 5 formed on the wall surfaces of the mount opening portion 73 in a state where the side-surface pattern formation portions are coated with the side-surface pattern resist film 6. Therefore, if the pattern width of the side-surface pattern resist film 6 is narrowed, the clearances between the side-surface patterns can be narrowed to about 0. 2 mm. Consequently, as shown in Fig. 10, more side-surface patterns 51 than in the embodiment 1 can be formed.
  • various wiring patterns 51 with different potentials can be formed in correspondence with the number of the wiring patterns 55 and 56 disposed on the upper surface and the lower surface of the insulating substrate 7. Therefore, circuits having various potentials can be formed between the upper surface and the lower surface of the insulating substrate 7. As a result, the electronic parts mounting substrate 30 can have high density packing and be made thin. Also, in the electronic parts mounting substrate (refer to Fig. 1) where the respective side-surface patterns are insulated by the projection portions according to the embodiment 1, the circuit function that requires a nine-layer insulating substrate becomes a six-layer insulating substrate according to this example because the side-surface patterns can be packaged with high density.
  • the side-surface patterns 51 are formed by etching the conductive layer 5 formed on the wall surfaces of the mount opening portion 73. Therefore, the side-surface patterns are not peeled off by the punching process as in the prior art.
  • the side-surface patterns 51 are insulated from each other by the exposed surfaces 731, which are exposed on substantially the same plane as that of side-surface patterns 51, provided between the patterns of the mount opening portion 73. Therefore, no projection portions are provided on the wall surfaces of the mount opening portion 73. Hence, the electronic parts can be smoothly mounted.
  • the side-surface pads 52 are formed along the upper and lower end portions 511 of the side-surface patterns 51, the connection area of the side-surface pads 52 to the side-surface patterns 51 is large, and the reliability of connection of both the pads and patterns is high. Therefore, the side-surface pads 52 enable a current supplied to the side-surface patterns 51 to be readily led to the bonding pads 520.
  • This example is different from embodiment 4 in that the side-surface patterns 51 and the bonding pads 520 are directly connected to each other as shown in Fig. 26.
  • the side-surface patterns 51 are not peeled off as in the embodiment 4, mounting of the electronic parts is facilitated, and the electronic parts mounting substrate 30 can be designed for high packing density and thinness.
  • the present invention relates to an electronic parts mounting substrate in which side-surface patterns are disposed on side surfaces of a mount opening portion for mounting electronic parts, and a method of manufacturing same, with the advantages that the side-surface patterns can be prevented from being peeled off, and the side-surface patterns having a plurality of potentials can be readily formed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Plusieurs motifs (11) et (12) de faces latérales sont formés sur la surface des parois d'une ouverture (2) pour monter un élément électronique. Des sections saillantes (21) font saillie vers l'intérieur depuis la surface de l'ouverture (2). Les sections terminales des motifs (11) et (12) se prolongent sur les faces latérales de la section saillante (21). On forme les motifs (11) et (12) en attaquant le motif des faces latérales ne faisant pas partie de la couche conductrice sur toute la surface des parois de l'ouverture (2), le motif des faces latérales faisant partie de la couche conductrice recouverte par un film de résist pour le motif de face latérale. Dans ces conditions, la séparation des motifs des faces latérales est empêchée et, en même temps, plusieurs motifs de faces latérales auxquels on donne différents potentiels, peuvent facilement être formés.

Claims (4)

  1. Substrat de montage de parties électroniques (31, 32) qui est formé à partir d'un matériau isolant, ledit substrat (31, 32) comprenant des parties en protubérance (21, 22) dudit matériau isolant qui font saillie en direction de l'intérieur d'une ouverture de montage (2) qui est ménagée dans le substrat (31, 32) et comportant une pluralité de motifs de surface latérale (11, 12) présentant une pluralité de potentiels appliqués sur la paroi de ladite ouverture de montage (2); dans lequel des parties d'extrémité des motifs de surface latérale respectifs (11, 12) s'étendent jusqu'à des surfaces latérales desdites parties en protubérance (21, 22).
  2. Substrat de montage de parties électroniques selon la revendication 1, caractérisé en ce que la longueur desdites parties en protubérance (21, 22) qui s'étendent depuis une partie de base jusqu'à une extrémité interne afférente est comprise entre 0,1 mm et 0,5 mm.
  3. Procédé de fabrication d'un substrat de montage de parties électroniques (31, 32) selon la revendication 1, ledit procédé comprenant les étapes qui suivent:
    formation d'un trou (205) comportant des parties convexes (222) au niveau de sa périphérie ou de trous (201, 202, 203) qui sont sectionnées par des parois de partition (210, 211, 213, 222) entre les trous (201, 202, 203) dans une partie de formation d'ouverture de montage;
    dépôt d'un film de placage en métal (10) sur les surfaces de paroi du trou (205) ou des trous (201, 202, 203); et
    découpe des parties convexes (222) ou des parois de partition (210, 211, 213) de telle sorte que des parties des parties convexes (222) ou des parois de partition (210, 211, 213) restent pour former des parties en protubérance (21, 22) qui font saillie en direction de l'intérieur de l'ouverture de montage (2) au moyen d'un usinage par routeur.
  4. Procédé de fabrication d'un substrat de montage de parties électroniques selon la revendication 3, caractérisé en ce que la longueur desdits parties en protubérance (21, 22) qui s'étendent depuis une partie de base jusqu'à une extrémité interne afférente est comprise entre 0,1 mm et 0,5 mm.
EP96941888A 1995-12-22 1996-12-16 Substrat pour monter un element electronique et procede pour le fabriquer Expired - Lifetime EP0932328B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP03010873A EP1351296B1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un élément electronique et procedé de fabrication associée

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP35032395 1995-12-22
JP35032395 1995-12-22
JP30740296 1996-11-01
JP30740296 1996-11-01
JP32789896A JP4000609B2 (ja) 1995-12-22 1996-11-21 電子部品搭載用基板及びその製造方法
JP32789896 1996-11-21
PCT/JP1996/003672 WO1997024021A1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un element electronique et procede pour le fabriquer

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP03010873A Division EP1351296B1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un élément electronique et procedé de fabrication associée

Publications (3)

Publication Number Publication Date
EP0932328A1 EP0932328A1 (fr) 1999-07-28
EP0932328A4 EP0932328A4 (fr) 1999-10-27
EP0932328B1 true EP0932328B1 (fr) 2005-03-16

Family

ID=27338901

Family Applications (2)

Application Number Title Priority Date Filing Date
EP96941888A Expired - Lifetime EP0932328B1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un element electronique et procede pour le fabriquer
EP03010873A Expired - Lifetime EP1351296B1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un élément electronique et procedé de fabrication associée

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP03010873A Expired - Lifetime EP1351296B1 (fr) 1995-12-22 1996-12-16 Substrat pour monter un élément electronique et procedé de fabrication associée

Country Status (5)

Country Link
US (1) US6201185B1 (fr)
EP (2) EP0932328B1 (fr)
JP (1) JP4000609B2 (fr)
KR (1) KR100300624B1 (fr)
WO (1) WO1997024021A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100393271B1 (ko) * 1997-11-19 2003-07-31 이비덴 가부시키가이샤 다층 전자부품탑재용 기판의 제조 방법
US6545227B2 (en) * 2001-07-11 2003-04-08 Mce/Kdi Corporation Pocket mounted chip having microstrip line
US6879039B2 (en) * 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US7258549B2 (en) * 2004-02-20 2007-08-21 Matsushita Electric Industrial Co., Ltd. Connection member and mount assembly and production method of the same
US7839657B2 (en) * 2006-04-28 2010-11-23 Continental Automotive Systems Us, Inc. Position adjustable printed circuit board
JPWO2008096450A1 (ja) * 2007-02-09 2010-05-20 パナソニック株式会社 回路基板、積層回路基板および電子機器
JP5699344B2 (ja) * 2013-03-26 2015-04-08 大日本印刷株式会社 部品内蔵配線板、部品内蔵配線板の製造方法

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GB1339660A (en) * 1971-11-20 1973-12-05 Ferranti Ltd Supports for semiconductor devices
JPS5626487A (en) 1980-01-21 1981-03-14 Futaba Denshi Kogyo Kk Bothhside wiring board
JPS57115850A (en) 1981-01-10 1982-07-19 Nec Corp Chip carrier for semiconductor ic
US4547795A (en) 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
FR2590051B1 (fr) * 1985-11-08 1991-05-17 Eurotechnique Sa Carte comportant un composant et micromodule a contacts de flanc
FR2603739B1 (fr) 1986-09-05 1988-12-09 Cimsa Sintra Boitier de composant electronique muni de broches de connexion comportant un micro-boitier amovible
US5107586A (en) * 1988-09-27 1992-04-28 General Electric Company Method for interconnecting a stack of integrated circuits at a very high density
JPH02232986A (ja) 1989-03-07 1990-09-14 Sony Corp 基板及びその製造法
CA2049979A1 (fr) * 1990-01-24 1991-07-25 Jury D. Sasov Unite electronique tridimensionnelle et sa methode de fabrication
US5235211A (en) 1990-06-22 1993-08-10 Digital Equipment Corporation Semiconductor package having wraparound metallization
US5279706A (en) * 1992-10-13 1994-01-18 General Electric Company Method and apparatus for fabricating a metal interconnection pattern for an integrated circuit module
JPH06188534A (ja) 1992-12-17 1994-07-08 Ibiden Co Ltd 電子部品搭載用基板及びその製造方法
JPH0786752A (ja) * 1993-06-30 1995-03-31 Ibiden Co Ltd 電子部品搭載用基板
IL106892A0 (en) * 1993-09-02 1993-12-28 Pierre Badehi Methods and apparatus for producing integrated circuit devices

Also Published As

Publication number Publication date
EP0932328A1 (fr) 1999-07-28
JPH10189805A (ja) 1998-07-21
EP1351296B1 (fr) 2011-06-01
KR100300624B1 (ko) 2001-09-29
WO1997024021A1 (fr) 1997-07-03
EP0932328A4 (fr) 1999-10-27
US6201185B1 (en) 2001-03-13
KR19990076719A (ko) 1999-10-15
JP4000609B2 (ja) 2007-10-31
EP1351296A1 (fr) 2003-10-08

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