EP0880124A1 - Leistungsendstufe zum Antreiben von Zellen einer Plasmaanzeigetafel - Google Patents

Leistungsendstufe zum Antreiben von Zellen einer Plasmaanzeigetafel Download PDF

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Publication number
EP0880124A1
EP0880124A1 EP98410053A EP98410053A EP0880124A1 EP 0880124 A1 EP0880124 A1 EP 0880124A1 EP 98410053 A EP98410053 A EP 98410053A EP 98410053 A EP98410053 A EP 98410053A EP 0880124 A1 EP0880124 A1 EP 0880124A1
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EP
European Patent Office
Prior art keywords
transistor
output
signal
channel
transistors
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP98410053A
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English (en)
French (fr)
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EP0880124B1 (de
Inventor
Gilles Troussel
Céline Lardeau
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STMicroelectronics SA
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STMicroelectronics SA
SGS Thomson Microelectronics SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/24—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using incandescent filaments
    • G09G3/26—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using incandescent filaments to give the appearance of moving signs

Definitions

  • the present invention relates to a power output stage for the control of plasma display cells.
  • a plasma screen is a matrix type screen made up of cells arranged at the intersections of rows and columns.
  • a cell includes a cavity filled with a rare gas, two control electrodes and a deposit of red, green or blue phosphorus.
  • a potential difference between the control electrodes of this cell so as to trigger an ionization of his gas. This ionization is accompanied by an emission of ultraviolet rays.
  • the creation of the light point is obtained by excitation of the phosphorus deposited, by the rays emitted.
  • the control of the cells, in order to create images, is carried out, conventionally, by logic circuits producing control signals.
  • the logical states of these signals determine which cells are controlled to produce a light point and those which are controlled so as not to produce.
  • These logic circuits are generally supplied with low voltage, by example with a supply voltage of 5 volts or less. This tension is not not sufficient to directly control the cell electrodes. Between the logic circuits and cells to be controlled, so we use output stages power, to convert low voltage control signals into signals high voltage control.
  • the ionization of the gas in the cavities requires the application of high potentials on the control electrodes, of the order of magnitude of a hundred volts.
  • the electrodes can be represented, schematically, by relatively equivalent capacities high in the order of a hundred picofarad (and, correspondingly, by sources current of a few tens of milliamps).
  • the control of these electrodes is therefore equivalent to charging or discharging a capacity.
  • Gold generally, in plasma screens, one wishes to obtain signals which have stiff fronts.
  • control of the plasma display electrodes is realized by power output stages receiving low logic signals voltage and converting them into high voltage control signals.
  • FIG. 1 illustrates a typical embodiment of a stage 1 for controlling an electrode.
  • Floor 1 includes an entrance to command 2 and an output 4.
  • Command input 2 receives a logic signal IN1 input. It is assumed that this signal is a low voltage signal, which can take two states, a high state and a low state.
  • Output 4 provides a control signal OUT1 output.
  • This output signal is supplied to an electrode, represented by a equivalent capacity Cout mounted between outlet 4 and earth.
  • the command of the electrode consists in charging the Cout capacity, to bring it to a high potential VPP voltage, or to discharge it, if it was charged. We will assume that the charge is controlled when signal IN1 is high, and the discharge is commanded when signal IN1 is low.
  • Stage 1 comprises a pair 6 of power transistors 8 and 10.
  • These transistors are, typically, complementary power transistors of VDMOS type, N channel, and HVMOS thick oxide type, P channel.
  • VDMOS transistor we mean vertical, N-channel MOS type transistors, able to withstand large differences in source-drain potential and to provide or absorb large currents.
  • HVMOS transistor on thick oxide we hears MOS type transistors, P channel, able to withstand strong source - drain and source - grid potential differences.
  • the transistor 8, of the type P channel HVMOS receives the VPP potential on its source. Its drain is connected to the output 4 and its control gate receives an INP control signal. This transistor allows to charge the Cout capacity, when passing. The transistor 10 is then blocked.
  • the transistor 8 is on, but to be able to block it, the INP signal must be can reach a potential at least equal to VPP. To do this, the command of the transistor 8 is produced by a circuit 14 potential translator, this circuit 14 being controlled by the input signal IN1.
  • Circuit 14 includes two power transistors 16 and 18 of MOS type P channel, and two power transistors 20 and 22, MOS type N channel. use transistors capable of withstanding high voltage, for example VDMOS transistors, N channel, and HVMOS transistors on thick oxide, P channel.
  • the transistors 16 and 18 receive the VPP potential on their sources.
  • the transistors 20 and 22 receive the GND potential on their sources.
  • the drain of transistor 16 is connected to the control gate of transistor 18 and to the drain of transistor 20.
  • the drain of transistor 18 is connected to the control gate of the transistor 16 and to the drain of transistor 22. Drains of transistors 18 and 22 provide the control signal INP.
  • the transistor 20 receives the signal INN on its control grid.
  • transistor 22 receives a control signal NIN on its control grid.
  • This NIN signal is supplied by an inverter 24, supplied in low voltage, and receiving the INN signal as input.
  • INN GND
  • the transistors 20 and 22 are, respectively, blocked and on.
  • Transistors 16 and 18 are, therefore, respectively passing and blocked.
  • INP GND.
  • the load transistor 8 is conducting and the discharge transistor 10 is blocked.
  • INN VCC
  • transistors 20 and 22 are, respectively, blocked and passerby.
  • the transistors 16 and 18 are, therefore, respectively on and off.
  • INP VPP.
  • the load transistor 8 is blocked and the transistor discharge 10 is passing.
  • a first problem posed by the circuit of FIG. 1 is the surface necessary to make the charge transistor 8. Indeed, taking into account a on the other hand, differences in conductivity of the P-channel and N-channel transistors and, on the other hand, important values of the charge and discharge currents, the transistor 8 occupies an area on the order of two to three times that of occupied by transistor 10, with equivalent current performance.
  • a second problem posed by the circuit of FIG. 1 is the risk of simultaneous conduction of the output transistors 8 and 10, when the input signal IN1 changes state.
  • Such simultaneous conduction when we modify the control signals of transistors 8 and 10, causes significant dissipation, taking into account the voltage and current values relating to these transistors.
  • An object of the invention is to propose an output stage structure which reduces the area required for the charge transistor and avoids simultaneous conduction of the charge and discharge transistors during state changes of the input signal.
  • the invention proposes replace the P-channel load transistor with an N-channel transistor arranged so as to form a composite P-type transistor, and to control the N-channel charge and discharge transistors using dimensioned inverters to avoid simultaneous conduction.
  • the invention relates to a power output stage for the control of plasma display cells, comprising an input for receiving a low voltage input logic signal, an output to provide a signal high voltage output control, an output circuit comprising, on the one hand, a load transistor receiving a high voltage potential on a drain and having a source connected to the control output and, on the other hand, a discharge transistor receiving a reference potential on a source and having a drain connected to the output, and control means providing control signals to the charge and discharge transistors to control these transistors in operation of the logic input signal, characterized in that the load and discharge are of the VDMOS type with N channel, the load transistor being arranged to form a composite P-type transistor, and in that the means for controls are arranged so that the potential of the control grid of the load transistor drops faster than the output potential when the input logic signal controls discharge of the output.
  • the output circuit comprises, on the one hand, a P channel power transistor controlled by a potential translator circuit, said P-channel transistor receiving the high voltage potential on a source and having a drain connected to a control gate of the charge transistor and, on the other hand, an N-channel power transistor having a source receiving the potential and having a drain connected to the control gate of the transistor load, the so-called P-channel and N-channel transistors being controlled so that the P channel transistor be on when you want to make the load transistor on and the N channel transistor is on when we want to block the load transistor, and in that the control means include low voltage inverters to control the N-channel transistor and the transistor discharge, the said inverters being dimensioned so that, on the one hand, the discharge transistor is turned on after the N-channel transistor is turned on, when you want to control the discharge of the output and, on the other hand, the N-channel transistor is blocked after the discharge transistor is blocked, when you want to order a load of the output through the load transistor.
  • control means are sized so that when one of the P-channel and N-channel transistors is turned on of the output circuit, the other of these transistors is blocked previously, so as to avoid any simultaneous conduction of these transistors.
  • the stage comprises logic circuits of filtering to filter the logic input signal so as to avoid modification of control signals of the power transistors of the stage if pulses parasites of a duration less than a given duration appear in the signal input logic.
  • FIG. 2 illustrates a power output stage 30 produced according to the invention.
  • the output stage 30 includes a control input 32 for receiving a logic input signal IN2 and an output 34 to provide a control signal high voltage output OUT2.
  • the signal IN2 will typically be supplied by logic circuitry, not illustrated, which will determine its logical state according to images to be formed.
  • the output stage 30 comprises an output circuit 36 making it possible to connect the output 34 of stage 30 at a high voltage VPP supply potential or at GND ground potential.
  • VPP high voltage supply potential
  • GND ground potential we will choose, for example, a supply potential 150 volt high voltage VPP.
  • this electrode is connected to the output 34 of the stage 30. This electrode will behave like a capacitor, which can be charged or unload, as shown in Figure 1.
  • the output circuit 36 includes two power transistors 38 and 40 allowing, respectively, to bring the potential of the control output 34 to VPP potential and GND potential.
  • the drain of transistor 38 called the load, receives the VPP potential.
  • the source of the transistor 40 called the discharge, receives the potential GND.
  • the drain of transistor 40 and the source of transistor 38 are interconnected and constitute the output 34.
  • the load transistor 38 makes it possible to supply a current load at output 34, to bring the potential of signal OUT2 substantially to the level of VPP potential.
  • the discharge transistor 40 absorbs a discharge current supplied by output 34, to bring the signal potential OUT2 substantially at the GND potential. Considering a charge 100 picofarads capacitive on output 34 and charge and discharge times of the order of 100 to 200 nanoseconds, the charge and discharge currents will be of the order of 80 milliamps.
  • the transistors 38 and 40 are N channel VDMOS type transistors, able to supply and absorb large currents and withstand voltages source - significant drain. We will choose, for example, transistors having a number of elementary cells, respectively, of 9 * 10 and 5 * 18.
  • the circuit of output 36 further includes two power transistors 42 and 44 of MOS type associated with charge transistor 38. These transistors 42 and 44, respectively at P channel and N channel, make it possible to form, jointly with the transistor 38, a P type composite transistor.
  • the P channel MOS transistor 42 receives the VPP potential on its source. Its drain is connected to the control gate of the load transistor 38. It receives a control signal, noted S10, on its control gate.
  • the transistor 44 of the N channel MOS type, receives the GND potential on its source. Its drain is connected to the drain of transistor 42 and to the control gate of the load transistor 38. Its control gate receives a control signal denoted S9.
  • the signal received by the control gate of the load transistor 38, supplied by the transistors 42 and 44, is noted PCDE.
  • transistor 42 of MOS type, having a W / L ratio of 294/18 (with W / L the channel width / length ratio transistor channel) and a transistor 44, of the VDMOS type, having a number of elementary cells of 6 * 2.
  • S10 GND.
  • S9 GND.
  • the potential of the PCDE signal increases, by charging the equivalent gate capacitance of the transistor load 38. Once PCDE reaches the threshold voltage Vt of the transistor load 38, the load transistor 38 turns on and the potential on its source substantially reaches VPP - Vt.
  • the control signal S9 is produced by a low voltage inverter 46, formed of two complementary transistors 48 and 50, of MOS type.
  • the transistor 48 at channel P, receives the potential VCC on its source.
  • the transistor 50 with N channel, receives the GND potential on its source.
  • the drains of these transistors are connected between them and provide the signal S9.
  • the control grids of these transistors are interconnected and receive a logic control signal S5.
  • transistors 48 and 50 having, respectively, a ratio W / L of 100/5 and 50/3.
  • the NCDE control signal is produced by a low inverter 52 voltage, formed by two complementary transistors 54 and 56, of MOS type.
  • the transistor 54 with P channel, receives the potential VCC on its source.
  • the transistor 56 at channel N, receives the GND potential on its source.
  • the drains of these transistors are interconnected and provide the NCDE signal.
  • the order grids of these transistors are interconnected and receive the logic control signal S5.
  • transistors 54 and 56 having, respectively, a W / L ratio of 250/5 and 100/3.
  • the control signal S10 is produced by a translating circuit of potential 58, similar to that described for FIG. 1.
  • Circuit 58 includes two power transistors 60 and 62 of the P channel MOS type, and two transistors with power 64 and 66, of MOS type with N channel.
  • transistors 60 and 62 having, respectively, a W / L ratio of 50/18 and 100/18 and transistors 64 and 66, of the VDMOS type, having a number of elementary cells of 6 * 1.
  • Transistors 60 and 62 receive the VPP potential on their sources.
  • the transistors 64 and 66 receive the GND potential on their sources.
  • the drain of transistor 60 is connected to the control gate of transistor 62 and to the drain of transistor 64.
  • the drain of transistor 62 is connected to the control gate of the transistor 60 and to the drain of transistor 66.
  • the drains of transistors 62 and 66 provide the control signal S10.
  • Transistor 66 receives a logic signal S7 control panel on its control grid.
  • the transistors 62 and 60 are, therefore, respectively on and off.
  • S10 VPP.
  • S7 VCC
  • transistors 66 and 64 are, respectively, passing and blocked.
  • the transistors 60 and 62 are, therefore, respectively passing and blocked.
  • S10 GND.
  • the output stage 30 further comprises logic circuits introducing delays.
  • These delay circuits include inverters 70, 72, 76, 78 and 82, these inverters comprising an input and an output, and two logic gates 74 and 80, of the NON_ET type, these doors comprising two inputs and one output.
  • these circuits are supplied with low voltage, for example by VCC and GND potentials.
  • the inverter 70 receives the input signal IN2 as an input and produces, on its output, a logic signal S1, by inversion of the signal IN2.
  • This signal S1 is supplied to a first input of gate 80 and at the input of inverter 72.
  • This inverter 72 produces, on its output, a logic signal S2.
  • This signal is supplied to a first entrance of gate 74 and at the input of reverser 76.
  • This reverser 76 produces, on its output, a logic signal S3.
  • the signal S3 is supplied to the input of the inverter 78 which produces, on its output, a logic signal S4.
  • the signal S4 is supplied to the second entry of door 74.
  • Door 74 produces, on its exit, the signal logic S5 which is supplied to inverters 46 and 52.
  • the signal S5 is, moreover, supplied at the second entrance to door 80.
  • This door produces, on its exit, a logic signal S6 which is supplied to the input of the inverter 82.
  • the inverter 82 produces, on its output, the logic signal S7 supplied to the potential translator circuit 58.
  • the assembly formed by the door 74 and the inverters 76 and 78 allows, as as will be seen below, delaying the positive pulses in the input signal IN2.
  • This assembly concurrently with the inverter 72 and the door 80, makes it possible to delay the negative pulses in the input signal IN2.
  • FIGS. 3a to 3n respectively illustrate the logic input signal IN2, the signal S1, signal S5, signal S2, signal S4, signal S3, signal S6, S7 signal, S8 signal, NCDE signal, S9 signal, S10 signal, signal PCDE and the output control signal OUT2.
  • the inverters 76 and 78 make it possible to delay the parasitic pulses positive, appearing in signal IN2. Indeed, as long as the transition to the state signal S2 has not propagated in inverters 76 and 78, signal S5 is kept high. To increase the minimum delay, we can increase the number of reversers placed between the outlet of reverser 72 and the second entrance to door 74, or else modify the layout of transistors forming these inverters. We can also place a capacitor between inverters 76 and 78. The delay of the positive edges in the signal IN2 vis-à-vis screw S9 and NCDE signals avoids simultaneous conduction in transistors 42 and 44 and in transistors 38 and 40. The conduction of transistors 40 and 44 is delayed until switching off of transistor 42 by the potential translator circuit 58 controlled by the signal S7.
  • the lowering of signal S1 in low state causes the signal S6 to go up. This causes the descent in the low state of the signal S7 and the subsequent rise, in the high state, of the signal S8. From this done, we cause the signal S10 to rise to the VPP potential, which blocks the transistor 42. If it is assumed that the signal S9 is then always in the low state, the PCDE potential is then maintained, by capacitive effect, at the grid of the load transistor 38. Simultaneous conduction of transistors 42 and 44.
  • Signal S1 will go high. This will cause the transition to the low state of signal S2. Consequently, signal S5 will go up, independently of the signals S3 and S4 which, in parallel, will pass high and low respectively. Therefore, we will block the transistors 48 and 54 and make transistors 50 and 56 passable. transistors 50 and 56 so that the potential of the NCDE signal drops more quickly than that of signal S9, we will block transistor 40 before blocking transistor 44.
  • the invention makes it possible to have one outlet stage at a time that is bulky and optimized with regard to conduction problems simultaneous.
  • the circuit is optimized so that the load transistor 38 is blocked before the discharge transistor 40 does not turn on. To do this, it is necessary to ensure a fall in the potential of the PCDE signal which is faster than the fall in the signal potential OUT2. Indeed, otherwise, we can see appear a positive gate-drain potential difference at the charge transistor 38, particularly if the capacitive load associated with the output 34 is low. In this case, the transistor 38 being with channel N, one would attend a restoration in conduction of transistor 38 and a phenomenon of simultaneous conduction. To avoid the appearance of this phenomenon, one thus controls the transistor 42 so that it discharges the control gate of the charge transistor 38 faster than the transistor 40 does not discharge output 34.
  • Cgd the gate-drain capacitance of a transistor
  • Csd its source-drain capacitance
  • Cg the equivalent capacity on the grid
  • Csub its substrate capacity
  • C (34) the equivalent capacity of the output 34 and Vt the threshold voltage of the N-channel transistors
  • the source of transistor 40 will be connected to an analog ground to absorb the discharge current supplied by this output 34 and we will use a different mass for the other components of the output stage.
  • a safety device is provided, represented by a Zener diode 84 placed between the output 34 and the control gate of the transistor 38.
  • This Zener diode avoids the appearance of a potential difference too large between the control gate of transistor 38 and its source. The presence of this diode creates a potential discharge path from output 34 to the source of transistor 44. This is not penalizing insofar as the control of transistors 44 and 40 is produced by devices of the same type, the inverters 46 and 52. If these devices undergo variations in their characteristics, for example examples due to variations in manufacturing parameters or temperature operation, these variations will be of the same nature for these two inverters 46 and 52.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electronic Switches (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Logic Circuits (AREA)
EP98410053A 1997-05-22 1998-05-18 Leistungsendstufe zum Antreiben von Zellen einer Plasmaanzeigetafel Expired - Lifetime EP0880124B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9706498A FR2763735B1 (fr) 1997-05-22 1997-05-22 Etage de sortie de puissance pour la commande de cellules d'ecran a plasma
FR9706498 1997-05-22

Publications (2)

Publication Number Publication Date
EP0880124A1 true EP0880124A1 (de) 1998-11-25
EP0880124B1 EP0880124B1 (de) 2006-03-08

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US (1) US6097214A (de)
EP (1) EP0880124B1 (de)
JP (1) JP3365310B2 (de)
DE (1) DE69833741T2 (de)
FR (1) FR2763735B1 (de)

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JP3853195B2 (ja) * 2001-10-29 2006-12-06 株式会社ルネサステクノロジ 半導体装置
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CN1275388C (zh) * 2004-07-30 2006-09-13 东南大学 低功耗cmos型高压驱动电路
FR2878065A1 (fr) 2004-11-18 2006-05-19 St Microelectronics Sa Circuit de decharge d'une charge electrique, et etage de sortie de puissance comprenant un tel circuit de decharge pour la commande de cellules d'ecran plasma
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DE69833741T2 (de) 2006-11-16
JPH11143427A (ja) 1999-05-28
EP0880124B1 (de) 2006-03-08
FR2763735B1 (fr) 1999-08-13
FR2763735A1 (fr) 1998-11-27
US6097214A (en) 2000-08-01
JP3365310B2 (ja) 2003-01-08
DE69833741D1 (de) 2006-05-04

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