EP0880124A1 - Power output stage for driving the cells of a plasma panel - Google Patents

Abstract

The power output stage (30) includes an input (32) receiving a low voltage input logic signal (IN2) and an output (34) supplying a high voltage control signal (OUT2). An output circuit (36) includes a charge transistor, which receives a high voltage potential(VPP) on a drain and has a source connected to an output (34). The output circuit also has a discharge transistor (40) which receives a reference potential (GND) on a source and has a drain connected to the output (34). A control circuit (42,44,46,52,58) supplies control signals (PCDE,NCDE) to the charge and discharge transistors as a function of the input logic signal. The charge and discharge transistors are of the n-channel VDMOS type. The charge transistor (38) is arranged to form a transistor of composite type P. The control circuit is arranged so that the potential at the grid of the charge transistor falls faster than the potential at the output when the input logic signal controls a discharge of the output .

Description

The present invention relates to a power output stage for the control of plasma display cells.

A plasma screen is a matrix type screen made up of cells arranged at the intersections of rows and columns. A cell includes a cavity filled with a rare gas, two control electrodes and a deposit of red, green or blue phosphorus. To create a bright spot on the screen, using a given cell, we apply a potential difference between the control electrodes of this cell, so as to trigger an ionization of his gas. This ionization is accompanied by an emission of ultraviolet rays. The creation of the light point is obtained by excitation of the phosphorus deposited, by the rays emitted.

The control of the cells, in order to create images, is carried out, conventionally, by logic circuits producing control signals. The logical states of these signals determine which cells are controlled to produce a light point and those which are controlled so as not to produce. These logic circuits are generally supplied with low voltage, by example with a supply voltage of 5 volts or less. This tension is not not sufficient to directly control the cell electrodes. Between the logic circuits and cells to be controlled, so we use output stages power, to convert low voltage control signals into signals high voltage control.

The ionization of the gas in the cavities requires the application of high potentials on the control electrodes, of the order of magnitude of a hundred volts. On the other hand, it is necessary to be able to supply the electrodes (and, correlatively, to be able to receive from these electrodes) large currents, of the order of several tens of milliamps. Indeed, the electrodes can be represented, schematically, by relatively equivalent capacities high in the order of a hundred picofarad (and, correspondingly, by sources current of a few tens of milliamps). The control of these electrodes is therefore equivalent to charging or discharging a capacity. Gold generally, in plasma screens, one wishes to obtain signals which have stiff fronts. This represents, for example, charging times and discharge of the order of one hundred nanoseconds. Given the potential high to reach and the importance of the capacitive load, this supposes that one can provide charge currents and absorb very discharge currents significant, up to a hundred milliamps.

As mentioned, the control of the plasma display electrodes is realized by power output stages receiving low logic signals voltage and converting them into high voltage control signals.

Figure 1 illustrates a typical embodiment of a stage 1 for controlling an electrode. Floor 1 includes an entrance to command 2 and an output 4. Command input 2 receives a logic signal IN1 input. It is assumed that this signal is a low voltage signal, which can take two states, a high state and a low state. The high state will be represented by a positive potential VCC, with for example VCC = 5V. The low state will be represented by a ground potential GND = V. Output 4 provides a control signal OUT1 output. This output signal is supplied to an electrode, represented by a equivalent capacity Cout mounted between outlet 4 and earth. The command of the electrode consists in charging the Cout capacity, to bring it to a high potential VPP voltage, or to discharge it, if it was charged. We will assume that the charge is controlled when signal IN1 is high, and the discharge is commanded when signal IN1 is low.

Stage 1 comprises a pair 6 of power transistors 8 and 10. These transistors are, typically, complementary power transistors of VDMOS type, N channel, and HVMOS thick oxide type, P channel. VDMOS transistor, we mean vertical, N-channel MOS type transistors, able to withstand large differences in source-drain potential and to provide or absorb large currents. By HVMOS transistor on thick oxide, we hears MOS type transistors, P channel, able to withstand strong source - drain and source - grid potential differences. The transistor 8, of the type P channel HVMOS receives the VPP potential on its source. Its drain is connected to the output 4 and its control gate receives an INP control signal. This transistor allows to charge the Cout capacity, when passing. The transistor 10 is then blocked. The N channel VDMOS transistor 10 receives the GND potential on its source. Its drain is connected to output 4 and its control gate receives a INN control signal. This transistor allows the Cout capacity to be discharged, when passing. The transistor 8 is then blocked. The transistor control discharge 10 is achievable at low voltage. If INN = VCC it is passing, and if INN = GND, it is blocked. Thus, in circuit 1, the signal INN is supplied by a inverter 12 receiving the signal IN1. We will use a low voltage inverter, powered by VCC and GND potentials. This inverter allows you to reverse the signal polarity IN1 so that charging and discharging are controlled, respectively, by IN1 = VCC and IN1 = GND. The transistor control charge 8 requires a high voltage command. Indeed, if INP = GND, the transistor 8 is on, but to be able to block it, the INP signal must be can reach a potential at least equal to VPP. To do this, the command of the transistor 8 is produced by a circuit 14 potential translator, this circuit 14 being controlled by the input signal IN1.

Circuit 14 includes two power transistors 16 and 18 of MOS type P channel, and two power transistors 20 and 22, MOS type N channel. use transistors capable of withstanding high voltage, for example VDMOS transistors, N channel, and HVMOS transistors on thick oxide, P channel. The transistors 16 and 18 receive the VPP potential on their sources. The transistors 20 and 22 receive the GND potential on their sources. The drain of transistor 16 is connected to the control gate of transistor 18 and to the drain of transistor 20. The drain of transistor 18 is connected to the control gate of the transistor 16 and to the drain of transistor 22. Drains of transistors 18 and 22 provide the control signal INP. The transistor 20 receives the signal INN on its control grid. Finally, transistor 22 receives a control signal NIN on its control grid. This NIN signal is supplied by an inverter 24, supplied in low voltage, and receiving the INN signal as input. When INN = GND, the transistors 20 and 22 are, respectively, blocked and on. Transistors 16 and 18 are, therefore, respectively passing and blocked. We then have INP = GND. The load transistor 8 is conducting and the discharge transistor 10 is blocked. When INN = VCC, then transistors 20 and 22 are, respectively, blocked and passerby. The transistors 16 and 18 are, therefore, respectively on and off. We then have INP = VPP. The load transistor 8 is blocked and the transistor discharge 10 is passing.

A first problem posed by the circuit of FIG. 1 is the surface necessary to make the charge transistor 8. Indeed, taking into account a on the other hand, differences in conductivity of the P-channel and N-channel transistors and, on the other hand, important values of the charge and discharge currents, the transistor 8 occupies an area on the order of two to three times that of occupied by transistor 10, with equivalent current performance.

A second problem posed by the circuit of FIG. 1 is the risk of simultaneous conduction of the output transistors 8 and 10, when the input signal IN1 changes state. Such simultaneous conduction, when we modify the control signals of transistors 8 and 10, causes significant dissipation, taking into account the voltage and current values relating to these transistors.

An object of the invention is to propose an output stage structure which reduces the area required for the charge transistor and avoids simultaneous conduction of the charge and discharge transistors during state changes of the input signal. To do this, the invention proposes replace the P-channel load transistor with an N-channel transistor arranged so as to form a composite P-type transistor, and to control the N-channel charge and discharge transistors using dimensioned inverters to avoid simultaneous conduction.

Thus the invention relates to a power output stage for the control of plasma display cells, comprising an input for receiving a low voltage input logic signal, an output to provide a signal high voltage output control, an output circuit comprising, on the one hand, a load transistor receiving a high voltage potential on a drain and having a source connected to the control output and, on the other hand, a discharge transistor receiving a reference potential on a source and having a drain connected to the output, and control means providing control signals to the charge and discharge transistors to control these transistors in operation of the logic input signal, characterized in that the load and discharge are of the VDMOS type with N channel, the load transistor being arranged to form a composite P-type transistor, and in that the means for controls are arranged so that the potential of the control grid of the load transistor drops faster than the output potential when the input logic signal controls discharge of the output.

According to one embodiment, the output circuit comprises, on the one hand, a P channel power transistor controlled by a potential translator circuit, said P-channel transistor receiving the high voltage potential on a source and having a drain connected to a control gate of the charge transistor and, on the other hand, an N-channel power transistor having a source receiving the potential and having a drain connected to the control gate of the transistor load, the so-called P-channel and N-channel transistors being controlled so that the P channel transistor be on when you want to make the load transistor on and the N channel transistor is on when we want to block the load transistor, and in that the control means include low voltage inverters to control the N-channel transistor and the transistor discharge, the said inverters being dimensioned so that, on the one hand, the discharge transistor is turned on after the N-channel transistor is turned on, when you want to control the discharge of the output and, on the other hand, the N-channel transistor is blocked after the discharge transistor is blocked, when you want to order a load of the output through the load transistor.

According to one embodiment, the control means are sized so that when one of the P-channel and N-channel transistors is turned on of the output circuit, the other of these transistors is blocked previously, so as to avoid any simultaneous conduction of these transistors.

According to one embodiment, the stage comprises logic circuits of filtering to filter the logic input signal so as to avoid modification of control signals of the power transistors of the stage if pulses parasites of a duration less than a given duration appear in the signal input logic.

• la figure 1 illustre un étage de sortie selon l'état de la technique,
• la figure 2 illustre un étage de sortie selon l'invention, et
• les figures 3a à 3n illustrent des chronogrammes de signaux et de potentiels produits ou fournis par le circuit selon l'invention.

Other advantages and particularities will appear on reading the following description of an exemplary embodiment of the invention, to be read in conjunction with the appended drawings in which:

• FIG. 1 illustrates an output stage according to the state of the art,
• FIG. 2 illustrates an output stage according to the invention, and
• Figures 3a to 3n illustrate timing diagrams of signals and potentials produced or supplied by the circuit according to the invention.

FIG. 2 illustrates a power output stage 30 produced according to the invention.

The output stage 30 includes a control input 32 for receiving a logic input signal IN2 and an output 34 to provide a control signal high voltage output OUT2. The logic signal IN2 will be a low voltage signal, whose potential will be representative of a given logical state: IN2 = VCC, with VCC a low voltage supply potential, will represent a high logic state, and IN2 = GND, with GND a reference potential (also called potential of mass), will represent a low logical state. We will have, for example, VCC = 5 V and GND = 0 V. The signal IN2 will typically be supplied by logic circuitry, not illustrated, which will determine its logical state according to images to be formed.

The output stage 30 comprises an output circuit 36 making it possible to connect the output 34 of stage 30 at a high voltage VPP supply potential or at GND ground potential. We will choose, for example, a supply potential 150 volt high voltage VPP. To order a screen cell electrode plasma, not shown, this electrode is connected to the output 34 of the stage 30. This electrode will behave like a capacitor, which can be charged or unload, as shown in Figure 1.

The output circuit 36 includes two power transistors 38 and 40 allowing, respectively, to bring the potential of the control output 34 to VPP potential and GND potential. The drain of transistor 38, called the load, receives the VPP potential. The source of the transistor 40, called the discharge, receives the potential GND. The drain of transistor 40 and the source of transistor 38 are interconnected and constitute the output 34. The load transistor 38 makes it possible to supply a current load at output 34, to bring the potential of signal OUT2 substantially to the level of VPP potential. The discharge transistor 40 absorbs a discharge current supplied by output 34, to bring the signal potential OUT2 substantially at the GND potential. Considering a charge 100 picofarads capacitive on output 34 and charge and discharge times of the order of 100 to 200 nanoseconds, the charge and discharge currents will be of the order of 80 milliamps.

The transistors 38 and 40 are N channel VDMOS type transistors, able to supply and absorb large currents and withstand voltages source - significant drain. We will choose, for example, transistors having a number of elementary cells, respectively, of 9 * 10 and 5 * 18. The circuit of output 36 further includes two power transistors 42 and 44 of MOS type associated with charge transistor 38. These transistors 42 and 44, respectively at P channel and N channel, make it possible to form, jointly with the transistor 38, a P type composite transistor.

The P channel MOS transistor 42 receives the VPP potential on its source. Its drain is connected to the control gate of the load transistor 38. It receives a control signal, noted S10, on its control gate. The transistor 44, of the N channel MOS type, receives the GND potential on its source. Its drain is connected to the drain of transistor 42 and to the control gate of the load transistor 38. Its control gate receives a control signal denoted S9. The signal received by the control gate of the load transistor 38, supplied by the transistors 42 and 44, is noted PCDE. We will choose, for example, a transistor 42, of MOS type, having a W / L ratio of 294/18 (with W / L the channel width / length ratio transistor channel) and a transistor 44, of the VDMOS type, having a number of elementary cells of 6 * 2.

The power transistor 42 makes it possible to turn the transistor on. load 38. For this, it suffices to supply a signal S10 such that the transistor 42 is passerby. Take, for example, S10 = GND. The potential of signal S9 will have then a value such that transistor 44 will be blocked. We will choose, for example, S9 = GND. When transistor 42 is on, then the potential of the PCDE signal increases, by charging the equivalent gate capacitance of the transistor load 38. Once PCDE reaches the threshold voltage Vt of the transistor load 38, the load transistor 38 turns on and the potential on its source substantially reaches VPP - Vt.

To block the load transistor 38, use the transistor 44. For this, it suffices to impose, for example, S9 = VCC and S10 = VPP. Transistor 44 becomes passing and discharging, towards ground, the equivalent grid capacity of the transistor 38. During this discharge, of course, transistor 42 must be blocked. Thus, the transistor 38, with N channel, is controlled so that a low potential (S10 = GND) turns it on and a high potential (S9 = VCC) turns it on blocks, which corresponds to the behavior of a P-channel transistor. we can use a load transistor two to three times less than the transistor 8 of Figure 1, at equal charge current.

The control signal S9 is produced by a low voltage inverter 46, formed of two complementary transistors 48 and 50, of MOS type. The transistor 48, at channel P, receives the potential VCC on its source. The transistor 50, with N channel, receives the GND potential on its source. The drains of these transistors are connected between them and provide the signal S9. The control grids of these transistors are interconnected and receive a logic control signal S5. We will choose, for example, transistors 48 and 50 having, respectively, a ratio W / L of 100/5 and 50/3.

The NCDE control signal is produced by a low inverter 52 voltage, formed by two complementary transistors 54 and 56, of MOS type. The transistor 54, with P channel, receives the potential VCC on its source. The transistor 56, at channel N, receives the GND potential on its source. The drains of these transistors are interconnected and provide the NCDE signal. The order grids of these transistors are interconnected and receive the logic control signal S5. We will choose, for example, transistors 54 and 56 having, respectively, a W / L ratio of 250/5 and 100/3.

The control signal S10 is produced by a translating circuit of potential 58, similar to that described for FIG. 1. Circuit 58 includes two power transistors 60 and 62 of the P channel MOS type, and two transistors with power 64 and 66, of MOS type with N channel. Transistors suitable for bear high voltage. We will choose, for example, transistors 60 and 62 having, respectively, a W / L ratio of 50/18 and 100/18 and transistors 64 and 66, of the VDMOS type, having a number of elementary cells of 6 * 1.

Transistors 60 and 62 receive the VPP potential on their sources. The transistors 64 and 66 receive the GND potential on their sources. The drain of transistor 60 is connected to the control gate of transistor 62 and to the drain of transistor 64. The drain of transistor 62 is connected to the control gate of the transistor 60 and to the drain of transistor 66. The drains of transistors 62 and 66 provide the control signal S10. Transistor 66 receives a logic signal S7 control panel on its control grid. Finally, transistor 64 receives a control signal S8 on its control grid. This signal S8 is provided by a inverter 68, supplied with low voltage, and receiving the signal S7 at input. When S7 = GND, transistors 66 and 64 are, respectively, blocked and passerby. The transistors 62 and 60 are, therefore, respectively on and off. We then have S10 = VPP. When S7 = VCC, transistors 66 and 64 are, respectively, passing and blocked. The transistors 60 and 62 are, therefore, respectively passing and blocked. We then have S10 = GND.

The output stage 30 further comprises logic circuits introducing delays. These delay circuits include inverters 70, 72, 76, 78 and 82, these inverters comprising an input and an output, and two logic gates 74 and 80, of the NON_ET type, these doors comprising two inputs and one output. We supposes that these circuits are supplied with low voltage, for example by VCC and GND potentials.

The inverter 70 receives the input signal IN2 as an input and produces, on its output, a logic signal S1, by inversion of the signal IN2. This signal S1 is supplied to a first input of gate 80 and at the input of inverter 72. This inverter 72 produces, on its output, a logic signal S2. This signal is supplied to a first entrance of gate 74 and at the input of reverser 76. This reverser 76 produces, on its output, a logic signal S3. The signal S3 is supplied to the input of the inverter 78 which produces, on its output, a logic signal S4. The signal S4 is supplied to the second entry of door 74. Door 74 produces, on its exit, the signal logic S5 which is supplied to inverters 46 and 52. The signal S5 is, moreover, supplied at the second entrance to door 80. This door produces, on its exit, a logic signal S6 which is supplied to the input of the inverter 82. The inverter 82 produces, on its output, the logic signal S7 supplied to the potential translator circuit 58.

The assembly formed by the door 74 and the inverters 76 and 78 allows, as as will be seen below, delaying the positive pulses in the input signal IN2. This assembly, concurrently with the inverter 72 and the door 80, makes it possible to delay the negative pulses in the input signal IN2.

We will now describe the operation of circuit 30, with reference to FIGS. 3a to 3n which respectively illustrate the logic input signal IN2, the signal S1, signal S5, signal S2, signal S4, signal S3, signal S6, S7 signal, S8 signal, NCDE signal, S9 signal, S10 signal, signal PCDE and the output control signal OUT2.

We will assume that initially we have S1 = S5 = S3 = S7 = VCC, PCDE = OUT2 = VPP, and IN2 = S2 = S4 = S6 = S8 = NCDE = S9 = S10 = GND. In other words, the load transistor 38 is on and the discharge transistor 40 is blocked. The potential of signal OUT2 is therefore substantially equal to the potential VPP, neglecting the threshold voltage of transistor 38.

Suppose we want to order a discharge from the output of control 34 through the discharge transistor 40. To do this, we position the input signal IN2 in the high state. We then have IN2 = VCC. The signal S1 therefore goes go low. This leads, on the one hand, to a rise in the high state of the signal S6 and, on the other hand, a rise in the high state of the signal S2. Subsequently, the signal S3 goes down to the low state, and the signal S4 goes up to the high state. Once the signal S4 is mounted high, the signal S5 goes low.

The inverters 76 and 78 make it possible to delay the parasitic pulses positive, appearing in signal IN2. Indeed, as long as the transition to the state signal S2 has not propagated in inverters 76 and 78, signal S5 is kept high. To increase the minimum delay, we can increase the number of reversers placed between the outlet of reverser 72 and the second entrance to door 74, or else modify the layout of transistors forming these inverters. We can also place a capacitor between inverters 76 and 78. The delay of the positive edges in the signal IN2 vis-à-vis screw S9 and NCDE signals avoids simultaneous conduction in transistors 42 and 44 and in transistors 38 and 40. The conduction of transistors 40 and 44 is delayed until switching off of transistor 42 by the potential translator circuit 58 controlled by the signal S7.

The lowering of signal S1 in low state, in addition to the subsequent lowering of the signal S5, causes the signal S6 to go up. This causes the descent in the low state of the signal S7 and the subsequent rise, in the high state, of the signal S8. From this done, we cause the signal S10 to rise to the VPP potential, which blocks the transistor 42. If it is assumed that the signal S9 is then always in the low state, the PCDE potential is then maintained, by capacitive effect, at the grid of the load transistor 38. Simultaneous conduction of transistors 42 and 44.

When signal S5 goes low, transistors 50 and 56 will block and transistors 48 and 54 will turn on. The capacitive load seen by transistor 50 being less than that supported by transistor 54, the signal potential S9 will increase faster than the signal potential NCDE. We will therefore discharge the control gate of the charge transistor 38 faster than output 34, ensuring that transistor 38 always remains blocked during discharge of outlet 34. Knowing the charges at the outlet of inverters 46 and 52, the transistors 48 and 54 have indeed been dimensioned result. Therefore, when the transistor 40 turns on, the transistor 38 remains blocked, which removes the phenomenon of simultaneous conduction in these transistors. Once the transistor 40 passes, the potential of the signal OUT2 goes fall to reach GND potential.

Suppose that later we want to control the load of the output 34. To do this, we will set the input signal IN2 to the low state. We then have IN2 = GND.

Signal S1 will go high. This will cause the transition to the low state of signal S2. Consequently, signal S5 will go up, independently of the signals S3 and S4 which, in parallel, will pass high and low respectively. Therefore, we will block the transistors 48 and 54 and make transistors 50 and 56 passable. transistors 50 and 56 so that the potential of the NCDE signal drops more quickly than that of signal S9, we will block transistor 40 before blocking transistor 44.

The rise of signal S5 leads, in parallel, the descent of signal S6. Of even as, previously, the positive impulses were delayed with the inverters 76 and 78, here we will delay the negative pulses with the inverter 72 and gate 74. This delay makes it possible to ensure that transistors 40 and 44 are well blocked before the conduction of the transistor 38. As well as previously, this delay is achieved in the low voltage logic circuits located input, which avoids the appearance of conduction phenomena simultaneous in power transistors.

The passage to the high state of the signal S6 causes the descent to the low state of the signal S7 and, consequently, the rise to high of signal S8. Consequently, the transistor 66 will turn on and the potential of signal S10 will go down to GND. We will then turn on transistor 42. This being on, the potential on the gate of the charge transistor 38 will increase. We assume that then the transistor 44 is, of course, blocked, to avoid any simultaneous conduction in the transistors 42 and 44. To do this, the inverters 82 and 68 will be dimensioned consequence, knowing the load supported by the transistor 50. The transistor 38 will therefore become conducting and the potential of signal OUT2 will increase. At this moment, transistor 40 being blocked, there can be no simultaneous conduction transistors 38 and 40.

Thus, the invention makes it possible to have one outlet stage at a time that is bulky and optimized with regard to conduction problems simultaneous.

As we have seen, when ordering a discharge from output 34, the circuit is optimized so that the load transistor 38 is blocked before the discharge transistor 40 does not turn on. To do this, it is necessary to ensure a fall in the potential of the PCDE signal which is faster than the fall in the signal potential OUT2. Indeed, otherwise, we can see appear a positive gate-drain potential difference at the charge transistor 38, particularly if the capacitive load associated with the output 34 is low. In this case, the transistor 38 being with channel N, one would attend a restoration in conduction of transistor 38 and a phenomenon of simultaneous conduction. To avoid the appearance of this phenomenon, one thus controls the transistor 42 so that it discharges the control gate of the charge transistor 38 faster than the transistor 40 does not discharge output 34.

Let us denote Cgd the gate-drain capacitance of a transistor, Csd its source-drain capacitance, Cg the equivalent capacity on the grid, Csub its substrate capacity, Cs la capacitive load connected to output 34, C (34) the equivalent capacity of the output 34 and Vt the threshold voltage of the N-channel transistors

When switching from charge to discharge of the output, currents supplied by transistors 54 and 48 will charge the grid - drain capacities of the transistors 40 and 44. These currents are all the higher as the variation dV / dt of the potential signal OUT2 is important. These currents reduce the differences in gate potential - source of transistors 40 and 44. By reducing the resistance to the state passing Ron from transistor 48, we apply a gate-source potential difference more important for transistor 44. In this way, the descent is accelerated of the potential of the gate of the load transistor 38 relative to its source.

Cg(38) = Cgd(38) + Csd(42) + Csub(44) et

C(34) = Cs + Csd (38) + Csub (40).

We have:

Cg (38) = Cgd (38) + Csd (42) + Csub (44) and

C (34) = Cs + Csd (38) + Csub (40).

Vgs (44) = VCC - Ron (48) * Cgd (44) * dV/dt (PCDE) et

Vgs (40) = VCC - Ron (54) * Cgd (40) * dV/dt (OUT2)

In addition, we have:

Vgs (44) = VCC - Ron (48) * Cgd (44) * dV / dt (PCDE) and

Vgs (40) = VCC - Ron (54) * Cgd (40) * dV / dt (OUT2)

Ron (50) * Cgd (44) * dV/dt (PCDE) < Vt (44) et

Ron (56) * Cgd (40) * dV/dt (OUT2) < Vt (40).

With regard to the passage from the discharge to the charge of the outlet 34, care will be taken to satisfy the following conditions:

Ron (50) * Cgd (44) * dV / dt (PCDE) <Vt (44) and

Ron (56) * Cgd (40) * dV / dt (OUT2) <Vt (40).

Advantageously, in order to avoid a disturbance of the logical part of the output stage 30 by the output discharge 34, the source of transistor 40 will be connected to an analog ground to absorb the discharge current supplied by this output 34 and we will use a different mass for the other components of the output stage.

In the output stage 30, a safety device is provided, represented by a Zener diode 84 placed between the output 34 and the control gate of the transistor 38. This Zener diode avoids the appearance of a potential difference too large between the control gate of transistor 38 and its source. The presence of this diode creates a potential discharge path from output 34 to the source of transistor 44. This is not penalizing insofar as the control of transistors 44 and 40 is produced by devices of the same type, the inverters 46 and 52. If these devices undergo variations in their characteristics, for example examples due to variations in manufacturing parameters or temperature operation, these variations will be of the same nature for these two inverters 46 and 52. As a result, the influence of variations in the characteristics of these inverters on the operation of the output stage will be very limited. So we can easily reconcile the protection of transistor 38 and proper operation of the stage, by sizing the inverters 46 and 52 so that most of the current discharge of the output is absorbed by the discharge transistor 40, of which it is the function, rather than by transistor 44.

Of course, various modifications can be made by humans of the profession, without departing from the scope of the invention. So we can modify the polarity of logic signals and / or produce them with gates different logics. We could, for example, choose to reverse the polarities of the control signals and use NON_OU type doors instead of NON_ET doors.

Claims (4)

Power output stage (30) for controlling screen cells plasma, comprising an input (32) for receiving an input logic signal low voltage (IN2), an output (34) to provide an output control signal high voltage (OUT2), an output circuit (36) comprising, on the one hand, a load transistor (38) receiving a high voltage potential (VPP) on a drain and having a source connected to the output (34) and, on the other hand, a discharge transistor (40) receiving a reference potential (GND) on a source and having a drain connected to the outlet (34), and control means (42, 44, 46, 52, 58) providing control signals (PCDE, NCDE) to the load transistors and discharge to control these transistors according to the logic input signal, characterized in that the charge and discharge transistors (38, 40) are of the type N-channel VDMOS, the load transistor (38) being arranged to form a composite P-type transistor, and in that the control means are arranged so that the potential of the charge transistor control gate drops faster than the output potential when the logic signal input controls discharge of the output. Stage according to claim 1, characterized in that the output circuit (36) comprises, on the one hand, a P-channel power transistor (42) controlled by a potential translator circuit (58), said P-channel transistor receiving the high voltage potential (VPP) on a source and having a drain connected to a grid control of the load transistor (38) and, on the other hand, a power transistor N-channel (44) having a source receiving the reference potential (GND) and having a drain connected to the control gate of the charge transistor (38), said P-channel and N-channel transistors being controlled so that the transistor P channel (42) either on when you want to make the load transistor (38) on and the N channel transistor (44) is on when we want to block the load transistor (38), and in that the control means comprise low voltage inverters (46, 52) for controlling the N-channel transistor (44) and the discharge transistor (40), said inverters being dimensioned so on the one hand, the discharge transistor (40) is turned on after the N-channel transistor (44) is turned on, when it is desired to control the discharge of the output and, on the other hand, the N-channel transistor (44) is blocked after the discharge transistor (40) is blocked, when it is desired to control charging the output through the charge transistor (38). Stage according to claim 2, characterized in that the means for commands are sized so that when we pass one of the P-channel and N-channel transistors (42, 44) of the output circuit, the other of these transistor is blocked beforehand, so as to avoid any conduction of these transistors. Stage according to one of claims 1 to 3, characterized in that it includes delay logic circuits (72, 74, 76, 78, 80) for delaying the input logic signal (IN2) so as to avoid modification of control (PCDE, NCDE) of the power transistors of the stage if spurious pulses of duration shorter than a given duration appear in the logic input signal.

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