FR2763735A1 - POWER OUTPUT STAGE FOR CONTROLLING PLASMA SCREEN CELLS - Google Patents

Abstract

The invention relates to a power output stage (30) for controlling plasma screen cells. It comprises two N-channel VDMOS charge and discharge transistors (38, 40), the charge transistor being arranged to form a composite P-type transistor. These transistors provide a charging current at an output (34) and absorb a discharge current from this output. Two inverters (46, 52) are sized so that the potential of the control gate of the load transistor (38) drops faster than the output potential when a discharge of that output is commanded. Thus, an output stage of limited size and without risk of simultaneous conduction of the charge and discharge transistors is realized.

Description

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  Etaee power output for the

  control of plasma screen cells.

  The present invention relates to a power output stage for the

  control of plasma screen cells.

  A plasma screen is a matrix-type screen, made up of cells arranged at intersections of rows and columns. A cell comprises a cavity filled with a rare gas, two control electrodes and a red, green or blue phosphorus deposit. To create a luminous point on the screen, using a given cell, a potential difference is applied between the control electrodes of this cell, so as to trigger an ionization of its gas. This ionization is accompanied by an emission of ultraviolet rays. The creation of the luminous point is obtained by excitation of the deposited phosphorus, by

the rays emitted.

  The control of the cells, in order to create images, is carried out,

  conventionally, by logic circuits producing control signals.

  The logic states of these signals determine the cells that are controlled to produce a bright spot and those that are controlled to not produce one. These logic circuits are generally supplied with low voltage, for example with a supply voltage of 5 volts or less. This voltage is not sufficient to directly drive the electrodes of the cells. Between the logic circuits and the cells to be controlled, therefore, power output stages are used to convert the low voltage control signals into signals.

high voltage control.

  Ionization of the gas cavities requires the application of high potentials on

  the control electrodes, of the order of magnitude of the hundred volts.

  On the other hand, it is necessary to be able to provide the electrodes (and, correlatively, to be able to receive these electrodes) large currents, of the order of several tens of milliamperes. Indeed, the electrodes can be represented, schematically, by relatively high equivalent capacities of the order of one hundred picofarad (and, correlatively, current sources of a few tens of milliamperes). The control of these electrodes is therefore equivalent to the control of charge or discharge of a capacitance. Now it is generally desired in plasma screens to obtain signals which have steep edges. This represents, for example, charging and discharging times of the order of one hundred nanoseconds. Given the high potential to reach and the magnitude of the capacitive load, this implies that load currents can be provided and very high discharge currents can be absorbed.

  important, up to a hundred milliamps.

  s As mentioned, the control of plasma screen electrodes is performed by power output stages receiving low logic signals

  voltage and converting them into high voltage control signals.

  Figure 1 illustrates an example of a conventional embodiment of an output stage 1 for controlling an electrode. The stage 1 comprises a control input 2 and an output 4. The control input 2 receives an input logic signal IN1. It is assumed that this signal is a low voltage signal that can assume two states, a high state and a low state. The high state will be represented by a positive potential VCC, with for example VCC = 5 V. The low state will be represented by a ground potential GND = 0 V. Output 4 provides an output control signal OUT 1. This Output signal is provided to an electrode, represented by an equivalent capacitance capacity mounted between output 4 and ground. The control of the electrode is to charge the capacity Cout, to bring it to a potential high voltage VPP, or to discharge it, if it was loaded. It will be assumed that the load is controlled when signal IN1 is in the high state, and that the discharge is

  controlled when the signal IN 1 is in the low state.

  The stage 1 comprises a pair 6 of power transistors 8 and 10. These transistors are, typically, complementary VDMOS type, N channel type, and thick oxide, P-channel type HVMOS transistors. By VDMOS transistor means vertical N-channel MOS type transistors capable of withstanding large differences in source-drain potential and providing or absorbing large currents. The term "thick oxide HVMOS transistor" refers to P-channel MOS type transistors capable of withstanding large differences in source-drain and source-gate potential. Transistor 8, of the P-channel HVMOS type, receives the potential VPP on its source. Its dramin is connected to the output 4 and its control gate receives an INP control signal. This transistor can charge the Cout capacity, when it is passing. The transistor 10 is then blocked. Transistor 10, of the N-channel VDMOS type, receives the GND potential on its source. Its drain is connected to the output 4 and its control gate receives an INN control signal. This transistor makes it possible to discharge the capacity Cout, when it is passing. The transistor 8 is then blocked. The transistor control

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  discharge 10 is achievable at low voltage. If INN = VCC it is passing, and if INN = GND, it is blocked. Thus, in the circuit 1, the signal INN is provided by an inverter 12 receiving the signal IN1. We will use a low voltage inverter, powered by the VCC and GND potentials. This inverter makes it possible to invert the polarity of the signal IN 1 so that the charge and the discharge are controlled, respectively, by IN1 = VCC and INI = GND. The control of the load transistor 10 requires high voltage control. Indeed, if INP = GND, the transistor 10 is passing, but to be able to block it, it is necessary that the signal INP can reach a potential at least equal to VPP. To do this, the transistor 8 is controlled by a potential translator circuit 14, which circuit 14

  being controlled by the input signal IN 1.

  The circuit 14 comprises two P-channel MOS power transistors 16 and 18 and two N-channel MOS type power transistors 20 and 22. Transistors capable of supporting the high voltage, for example VDMOS transistors, will be used. N-channel, and thick-channel, P-channel HVMOS transistors. Transistors 16 and 18 receive the VPP potential at their sources. Transistors 20 and 22 receive the potential GND on their sources. The drain of the transistor 16 is connected to the control gate of the transistor 18 and the drain of the transistor 20. The drain of the transistor 18 is connected to the control gate of the transistor 16 and the drain of the transistor 22. The drains of the transistors 18 and 22 provide the control signal INP. The transistor 20 receives the signal INN on its control gate. Enfmin, the transistor 22 receives a control signal NIN on its control gate. This NIN signal is provided by an inverter 24, supplied with low voltage, and receiving the input signal INN. When INN = GND, transistors 20 and 22 are respectively blocked and switched on. Transistors 16 and 18 are therefore respectively conducting and blocked. We then have INP = GND. The

  Charge transistor 8 is on and the discharge transistor 10 is off.

  When INN = VCC, then transistors 20 and 22 are respectively on and off. Transistors 16 and 18 are therefore respectively conducting and blocked. We then have INP = VPP. Charge transistor 8 is blocked and the transistor

discharge 10 is passing.

  A first problem posed by the circuit of FIG. 1 is the area necessary to produce the charge transistor 8. Indeed, taking into account, on the one hand, differences in the conductivity of the P-channel and N-channel transistors and, on the other hand, significant values of the charging and discharging currents, the

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  transistor 8 occupies a surface of the order of two to three times greater than

  occupied by transistor 10, equivalent current performance.

  A second problem posed by the circuit of FIG. 1 is the risk of simultaneous conduction of the output transistors 8 and 10, when the input signal INI changes state. Such a simultaneous conduction, when modifying the control signals of transistors 8 and 10, leads to a considerable dissipation,

  given the voltage and current values for these transistors.

  An object of the invention is to propose an output stage structure which makes it possible to reduce the area required for the load transistor and to avoid simultaneous conduction of the load and discharge transistors during the changes in the state of the signal of the load. 'Entrance. For this purpose, the invention proposes to replace the P-channel charge transistor with an N-channel transistor arranged to form a composite P-type transistor, and to control the N-channel charge and discharge transistors at the same time. using sized inverters

  to avoid simultaneous conduction.

  Thus, the invention relates to a power output stage for controlling plasma screen cells, comprising an input for receiving a low voltage input logic signal, an output for providing a high voltage output control signal, a output circuit comprising, on the one hand, a load transistor receiving a high voltage potential on a drain and having a source connected to the control output and, on the other hand, a discharge transistor receiving a reference potential on a source and having a drain connected to the output, and control means providing control signals to the load and discharge transistors for controlling these transistors as a function of the input logic signal, characterized in that the load transistors and the discharge are of N-channel VDMOS type, the charge transistor being arranged to form a composite P type transistor, and in that the control means are arranged so that the potent ial of the charge transistor control gate drops faster than the output potential when the

  input logic signal controls discharge of the output.

  According to one embodiment, the output circuit comprises, on the one hand, a P-channel power transistor controlled by a potential translator circuit, said P-channel transistor receiving the high voltage potential on a source and having a drain connected to a control gate of the charge transistor and, secondly, an N-channel power transistor having a source receiving the potential

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  reference and having a drain connected to the control gate of the load transistor, said P-channel and N-channel transistors being controlled so that the P-channel transistor is on when it is desired to make the load transistor go through and the N-channel transistor is conducting when it is desired to block the load transistor, and in that the control means comprise low-voltage inverters for controlling the N-channel transistor and the discharge transistor, said inverters being sized so that on the one hand, the discharge transistor is turned on after the N-channel transistor is turned on, when it is desired to control the discharge of the output and, on the other hand, the N-channel transistor is blocked after that the discharge transistor is blocked, when it is desired to control a load of the output through the

charge transistor.

  According to one embodiment, the control means are dimensioned so that, when one of the P-channel and N-channel transistors of the output circuit is turned on, the other of these transistors is previously blocked,

  way to avoid simultaneous conduction of these transistors.

  According to one embodiment, the stage comprises filtering logic circuits for filtering the input logic signal so as to avoid a modification of control signals of the stage power transistors if spurious pulses of a shorter duration at a given time appear in the signal

input logic.

  Other advantages and particularities will appear on reading the description

  which follows of an exemplary embodiment of the invention, to read in conjunction with the accompanying drawings in which: - Figure 1 illustrates an output stage according to the prior art, - Figure 2 illustrates an output stage according to the invention, and FIGS. 3a to 3n illustrate timing diagrams of signals and

  potential products or provided by the circuit according to the invention.

  FIG. 2 illustrates a power output stage 30 produced according to

the invention.

  The output stage 30 includes a control input 32 for receiving an input logic signal IN2 and an output 34 for providing a high voltage output control signal OUT2. The logic signal IN2 will be a low voltage signal whose potential will be representative of a given logic state: IN2 = VCC, with VCC a low voltage supply potential, will represent a high logic state,

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  and IN2 = GND, with GND a reference potential (also called mass potential), will represent a low logic state. For example, VCC = 5 V and GND = 0 V. The IN2 signal will typically be provided by a logic circuit,

  not illustrated, which will determine its logical state according to images to be formed.

  The output stage 30 comprises an output circuit 36 making it possible to connect the output 34 of the stage 30 to a high voltage VPP supply potential or to the GND ground potential. For example, a high voltage VPP supply potential of 150 volts will be chosen. To control a plasma screen cell electrode, not shown, this electrode is connected to the output 34 of the stage 30. This electrode will behave as a capacitor, which can be charged or

  unload, as shown in Figure 1.

  The output circuit 36 comprises two power transistors 38 and 40 respectively for increasing the potential of the control output 34 to the potential VPP and the potential GND. The drain of transistor 38, called charge, receives the potential VPP. The source of transistor 40, called discharge, receives the potential GND. The drain of the transistor 40 and the source of the transistor 38 are interconnected and constitute the output 34. The load transistor 38 provides a charging current at the output 34, to bring the signal potential OUT2 substantially to the potential level. VPP. The discharge transistor 40 makes it possible to absorb a discharge current supplied by the output 34, in order to bring the potential of the signal OUT2 substantially to the level of the potential GND. Considering a capacitive load of 100 picofarads on the output 34 and charging and discharging times of the order of 100 to 200 nanoseconds, the charging and discharging currents

  will be of the order of 80 milliamps.

  Transistors 38 and 40 are N-channel VDMOS type transistors capable of providing and absorbing large currents and withstanding large source-drain voltages. For example, transistors having a number of elementary cells of 9 * 10 and 5 * 18, respectively, will be chosen. The output circuit 36 furthermore comprises two MOS type power transistors 42 and 44 associated with the load transistor 38. These transistors 42 and 44, respectively P-channel and N-channel, make it possible to form, together with the transistor 38, a

composite type P transistor.

  Transistor 42, of the P-channel MOS type, receives the potential VPP on its source. Its drain is connected to the control gate of the charge transistor 38. It receives a control signal, denoted S10, on its control gate. The N-channel MOS transistor 44 receives the GND potential on its source. Its drain is connected to the drain of transistor 42 and to the control gate of charge transistor 38. Its control gate receives a control signal denoted S9. The signal received by the control gate of the charge transistor 38, supplied by the transistors 42 and 44, is noted as PCDE. For example, a transistor 42, of the MOS type, having a W / L ratio of 294/18 (with W / L the channel width / channel length ratio of the transistor) and a transistor 44, of the VDMOS type, will be selected. having a number of

elementary cells of 6 * 2.

  The power transistor 42 makes it possible to turn on the load transistor 38. To do this, it suffices to supply a signal S 10 such that the transistor 42 is on. We will take, for example, S10 = GND. The potential of the signal S9 will then have a value such that the transistor 44 will be blocked. For example, S9 = GND will be chosen. When the transistor 42 is on, then the potential of the PCDE signal increases, by charging the equivalent gate capacitance of the charge transistor 38. Once the PCDE reaches the threshold voltage Vt of the charge transistor 38, the charge transistor 38 becomes passing and the potential on its source

achieved substantially VPP - Vt.

  To block charge transistor 38, transistor 44 is used. For this, it suffices to impose, for example, S9 = VCC and S10 = VPP. Transistor 44 becomes on and the equivalent gate capacitance of transistor 38 is discharged to ground. During this discharge, of course, transistor 42 must be turned off. Thus, the N-channel transistor 38 is controlled so that a low potential (S10 = GND) turns it on and a high potential (S9 = VCC) blocks it, which corresponds to the behavior of a On the other hand, it is possible to use a charge transistor two to three times smaller than the

  transistor 8 of Figure 1, at equal load current.

  The control signal S9 is produced by a low voltage inverter 46, formed of two complementary transistors 48 and 50, of the MOS type. Transistor 48, P-channel, receives the potential VCC on its source. The N-channel transistor 50 receives the GND potential on its source. The drains of these transistors are interconnected and provide the signal S9. The control gates of these transistors are interconnected and receive a control logic signal S5. For example, transistors 48 and 50 having, respectively, a ratio

W / L of 100/5 and 50/3.

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  The control signal NCDE is produced by a low voltage inverter 52, formed of two complementary transistors 54 and 56, of the MOS type. The P-channel transistor 54 receives the potential VCC on its source. The N-channel transistor 56 receives the GND potential on its source. The drains of these transistors are interconnected and provide the NCDE signal. The control grids of these

  transistors are interconnected and receive the control logic signal S5.

  For example, transistors 54 and 56 having, respectively, a

W / L ratio of 250/5 and 100/3.

  The control signal S10 is produced by a potential translator circuit 58, similar to that described for FIG. 1. The circuit 58 comprises two P-channel MOS power transistors 60 and 62, and two power transistors 64 and 66. , of N-channel MOS type. Transistors capable of withstanding the high voltage will be used. For example, transistors 60 and 62 having a W / L ratio of 50/18 and 100/18 and transistors 64 and 64, respectively, will be selected.

  66, of type VDMOS, having a number of elementary cells of 6 * 1.

  Transistors 60 and 62 receive the VPP potential on their sources. Transistors 64 and 66 receive the GND potential on their sources. The drain of the transistor 60 is connected to the control gate of the transistor 62 and to the drain of the transistor 64. The drain of the transistor 62 is connected to the control gate of the transistor 60 and to the drain of the transistor 66. The drains of the transistors 62 and 66 provide the control signal S 10. The transistor 66 receives a control logic signal S7 on its control gate. Finally, the transistor 64 receives a control signal S8 on its control gate. This signal S8 is provided by a

  inverter 68, supplied with low voltage, and receiving the signal S7 input.

  When S7 = GND, transistors 66 and 64 are, respectively, blocked and

  passing. Transistors 62 and 60 are therefore respectively conducting and blocked.

  We then have S10 = VPP. When S7 = VCC, transistors 66 and 64 are respectively on and off. Transistors 60 and 62 are, therefore,

  respectively passing and blocked. We then have S10 = GND.

  The output stage 30 further comprises logic circuits introducing delays. These delay circuits comprise inverters 70, 72, 76, 78 and 82, these inverters comprising an input and an output, and two logic gates 74 and 80, of the NONET type, these gates comprising two inputs and an output. It is assumed that these circuits are supplied with low voltage, for example by

potential VCC and GND.

  The inverter 70 receives the input signal IN2 as input and produces, at its output, a logic signal SI1, by inverting the signal IN2. This signal SI1 is supplied to a first input of the gate 80 and to the input of the inverter 72. This inverter 72 produces, at its output, a logic signal S2. This signal is supplied to a first input of the gate 74 and to the input of the inverter 76. This inverter 76 produces, at its output, a logic signal S3. The signal S3 is supplied to the input of the inverter 78 which produces, at its output, a logic signal S4. The signal S4 is supplied to the second input of the gate 74. The gate 74 produces, at its output, the logic signal S5 which is supplied to the inverters 46 and 52. The signal S5 is, moreover, supplied to the second input of gate 80. This gate produces, on its output, a logic signal S6 which is supplied to the input of the inverter 82. The inverter 82 produces,

  at its output, the logic signal S7 supplied to the potential translator circuit 58.

  The assembly formed by the gate 74 and the inverters 76 and 78 makes it possible, as will be seen hereinafter, to delay the positive pulses in the input signal IN2. This assembly, concurrently with the inverter 72 and the gate 80, allows

  delay the negative pulses in the input signal IN2.

  The operation of the circuit 30 will now be described with reference to FIGS. 3a to 3n which respectively illustrate the input logic signal IN2, the signal S1, the signal S5, the signal S2, the signal S4, the signal S3, the signal S6, the signal S7, the signal S8, the signal NCDE, the signal S9, the signal S10, the signal

  PCDE and OUT2 output control signal.

  It will be assumed that initially S1 = S5 = S3 = S7 = VCC, PCDE =

  OUT2 = VPP, and IN2 = S2 = S4 = S6 = S8 = NCDE = S9 = S10 = GND.

  In other words, the charge transistor 38 is on and the discharge transistor 40 is off. The potential of the signal OUT2 is therefore substantially equal to the potential

  VPP, neglecting the threshold voltage of the transistor 38.

  Suppose that it is desired to control a discharge of the control output 34 through the discharge transistor 40. To do this, the input signal IN2 is set high. We then have IN2 = VCC. The signal S 1 will therefore go to the low state. This causes, on the one hand, a high rise of the signal S6 and, on the other hand, a rise to the high state of the signal S2. Subsequently, the signal S3 goes down, and the signal S4 goes up. Once the S4 signal

  is mounted high, the signal S5 goes to the low state.

  The inverters 76 and 78 make it possible to delay the positive spurious pulses appearing in the signal IN2. Indeed, as long as the transition to the high state of the signal S2 has not propagated in the inverters 76 and 78, the signal S5 is kept high. To increase the minimum delay delay, we can increase the number of miners placed between the output of the inverter 72 and the second input of the door 74, or even change the size of the transistors forming these inverters. It will also be possible to place a capacitor between the inverters 76 and 78. The delay of the positive edges in the signal IN2 with respect to the signals S9 and NCDE makes it possible to avoid simultaneous conduction in the transistors 42 and 44 and in the transistors 38. and 40. The conduction of transistors 40 and 44 is delayed until the transistor 42 is turned off.

  by the potential translator circuit 58 controlled by the signal S7.

  The downward descent of the signal S 1, in addition to the subsequent induced descent of the signal S5, causes the high state of the signal S6 to rise. This causes the signal S7 to go down to a low state and the signal S8 to rise further in the high state. As a result, the voltage VPP is raised to the signal S10, which blocks the transistor 42. If it is assumed that the signal S9 is then always in the low state, the potential PCDE is then maintained, by capacitive effect, at the level of the gate of the charge transistor 38. Simultaneous conduction of the transistors 42 and 44 is avoided. When the signal S5 goes down, the transistors 50 and 56 will lock and the transistors 48 and 54 will become on. As the capacitive load seen by the transistor 50 is lower than that supported by the transistor 54, the potential of the signal S9 will increase more rapidly than the potential of the signal NCDE. Thus, the control gate of the charge transistor 38 will be discharged more rapidly than the output 34, thus ensuring that the transistor 38 remains always blocked during the discharge of the output 34. Knowing the output loads of the inverters 46 and 52, we have indeed sized the transistors 48 and 54 accordingly. As a result, when the transistor 40 becomes on, the transistor 38 remains blocked, which eliminates the phenomenon of simultaneous conduction in these transistors. Once the transistor 40 passes, the potential of the signal OUT2 will

  fall to reach the GND potential.

  Suppose that later it is desired to control the load of the output 34. To do this, we will position the input signal IN2 in the low state. We then

IN2 = GND.

  The signal S 1 will go up. This will cause the signal S2 to go low. As a result, the signal S5 will go high, independently of the signals S3 and S4, which, in parallel, will go respectively to the high state and the low state. Therefore, we will block the transistors 48 and 54 and pass transistors 50 and 56. By sizing the transistors 50 and 56 so that the potential of the NCDE signal drops faster than that of the signal S9, we will block the transistor 40 before blocking

the transistor 44.

  The rise of the signal S5 leads, in parallel, the descent of the signal S6. Just as, previously, the positive pulses with the inverters 76 and 78 were delayed, here the negative pulses with the reverser 72 and the gate 74 will be delayed. This delay makes it possible to ensure that the transistors 40 and 44 are blocked before the transistor 38 is turned on. As before, this delay is achieved in the low voltage logic circuits located at the input, which makes it possible to avoid the appearance of conduction phenomena.

  simultaneous in the power transistors.

  The transition to the high state of the signal S6 causes the signal S7 to go down to the low state and, consequently, to raise the signal S8 to the high state. As a result, the transistor 66 will become on and the potential of the signal S 10 will

go down to GND.

  Transistor 42 will then be turned on. This being on, the potential on the gate of the charge transistor 38 will increase. It is assumed that the transistor 44 is, of course, blocked, to avoid simultaneous conduction in the transistors 42 and 44. To do this, the inverters 82 and 68 will be sized accordingly, knowing the load supported by the transistor 50. The transistor 38 will therefore become on and the potential of the signal OUT2 will increase. At this moment, the transistor 40 being blocked, there can not be simultaneous conduction

transistors 38 and 40.

  Thus, the invention makes it possible to have an output stage that is both compact and optimized with regard to the problems of simultaneous conduction. As has been seen, when a discharge of the output 34 is commanded, the circuit is optimized so that the load transistor 38 is turned off before the discharge transistor 40 becomes on. To do this, it is necessary to ensure a drop in the potential of the signal PCDE which is faster than the fall of the potential of the signal OUT2. In fact, in the opposite case, a positive gate-drain potential difference can be seen at the level of the charge transistor 38, particularly if the capacitive load associated with the output 34 is small. In

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  In this case, the transistor 38 being N-channel, there would be a return to conduction of the transistor 38 and a simultaneous conduction phenomenon. To avoid the occurrence of this phenomenon, so the transistor 42 is controlled so that it discharges the control gate of the charge transistor 38 faster than the transistor 40 discharges the output 34.

  Let Cgd be the grid-drain capacitance of a transistor, Csd its source capacitance -

  drain, Cg the equivalent capacity on the gate, Csub its substrate capacity, Cs the capacitive load connected to the output 34, C (34) the equivalent capacitance of the output 34 and Vt the threshold voltage of the N-channel transistors. transition from the load to the discharge of the output, the currents supplied by the transistors 54 and 48 will charge the gate-drain capacitances of the transistors and 44. These currents are even higher than the variation dV / dt of the signal potential. OUT2 is important. These currents reduce the gate-source potential differences of transistors 40 and 44. By reducing the resistance in the state

  passing Ron from transistor 48, a grid potential difference is applied -

  more important source for the transistor 44. In this way, we accelerate the descent

  the potential of the gate of the charge transistor 38 with respect to its source.

  We have: Cg (38) = Cgd (38) + Csd (42) + Csub (44) and

C (34) = Cs + Csd (38) + Csub (40).

  On the other hand, we have: Vgs (44) = VCC - Ron (48) * Cgd (44) * dV / dt (PCDE) and Vgs (40) = VCC - Ron (54) * Cgd (40) * dV / dt (OUT2) With regard to the passages from the discharge to the load of the outlet 34, the following conditions shall be satisfied: Ron (50) * Cgd (44) * dV / dt (PCDE) <Vt (44) and

  Ron (56) * Cgd (40) * dV / dt (OUT2) <Vt (40).

  Of course, various modifications may be made by those skilled in the art, without departing from the scope of the invention. Thus, it is possible to modify the polarity of the logic signals and / or to produce them with different logic gates. One could, for example, choose to invert the polarities of the control signals and use doors type NON_OU instead of the doors NON_ET. It will also be possible to use a logic ground for the logic circuits and an analogous ground, which is less noisy, for the power components forming the output circuit and the potential translator circuit. We

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  may also provide for safety devices. Thus, in FIG. 2, a Zener diode 84 is shown between the output 34 and the control gate of the

transistor 38.

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Claims (4)

  1 - Power output stage (30) for controlling plasma screen cells, comprising an input (32) for receiving a low voltage input logic signal (IN2), an output (34) for providing a signal high voltage output control device (OUT2), an output circuit (36) comprising, on the one hand, a load transistor (38) receiving a high voltage potential (VPP) on a drain and having a source connected to the output (34) and, on the other hand, a discharge transistor (40) receiving a reference potential (GND) on a source and having a drain connected to the output (34), and control means (42, 44, 46, 52, 58) supplying control signals (PCDE, NCDE) to the charge and discharge transistors for controlling these transistors in accordance with the input logic signal, characterized in that the charge and discharge transistors (38, 40) are of the N-channel VDMOS type, the charge transistor (38) being arranged to form a composite P-type transistor, and in that the control means are arranged so that the potential of the control gate of the charge transistor drops faster than the potential of the output when the logic signal   input controls a discharge from the output.   2 - Stage according to claim 1, characterized in that the output circuit (36) comprises, firstly, a P-channel power transistor (42) controlled by a potential translator circuit (58), said transistor P-channel receiver receiving the high voltage potential (VPP) on a source and having a drain connected to a control gate of the charge transistor (38) and, secondly, an N-channel power transistor (44) having a source receiving the reference potential (GND) and having a drain connected to the control gate of the charge transistor (38), said P-channel and N-channel transistors being controlled so that the P-channel transistor (42) is passing when it is desired to make the load transistor (38) go and the N-channel transistor (44) is on when it is desired to block the load transistor (38), and in that the control means comprise low voltage inverters (46, 52) for controlling the N-channel transistor (44) and the tr discharge transistor (40), said inverters being sized so that, on the one hand, the discharge transistor (40) is turned on after the N-channel transistor (44) is turned on, when it is desired to control discharging the output and, on the other hand, the N-channel transistor (44) is turned off after the discharge transistor (40) is off, when it is desired to control   a charge of the output through the load transistor (38).   3 - Stage according to claim 2, characterized in that the control means are dimensioned so that, when passing one of the P-channel transistors and N-channel (42, 44) of the output circuit, the other of these transistors is blocked previously, so as to avoid any conduction simultaneous of these transistors.   4 - Floor according to one of claims 1 to 3, characterized in that   comprises delay logic circuits (72, 74, 76, 78, 80) for delaying the input logic signal (IN2) so as to avoid modification of control signals (PCDE, NCDE) of the power transistors of the floor if spurious pulses of less than a given duration appear in the input logic signal.