EP1862999A2 - Control of a plasma screen - Google Patents

Abstract

The method involves connecting an intermediate supply potential application terminal to output terminals of column control stages corresponding to medium association points in series with interrupters between supply voltage application terminals, for performing a precharge or predischarge of cells of a plasma display. The output terminals are disconnected from an intermediate potential. The application terminal connection operation is delayed with respect to the disconnection of the corresponding output terminals from the application terminal. Independent claims are also included for the following: (1) a circuit for controlling a plasma display (2) a plasma display comprising a circuit for controlling a plasma display.

Description

Field of the invention

The present invention generally relates to plasma screens and, more particularly, the control of a power stage of a plasma screen.

Presentation of the prior art

A plasma screen consists of a matrix array of cells arranged at the intersection of rows and columns. Each cell of the screen comprises a cavity filled with a gas and at least two control electrodes. To create a light spot on the screen using a given cell, a potential difference is applied between its control electrodes, the gas contained in the cell being then ionized generally by means of a third electrode. This ionization is accompanied by an emission of ultraviolet rays, the creation of the luminous point being obtained by excitation of a red, green or blue luminescent material by these rays.

FIG. 1 represents, very schematically and in block form, a conventional example of a plasma screen formed of an array of cells represented in FIG. 1 by their equivalent capacitances 2. Each cell comprises two electrodes respectively connected to a line 4 and a column 6. A line control circuit 8 (SCAN) has, for each line 4, an on / off circuit having an output connected to the line in question. A column control circuit 12 comprises an element 16 (DATA) for parallelization (generally of the shift register type) of addressing data received in series (signal COL) and, for each column 6, a control circuit or stage 14 having an output O connected to the column 6 considered and receiving, on input terminals E, setpoint signals generated from the luminance data. The elements 14 and 16 are generally integrated in the same circuit 12. A general control circuit (CTRL) of the screen synchronizes the operation of the circuits 8 and 12.

The cells of the screen are activated in a line scan by means of the circuit 8. The non-activated lines are subjected to a rest potential (generally greater than 100 volts), while the activated line is brought to an activation potential (usually 0 volts). The resting potential of a column is the mass. To activate cells according to the data provided by the circuit 16 on the activated line, the corresponding columns are brought to an activation potential Vpp generally of the order of 70 volts for a given period.

The potential difference between an activated line and a column (of the order of 70 volts) makes it possible to turn on the selected cells. The third electrode (not shown in FIG. 1), called support, makes it possible to adjust the luminance of the selected cells (memory effect).

FIG. 2 illustrates, by a very schematic and partial representation of three control stages 14 _{i-1 '14} i and 14 _{i + 1} of columns C _i-1 , Ci and C _{i + 1} , a classic example of precharging or predischarging of cells of a plasma screen of the type shown in FIG. 1. The role is to limit the consumption of the screen to bring the respective electrodes of the columns to the activation potential. For example, an external capacitor with a capacitance greater than the total equivalent capacity of the panel is used to store energy when discharging a line that has just been addressed and prepare the charge for the next line. Each output terminal O of a circuit 14 is connected to the midpoint of a series connection of two switches P1 and N1 in series between two terminals. application of the activation voltage Vpp. Switches K connect the terminals O to a terminal 24 which is at a potential Vpp / 2 (for example, the first electrode of the capacitor whose other electrode is grounded). The control of the switches P1, N1 and K of each stage is organized for, between each line L _j , to recover the loads of the columns to be discharged (cells to be switched off) in favor of columns to be loaded (cells to be switched on). We then talk about burden sharing. The potential Vpp / 2 of the terminal 24 can also be obtained by an internal or external voltage source or any other means. In FIG. 2, the cumulative equivalent capacities of the cells of the columns C ₁ , C 1 and C _{1 +1} have been represented by capacities {2} _{¡-1 '} {2} _¡ and {2} _¡+1 in dashed lines.

Figure 3 shows the circuit diagram of a control circuit 14 of a column (represented by its equivalent capacity {2} in dashed lines). The switches P1 and N1 formed of MOS transistors respectively P and N channel, in series between two terminals 20 and 22 for applying the voltage Vpp, are each in parallel with a diode D16 or D18 (for example, their respective parasitic diodes). ). The anode of diode D16 is connected to the drain of transistor P1 (output terminal O of the stage), the source of transistor P1 being connected to terminal 20. The anode of diode D18 is connected to ground 22 , the source of the transistor N1 being also connected to the ground 22 and its drain being connected to the terminal O. The bidirectional switch K is formed of two N-channel MOS transistors N2 and N3 in series and common source between the terminal 24 at potential Vpp / 2 and the terminal O. Two diodes D26 and D28 corresponding for example to the parasitic diodes of transistors N2 and N3 have their respective anodes connected to the midpoint 30 of switch K. The gates of transistors N2 and N3 are connected together at the drain of a P-channel MOS transistor P2, mirrored on a P-channel MOS transistor P3. The transistor P3 is in series with a control transistor N4 and a current source 34 between the terminal 20 and the ground 22.

The control of the circuit 14 is effected by means of three signals V _H , V _L and V _M. A level shifter circuit 36 (LS), controlled by the signal V _H referenced to ground, is interposed between the terminal 20 and the gate of the transistor P1. The signal V _L is applied directly to the gate of the transistor N1 while the signal V _M is applied to that of the transistor N4. The role of the signals V _L , V _H and V _M is to control the circuit 14 to organize the precharging and predischarge of the addressed cells between the actual display periods.

FIG. 4 very schematically shows in the form of blocks an amplifier 14 and partially the column control circuit 16, to illustrate the different signals received by these circuits. The circuit 16 receives, from the circuit 10, a CSE (Charge Sharing Enable) signal for controlling the precharge or predischarge and a synchronization signal Str. The signal CSE is active at the state 1 while the signal Str indicates, by pulses at the ground, the instants of passage of the column data of the shift register of the circuit 16 to the circuits 14 for generating the signals Out.

FIGS. 5A, 5B, 5C, 5D, 5E and 5F illustrate, by timing diagrams, the operation of the amplifier 14 of FIGS. 3 and 4 for the ignition (signal DATA at 1) of a cell at the intersection of a line L _j and the column in question Ci. In FIG. 5, the preceding lines L _j-1 and following L _{j + 1} are supposed not to have to be lit for the current column (signal DATA at 0).

The signals V _L (FIG. 5C), V _M (FIG. 5D) and V _H (FIG. 5E) are generated by the circuit 16 from the signals Str (FIG. 5A) and CSE (FIG. 5B), taking into account the data to be displayed. previous columns. An example of a signal generation circuit V _L , V _M and V _H is described in US Patent Application No. 2003/0107327.

The role of the signals V _L , V _M and V _H is to control the amplifier 14 to obtain a precharge at the Vpp / 2 level of the column concerned (voltage Vout, FIG. 5F) before to complete this charge by the transistor P1. Conversely, at the end of the addressing of the column, these signals serve to organize the discharge of the cell to the terminal 24 before terminating this discharge by the transistor N1.

Assuming that the datum of the preceding line L _i-1 is 0, the signals V _M and V _H are in the low state up to the instant t 1 of the pulse of the signal Str, so that the transistors P 1 and N4 are blocked while transistor N1 is on. At a time t0, preceding the time t1 towards the end of addressing of the line L _i-1 , the signal CSE is switched to the state 1 to activate the charge transfer system. At time t1 when the signal Str switches to the low state to transfer the data of the shift register to the circuits 14, the signal V _L switches to the low state to block the transistor N1 while the signal V _M passes in the high state to turn on transistor N4. Since the terminal O is in the low state, this results in a conduction of the transistor N2 and a precharge (FIG. 5F) of the point O approximately to the level Vpp / 2 via the transistor N2 and the diode D28 then polarized live. With a capacitor providing the level Vpp / 2, the growth of the voltage Vout actually lasts until the balance of the charges between this capacitor and the equivalent capacitances of the cells of the screen addressed. At a time t2, the signal CSE returns to the low state, which causes a transition to the low state of the transistor of the signal V _M and a high transition of the signal V _H. It follows an opening of the transistor N4, whence an opening of the transistor N2 and the switch K, and a closing of the transistor P1 to complete the load of the cells of the addressed column to the level Vpp. Shortly before the end of the addressing of the current line Li (instant t0 '), the signal CSE goes back to the high state indicating an activation of the precharge or predischarge circuit. At a time t1 'that follows, the pulse on the signal Str causes the high state of the signal V _M as at time t1 and due to the desired data level 0 for the next line L _{¡+1 'V H} signal switches to the low state while the signal V _L remains there. This results in a discharge of the cells loaded at the Vpp level during the previous period until reaching the Vpp / 2 level. As for the previous period, when the signal CSE goes back to the low state (instant t2 '), this causes the continuation of the discharge at 0 by the high state of the signal V _L and the extinction of the transistor N4 (transition to the low state of the signal V _M ).

For the case where a next line in the scan order has to keep the same level, the predischarge (times t1 'to t2') does not occur.

Compared to still earlier solutions based on the use of a PMOS transistor to constitute the switch K, the use of two DMOS transistors N2 and N3 is gaining space, a switch K to be provided for each column.

However, a disadvantage of the circuit of FIG. 3 is a static consumption when the switch K is closed.

Another disadvantage is a risk of simultaneous conduction of transistors N2 and N3 and transistor P1 at time t2, causing a short circuit between supply line 20 at Vpp level and terminal 24 at Vpp / 2 level. The same problem occurs at time t2 'with mass.

The risk of simultaneous conduction is partly related to the parasitic capacitances of the gates of transistors N2 and N3 which, added to the parasitic drain capacitance of transistor P1, give rise to a delay in switching. The risk of simultaneous conduction also comes from the recovery time of diodes D26 or D28 as a function of the initial polarity of the cell.

An additional constraint in the screens of the type to which the present invention applies is that it is undesirable to multiply the number of input signals of the column control circuits which are in practice realized integrated circuit. This wish is, among other things, motivated by a need for compatibility of the column control circuit with the rest of the circuits.

Summary of the invention

The present invention aims to overcome all or part of the disadvantages of known circuit circuits of power control circuits of columns of a plasma screen.

The invention relates more particularly to the problems of simultaneous conduction of precharging transistors of the cells of such a screen with one of the transistors for supplying the bias potential to the cell in question.

The invention also provides a solution requiring no additional terminal to the column control circuit.

• une connexion d'une borne d'application d'un potentiel intermédiaire d'alimentation à des bornes de sortie d'étages de commande de colonnes correspondant aux points milieux d'associations en série de premiers et de deuxièmes interrupteurs entre deux bornes d'application d'une tension d'alimentation, pour effectuer une précharge ou une prédécharge des cellules de l'écran ;
• une déconnexion desdites bornes de sortie de ce potentiel intermédiaire ; et
• une connexion de chaque borne de sortie à un premier ou un second potentiel d'alimentation par la fermeture du premier ou second interrupteur de l'étage correspondant, en fonction d'une consigne d'adressage, retardée par rapport à la déconnexion de la borne de sortie correspondante de la borne d'application du potentiel intermédiaire.

To achieve all or part of these objects as well as others, the present invention provides a control method of a plasma screen, comprising successively, at least for all the cells of a current line to change state for the next line:

• a connection of an application terminal of an intermediate supply potential to output terminals of column control stages corresponding to the midpoint points of series associations of first and second switches between two application terminals a supply voltage, for precharging or predischarging the cells of the screen;
• disconnecting said output terminals from this intermediate potential; and
• a connection of each output terminal to a first or a second supply potential by closing the first or second switch of the corresponding stage, according to an addressing instruction, delayed with respect to the disconnection of the terminal corresponding output of the application terminal of the intermediate potential.

According to an embodiment of the present invention, the delay is obtained by a resistive cell and capacitive offset of a deactivation edge of an activation signal of the precharge or predischarge.

According to an embodiment of the present invention, said delay is chosen as a function of the parasitic diode overlap time of N-channel MOS transistors forming a switch for connecting said intermediate potential to the output terminals.

According to an embodiment of the present invention, an internal signal is generated from the activation signal of the precharge or predischarge.

According to an embodiment of the present invention, said internal signal is used to generate activation and reset signals of flip-flops placed at the output of a control signal generation circuit of said control stage switches. column.

The present invention also provides a control circuit of a column of a plasma screen.

The invention also provides a plasma screen.

Brief description of the drawings

• la figure 1 décrite précédemment représente, de façon très schématique et sous forme de blocs, un exemple d'architecture d'un écran à plasma du type auquel s'applique la présente invention ;
• la figure 2 décrite précédemment représente un exemple d'architecture classique de circuits de précharge et prédécharge du type auquel s'applique la présente invention ;
• la figure 3 décrite précédemment représente le schéma électrique d'un circuit de commande d'une colonne d'écran à plasma classique ;
• La figure 4 décrite précédemment illustre les signaux reçus par un circuit de commande de colonne classique ;
• les figures 5A, 5B, 5C, 5D, 5E et 5F illustrent par des chronogrammes un exemple de fonctionnement du circuit des figures 3 et 4 ;
• les figures 6A, 6B, 6C, 6D, 6E, 6F et 6G illustrent par des chronogrammes un mode de mise en oeuvre du procédé de commande selon la présente invention ;
• la figure 7 représente un exemple de circuit d'obtention d'un signal interne exploité par le procédé de l'invention ;
• la figure 8 représente, de façon très schématique et sous forme de blocs, un mode de réalisation d'un circuit de génération de signaux exploités par le procédé de l'invention ;
• les figures 9A, 9B, 9C, 9D et 9E illustrent un exemple d'allure de signaux internes au circuit de la figure 8 ; et
• la figure 10 représente un mode de réalisation d'un détail du circuit de la figure 8.

These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments and embodiments made in a non-limitative manner with reference to the accompanying figures in which:

• FIG. 1, previously described, very schematically and in the form of blocks, an exemplary architecture of a plasma screen of the type to which the present invention applies;
• FIG. 2 previously described represents an example of a conventional precharge and pre-discharge circuit architecture of the type to which the present invention applies;
• Figure 3 described above shows the circuit diagram of a control circuit of a conventional plasma screen column;
• Figure 4 previously described illustrates the signals received by a conventional column driver;
• FIGS. 5A, 5B, 5C, 5D, 5E and 5F illustrate, by timing diagrams, an example of operation of the circuit of FIGS. 3 and 4;
• FIGS. 6A, 6B, 6C, 6D, 6E, 6F and 6G illustrate, by timing diagrams, a mode of implementation of the control method according to the present invention;
• FIG. 7 represents an exemplary circuit for obtaining an internal signal operated by the method of the invention;
• FIG. 8 very schematically shows in the form of blocks an embodiment of a signal generation circuit operated by the method of the invention;
• FIGS. 9A, 9B, 9C, 9D and 9E illustrate an example of the appearance of signals internal to the circuit of FIG. 8; and
• FIG. 10 represents an embodiment of a detail of the circuit of FIG. 8.

The same elements have been designated by the same references to the different figures which have been drawn without respect of scale. For the sake of clarity, only the steps and elements that are useful for understanding the invention have been represented and will be written. In particular, the generation of the luminance setpoints and the generation of the scan control signals have not been represented, the invention being compatible with any conventional circuit generating such signals.

detailed description

A feature of an embodiment of the present invention is to shift the switching of the transistors providing additional charge or discharge of the screen cells relative to the opening of the precharge control switch or discharge.

Another characteristic of an embodiment of the present invention is to provide a generation of internal control signals to the column control circuit, that is, based exclusively on the data delivery and activation signals of the precharge and predischarge stage.

The present invention exploits the conventional architecture of the column control circuits as described above in connection with Figures 1, 2 and 3. For simplicity, the invention will be described later in relation to the elements and references of these figures. which will not be described again.

FIGS. 6A, 6B, 6C, 6D, 6E, 6F and 6G illustrate, by timing diagrams to be compared with those of FIGS. 5, an embodiment of the present invention. The same situation is assumed as in FIGS. 5 of a preloading requirement for displaying a line Lj with respect to a previous line L _j-1 , then a predischarge for extinguishing the next line L _{j + 1} .

As before, signals Str (FIG. 6A) for controlling the shift register of the circuit 16 (FIG. 1) and CSE (FIG. 6B) for activating the precharging or predischarge, originating from the global control circuit 10, switch at times t1. , t0 and t2, t0 ', t1' and t2. Figures 6A and 6B are identical to Figures 5A and 5B.

Still as before, the control signal V _M , of the transistor N4 (FIG. 3) is switched high at times t1 and t1 'and then at the low state at times t2 and t2', and the signals V _{L '} and V _{H '} , are switched to their respective low states according to the contents of the columns to be addressed (in this example at times t1 and t1').

According to this mode of implementation of the present invention, the time t3, respectively t3 ', of high switching of the signals V _H' , and V _L 'to close the switch P1 or N1 and to provide the complement charge or discharge, is delayed by a delay τ with respect to the instants t2 and t2 'of switching of the signal V _M' in the low state, therefore with respect to the opening command of the switch K.

The delay τ can be obtained by internal generation of a signal CSEINT common to all the circuits 14. The signal CSEINT has a rising edge triggered by the rising edge of the signal CSE (time t0) and a falling edge (time t3) delayed by to the falling edge of the CSE signal. The signal CSEINT is obtained, for example, by delaying the falling edge of the signal CSE by a duration τ by means of a resistive and capacitive cell from the signal CSE.

FIG. 7 represents an exemplary circuit for generating the signal CSEINT from the signal CSE. Other achievements are of course possible.

In this example, an OR logic gate 411 (OR) combines the signal CSE with a signal DELCSE obtained by delaying the signal CSE by means of a resistive and capacitive cell formed by a resistor R between a terminal 412 receiving the signal CSE and an input terminal of the gate 411, and a capacitor C connecting this input terminal to ground. The other terminal of the gate 411 is connected directly to the terminal 412 and the output of the gate 411 provides the signal CSEINT.

The delay τ (corresponding to the time constant of the RC cell) is chosen to enable the diodes (D26 and D28, FIG. 3) to cover before the conduction of the transistor P1 by the signal V _H. The interval between times t1 and t2 is chosen so that the level Vpp / 2 is reached at time t2 even on a maximum load (dashed in Figure 6F).

FIG. 8 very schematically shows in the form of blocks an embodiment of a circuit 40 for generating the signals V _H ', V _M ' and V _L 'from signals V _H , V _M and V _L provided by a decoding circuit 41 (DECOD) generating these signals from the signal CSE and the signal Str. An example of a circuit for obtaining the signals V _H , V _M and V _L will be described later in connection with FIG. 10. In the representation of FIG. 8, the generation of the signal CSEINT (for example by means of the circuit of FIG. 7) is assumed to be integrated in circuit 41. As illustrated in Figure 8, for each output 16i of the shift register receiving the serial data COL (addressing instructions), two flip-flops 43 and 44 are used to store two data of this column for two successive lines so as to take account, for a current line L _i , states of the previous line L _i-1 in the generation of V _H and V _L signals.

According to this embodiment of the invention, two flip-flops 44 and 45, of type D, respectively receive the signals V _H and V _L generated by the decoder 41 in the manner of the signals of FIG. 5 and supply the signals V _H '. and V _L '. The latches 44 and 45 are controlled by a Valid signal causing the passage of the present state input (signal V _H or V _L ) on the output of the flip-flop concerned. A third flip-flop 46 of the RS type receives the signal V _M and is controlled by the signal Valid. Flip-flop 46 supplies the signal V _M 'and receives a Reset reset signal. The Valid and Reset signals are generated from the signals Str, CSE and CSEINT and can be common to all the circuits 14.

FIGS. 9A, 9B, 9C, 9D and 9E illustrate an example of generation of Valid and Reset signals (FIGS. 9D and 9E) as a function of the signals of signals S1 (FIG. 9A), CSE (FIG. 9B) and CSEINT (FIG. 9C). .

The signal Valid is, for example, obtained by logical combination of signals Str, CSE and CSEINT. The Reset signal has a pulse between times t2 and t3. This signal is, for example, obtained by a logical combination of the exclusive-OR type of the CSE and CSEINT signals. On the Valid signal side, a first pulse (between instants t1 and t4) corresponds to the inverse pulse of that of signal Str and a second pulse occurs between time t3 and a moment t5 slightly later. This second pulse of the Valid signal is, for example, obtained by means of a resistive and capacitive cell. The first pulse of the Valid signal is obtained, for example, by a combination of the AND type of the CSEINT signal with the result of an OR-Exclusive combination of the signals Str and CSE.

As a variant, the durations of all the pulses of the Valid and Reset signals are fixed by resistive and capacitive cells.

The generation of the Valid and Reset signals for controlling the flip-flops 44 to 46 of FIG. 8 makes it possible to take into account the actual operating conditions of the screen and in particular the extreme conditions of the need for precharging or predischarge of the cells of the screen.

FIG. 10 represents an example of a signal generation circuit V _H , V _L and V _M. Other circuits are of course possible. In the example shown, an AND type logic gate 413 (AND) combines the signal L _j and the inverse of the signal CSEINT (inverter 414), and supplies the signal V _H. An AND type logic gate 415 (AND) receives the output of inverter 414 (inverse of signal CSEINT) and the inverse of signal L _j (inverter 416), and provides the signal V _L. The signal V _M is provided by an AND type logic gate 417 (AND) which combines the CSEINT signal with the result of an OR type logic gate 418 (OR) combining the respective results of two gates 419 and 420 (AND). ) of type ET respectively receiving the signal L _j-1 and the inverse of the signal L _j , and the inverse of the signal L _j-1 (inverter 421) and the signal L _j .

An advantage of the present invention is that it allows a simple way and without the use of additional external signals, to overcome the problems of simultaneous conduction in a plasma screen type screen.

Another advantage of the invention is that it does not detract from the advantages provided by control circuits based on DMOS transistors with respect to the use of PMOS transistors.

Another advantage of the present invention is that it is compatible with any conventional structure for addressing columns and lines of a plasma screen.

Of course, the present invention is susceptible of various variants and modifications which will appear to man art. In particular, the practical generation of signals useful for the implementation of the invention is within the abilities of those skilled in the art from the functional indications given above. For example, the active and inactive levels can be adapted according to the control circuits.

Claims (7)

A method of controlling a plasma screen, comprising successively, at least for all cells of a current line to change state for the following line: a connection (t1) of a terminal (24) for applying an intermediate supply potential (Vpp / 2) to output terminals (O) of column control stages corresponding to the midpoints of associations in series of first (P1) and second (N1) switches between two terminals (20, 22) for applying a supply voltage (Vpp), to perform a precharge or a predischarge of the cells of the screen; a disconnection (t2) of said output terminals of this intermediate potential; and a connection (t3) of each output terminal to a first (20) or second (22) supply potential by closing the first or second switch of the corresponding stage, according to an addressing instruction, characterized in that said connecting step as a function of an addressing setpoint is delayed (τ) with respect to the disconnection of the corresponding output terminal of the intermediate potential application terminal. The method of claim 1, wherein the delay (τ) is obtained by a resistive and capacitive offset cell of a deactivation front (t2) of an activation signal (CSE) of the precharge or predischarge. A method according to any one of claims 1 and 2, wherein said delay (τ) is selected as a function of the parasitic diode overlap time (D26, D28) of N-channel MOS transistors (N2, N3) forming a switch ( K) connecting said intermediate potential to the output terminals (O). A method as claimed in any one of claims 1 to 3, wherein an internal signal (CSEINT) is generated from the precharge or predischarge activation signal (CSE). The method of claim 4, wherein said internal signal (CSEINT) is used to generate activation (Reset) and reset (Reset) signals of flip-flops (44, 45, 46) placed at the output of a circuit (41). ) of generating control signals from said column control stage switches. Circuit for controlling a column of a plasma screen, characterized in that it comprises means for implementing the method according to any one of Claims 1 to 5. Plasma screen having a circuit according to claim 6.

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